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# ---------------------------------------------------------------------------

# Filename:            DE5QGen3x4If128.sdc (Qsys)

# Version:             1.00.a

# Verilog Standard:    Verilog-2001

# Description:         Synopsys Design Constraints for the DE5 board.

# These design constrains constrain the PCIE_REFCLK, and 50 MHz Clock Input

# Author:              Dustin Richmond (@darichmond)

# ----------------------------------------------------------------------------

# create_clock -name PCIE_REFCLK -period 10.000 [get_ports {PCIE_REFCLK}]

# create_clock -name osc_50MHz -period 20.000 [get_ports {OSC_BANK3D_50MHZ}]

create_clock -name {altera_reserved_tck} -period 33.333 -waveform { 0.000 16.666 } [get_ports {altera_reserved_tck}]

create_clock -name {clk_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {clk_50}]

# create_clock -name {pcie_ob_refclk_p} -period 10.000 [get_ports {pcie_ob_refclk_p}]

# create_clock -name {emif_0_pll_ref_clk_clk} -period 6.666 [ get_ports emif_0_pll_ref_clk_clk]

# derive_pll_clocks -create_base_clocks

# derive_clock_uncertainty

#**************************************************************

# Set Input Delay

#**************************************************************

set_input_delay -clock altera_reserved_tck 6 [get_ports altera_reserved_tdi]

set_input_delay -clock altera_reserved_tck 6 [get_ports altera_reserved_tms]

#**************************************************************

# Set Output Delay

#**************************************************************

set_output_delay -clock altera_reserved_tck -clock_fall -max 6 [get_ports altera_reserved_tdo]

#**************************************************************

# Set Clock Groups

#**************************************************************

set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]

set_clock_groups -asynchronous -group [get_clocks { clk_50 }]

# set_clock_groups -asynchronous -group [get_clocks { pcie_ob_refclk_p }]

# set_clock_groups -asynchronous -group [get_clocks { emif_0_pll_ref_clk_clk }]

#**************************************************************

# Set False Path

#**************************************************************

set_false_path -from * -to [get_ports {user_led_g[*]}]

set_false_path -from * -to [get_ports {user_led_r[*]}]

set_false_path -from [get_ports {altera_reserved_ntrst}]

set_false_path -from [get_ports {cpu_resetn}]

# set_false_path -from [get_ports {emif_0_oct_oct_rzqin}]

#**************************************************************

# Set Multicycle Path

#**************************************************************

#**************************************************************

# Set Maximum Delay

#**************************************************************

#**************************************************************

# Set Minimum Delay

#**************************************************************

#**************************************************************

# Set Input Transition

#**************************************************************