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//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2018 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

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//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

module

  a10gx_riffa_pcie

  #(

    C_PCI_DATA_WIDTH

  )

  (

    input  [ 7:0]  pcie_rx_p,          //PCML14  //PCIe Receive Data-req's OCT

    output [ 7:0]  pcie_tx_p,          //PCML14  //PCIe Transmit Data

    input          pcie_edge_refclk_p, //HCSL    //PCIe Clock- Terminate on MB

    input          pcie_perstn,        //1.8V    //PCIe Reset

    output         pld_clk,

    input     npor,

    output              reset_status,

    output      [7:0]   ko_cpl_spc_header,

    output      [11:0]  ko_cpl_spc_data,

    input               app_msi_req,

    output              app_msi_ack,

    output      [3:0]   tl_cfg_add,

    output      [31:0]  tl_cfg_ctl,

    output      [52:0]  tl_cfg_sts,

    output      [0:0]   rx_st_sop,

    output      [0:0]   rx_st_eop,

    output      [0:0]   rx_st_err,

    output      [0:0]   rx_st_valid,

    input               rx_st_ready,

    output      [C_PCI_DATA_WIDTH-1:0] rx_st_data,

    output      [0:0]   rx_st_empty,

    input       [0:0]   tx_st_sop,

    input       [0:0]   tx_st_eop,

    input       [0:0]   tx_st_err,

    input       [0:0]   tx_st_valid,

    output              tx_st_ready,

    input       [C_PCI_DATA_WIDTH-1:0] tx_st_data,

    input       [0:0]   tx_st_empty

  );

  // --------------------------------------------------------------------

  //

  wire                     pin_perst;

  // ----------Clocks & Locks----------

  wire                     coreclkout_hip;

  wire                     refclk;

  wire                     pld_core_ready;

  wire                     serdes_pll_locked;

  // ------------Status Interface------------

  wire                     derr_cor_ext_rcv;

  wire                     derr_cor_ext_rpl;

  wire                     derr_rpl;

  wire                     dlup;

  wire                     dlup_exit;

  wire                     ev128ns;

  wire                     ev1us;

  wire                     hotrst_exit;

  wire [3:0]               int_status;

  wire                     l2_exit;

  wire [3:0]               lane_act;

  wire [4:0]               ltssmstate;

  wire                     rx_par_err;

  wire [1:0]               tx_par_err;

  wire                     cfg_par_err;

  // ----------Clocks----------

  assign pld_clk = coreclkout_hip;

  assign refclk = pcie_edge_refclk_p;

  assign pld_core_ready = serdes_pll_locked;

  // ----------Resets----------

  assign pin_perst = pcie_perstn;

  // --------------------------------------------------------------------

  //

  wire [31:0] test_in = 32'h00000188;

  wire        simu_mode_pipe = 0;

  wire        sim_pipe_pclk_in = 0;

  wire [1:0]  sim_pipe_rate;

  wire [4:0]  sim_ltssmstate;

  wire [2:0]  eidleinfersel0;

  wire [2:0]  eidleinfersel1;

  wire [2:0]  eidleinfersel2;

  wire [2:0]  eidleinfersel3;

  wire [2:0]  eidleinfersel4;

  wire [2:0]  eidleinfersel5;

  wire [2:0]  eidleinfersel6;

  wire [2:0]  eidleinfersel7;

  wire [1:0]  powerdown0;

  wire [1:0]  powerdown1;

  wire [1:0]  powerdown2;

  wire [1:0]  powerdown3;

  wire [1:0]  powerdown4;

  wire [1:0]  powerdown5;

  wire [1:0]  powerdown6;

  wire [1:0]  powerdown7;

  wire        rxpolarity0;

  wire        rxpolarity1;

  wire        rxpolarity2;

  wire        rxpolarity3;

  wire        rxpolarity4;

  wire        rxpolarity5;

  wire        rxpolarity6;

  wire        rxpolarity7;

  wire        txcompl0;

  wire        txcompl1;

  wire        txcompl2;

  wire        txcompl3;

  wire        txcompl4;

  wire        txcompl5;

  wire        txcompl6;

  wire        txcompl7;

  wire [31:0] txdata0;

  wire [31:0] txdata1;

  wire [31:0] txdata2;

  wire [31:0] txdata3;

  wire [31:0] txdata4;

  wire [31:0] txdata5;

  wire [31:0] txdata6;

  wire [31:0] txdata7;

  wire [3:0]  txdatak0;

  wire [3:0]  txdatak1;

  wire [3:0]  txdatak2;

  wire [3:0]  txdatak3;

  wire [3:0]  txdatak4;

  wire [3:0]  txdatak5;

  wire [3:0]  txdatak6;

  wire [3:0]  txdatak7;

  wire        txdetectrx0;

  wire        txdetectrx1;

  wire        txdetectrx2;

  wire        txdetectrx3;

  wire        txdetectrx4;

  wire        txdetectrx5;

  wire        txdetectrx6;

  wire        txdetectrx7;

  wire        txelecidle0;

  wire        txelecidle1;

  wire        txelecidle2;

  wire        txelecidle3;

  wire        txelecidle4;

  wire        txelecidle5;

  wire        txelecidle6;

  wire        txelecidle7;

  wire        txdeemph0;

  wire        txdeemph1;

  wire        txdeemph2;

  wire        txdeemph3;

  wire        txdeemph4;

  wire        txdeemph5;

  wire        txdeemph6;

  wire        txdeemph7;

  wire [2:0]  txmargin0;

  wire [2:0]  txmargin1;

  wire [2:0]  txmargin2;

  wire [2:0]  txmargin3;

  wire [2:0]  txmargin4;

  wire [2:0]  txmargin5;

  wire [2:0]  txmargin6;

  wire [2:0]  txmargin7;

  wire        txswing0;

  wire        txswing1;

  wire        txswing2;

  wire        txswing3;

  wire        txswing4;

  wire        txswing5;

  wire        txswing6;

  wire        txswing7;

  wire        phystatus0 = 0;

  wire        phystatus1 = 0;

  wire        phystatus2 = 0;

  wire        phystatus3 = 0;

  wire        phystatus4 = 0;

  wire        phystatus5 = 0;

  wire        phystatus6 = 0;

  wire        phystatus7 = 0;

  wire [31:0] rxdata0 = 0;

  wire [31:0] rxdata1 = 0;

  wire [31:0] rxdata2 = 0;

  wire [31:0] rxdata3 = 0;

  wire [31:0] rxdata4 = 0;

  wire [31:0] rxdata5 = 0;

  wire [31:0] rxdata6 = 0;

  wire [31:0] rxdata7 = 0;

  wire [3:0]  rxdatak0 = 0;

  wire [3:0]  rxdatak1 = 0;

  wire [3:0]  rxdatak2 = 0;

  wire [3:0]  rxdatak3 = 0;

  wire [3:0]  rxdatak4 = 0;

  wire [3:0]  rxdatak5 = 0;

  wire [3:0]  rxdatak6 = 0;

  wire [3:0]  rxdatak7 = 0;

  wire        rxelecidle0 = 0;

  wire        rxelecidle1 = 0;

  wire        rxelecidle2 = 0;

  wire        rxelecidle3 = 0;

  wire        rxelecidle4 = 0;

  wire        rxelecidle5 = 0;

  wire        rxelecidle6 = 0;

  wire        rxelecidle7 = 0;

  wire [2:0]  rxstatus0 = 0;

  wire [2:0]  rxstatus1 = 0;

  wire [2:0]  rxstatus2 = 0;

  wire [2:0]  rxstatus3 = 0;

  wire [2:0]  rxstatus4 = 0;

  wire [2:0]  rxstatus5 = 0;

  wire [2:0]  rxstatus6 = 0;

  wire [2:0]  rxstatus7 = 0;

  wire        rxvalid0 = 0;

  wire        rxvalid1 = 0;

  wire        rxvalid2 = 0;

  wire        rxvalid3 = 0;

  wire        rxvalid4 = 0;

  wire        rxvalid5 = 0;

  wire        rxvalid6 = 0;

  wire        rxvalid7 = 0;

  wire        rxdataskip0 = 0;

  wire        rxdataskip1 = 0;

  wire        rxdataskip2 = 0;

  wire        rxdataskip3 = 0;

  wire        rxdataskip4 = 0;

  wire        rxdataskip5 = 0;

  wire        rxdataskip6 = 0;

  wire        rxdataskip7 = 0;

  wire        rxblkst0 = 0;

  wire        rxblkst1 = 0;

  wire        rxblkst2 = 0;

  wire        rxblkst3 = 0;

  wire        rxblkst4 = 0;

  wire        rxblkst5 = 0;

  wire        rxblkst6 = 0;

  wire        rxblkst7 = 0;

  wire [1:0]  rxsynchd0 = 0;

  wire [1:0]  rxsynchd1 = 0;

  wire [1:0]  rxsynchd2 = 0;

  wire [1:0]  rxsynchd3 = 0;

  wire [1:0]  rxsynchd4 = 0;

  wire [1:0]  rxsynchd5 = 0;

  wire [1:0]  rxsynchd6 = 0;

  wire [1:0]  rxsynchd7 = 0;

  wire [17:0] currentcoeff0;

  wire [17:0] currentcoeff1;

  wire [17:0] currentcoeff2;

  wire [17:0] currentcoeff3;

  wire [17:0] currentcoeff4;

  wire [17:0] currentcoeff5;

  wire [17:0] currentcoeff6;

  wire [17:0] currentcoeff7;

  wire [2:0]  currentrxpreset0;

  wire [2:0]  currentrxpreset1;

  wire [2:0]  currentrxpreset2;

  wire [2:0]  currentrxpreset3;

  wire [2:0]  currentrxpreset4;

  wire [2:0]  currentrxpreset5;

  wire [2:0]  currentrxpreset6;

  wire [2:0]  currentrxpreset7;

  wire [1:0]  txsynchd0;

  wire [1:0]  txsynchd1;

  wire [1:0]  txsynchd2;

  wire [1:0]  txsynchd3;

  wire [1:0]  txsynchd4;

  wire [1:0]  txsynchd5;

  wire [1:0]  txsynchd6;

  wire [1:0]  txsynchd7;

  wire        txblkst0;

  wire        txblkst1;

  wire        txblkst2;

  wire        txblkst3;

  wire        txblkst4;

  wire        txblkst5;

  wire        txblkst6;

  wire        txblkst7;

  wire        txdataskip0;

  wire        txdataskip1;

  wire        txdataskip2;

  wire        txdataskip3;

  wire        txdataskip4;

  wire        txdataskip5;

  wire        txdataskip6;

  wire        txdataskip7;

  wire [1:0]  rate0;

  wire [1:0]  rate1;

  wire [1:0]  rate2;

  wire [1:0]  rate3;

  wire [1:0]  rate4;

  wire [1:0]  rate5;

  wire [1:0]  rate6;

  wire [1:0]  rate7;

  wire  [1:0] currentspeed;

  wire pld_clk_inuse;

  wire testin_zero;

  wire clr_st;

  wire app_int_sts = 0;

  wire app_int_ack;

  wire [4:0] app_msi_num = 0;

  wire [2:0] app_msi_tc = 0;

  wire [7:0] rx_st_bar;

  wire rx_st_mask = 0;

  wire [11:0] tx_cred_data_fc;

  wire [5:0] tx_cred_fc_hip_cons;

  wire [5:0] tx_cred_fc_infinite;

  wire [7:0] tx_cred_hdr_fc;

  wire [1:0] tx_cred_fc_sel = 0;

  wire pm_auxpwr = 0;

  wire [9:0] pm_data = 0;

  wire pme_to_cr = 0;

  wire pm_event = 0;

  wire pme_to_sr;

  wire [4:0] hpg_ctrler = 0;

  wire [6:0] cpl_err = 0;

  wire cpl_pending = 0;

  A10GXGen2x8If128_PCIe

    A10GXGen2x8If128_PCIe_i

    (

      .rx_in0(pcie_rx_p[0]),

      .rx_in1(pcie_rx_p[1]),

      .rx_in2(pcie_rx_p[2]),

      .rx_in3(pcie_rx_p[3]),

      .rx_in4(pcie_rx_p[4]),

      .rx_in5(pcie_rx_p[5]),

      .rx_in6(pcie_rx_p[6]),

      .rx_in7(pcie_rx_p[7]),

      .tx_out0(pcie_tx_p[0]),

      .tx_out1(pcie_tx_p[1]),

      .tx_out2(pcie_tx_p[2]),

      .tx_out3(pcie_tx_p[3]),

      .tx_out4(pcie_tx_p[4]),

      .tx_out5(pcie_tx_p[5]),

      .tx_out6(pcie_tx_p[6]),

      .tx_out7(pcie_tx_p[7]),

      .*

    );

// --------------------------------------------------------------------

//

endmodule