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qaztronic |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2018 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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module
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a10gx_riffa_top
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#(// Number of RIFFA Channels
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C_NUM_CHNL = 1,
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// Number of PCIe Lanes
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C_NUM_LANES = 8,
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// Settings from Quartus IP Library
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C_PCI_DATA_WIDTH = 128,
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C_MAX_PAYLOAD_BYTES = 256,
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C_LOG_NUM_TAGS = 5,
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C_FPGA_ID = 8'hab
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)
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(
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input clk_50, //1.8V - 50MHz
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input cpu_resetn, //1.8V //CPU Reset Pushbutton (TR=0)
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output [ 7:0] user_led_g, //1.8V //User LEDs
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output [ 7:0] user_led_r, //1.8V //User LEDs
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input [ 2:0] user_pb, //1.8V //User Pushbuttons (TR=0)
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input [ 7:0] pcie_rx_p, //PCML14 //PCIe Receive Data-req's OCT
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output [ 7:0] pcie_tx_p, //PCML14 //PCIe Transmit Data
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input pcie_edge_refclk_p, //HCSL //PCIe Clock- Terminate on MB
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input pcie_perstn //1.8V //PCIe Reset
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);
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// --------------------------------------------------------------------
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localparam R_N = (C_PCI_DATA_WIDTH / 8); // width of the RIFFA bus in bytes
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localparam RR_B = 4; // number of available registers
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localparam I = 0; // TID width
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localparam D = 0; // TDEST width
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localparam U = 3; // TUSER width
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// --------------------------------------------------------------------
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wire sys_aresetn;
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wire chnl_clk;
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wire chnl_reset;
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wire chnl_reset_s;
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wire clk = chnl_clk;
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wire reset = chnl_reset_s;
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wire aclk = chnl_clk;
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wire aresetn = ~chnl_reset_s;
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sync_reset
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sync_reset_i
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(
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.clk_in(chnl_clk),
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.async_reset_in(chnl_reset),
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.sync_reset_out(chnl_reset_s)
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);
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// --------------------------------------------------------------------
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riffa_chnl_if #(.N(R_N)) chnl_bus[C_NUM_CHNL]();
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riffa_register_if #(.N(R_N), .B(RR_B)) r_if(.*);
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// --------------------------------------------------------------------
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wire npor;
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a10gx_riffa
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#(// Number of RIFFA Channels
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.C_NUM_CHNL(C_NUM_CHNL),
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// Number of PCIe Lanes
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.C_NUM_LANES(C_NUM_LANES),
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// Settings from Quartus IP Library
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.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH),
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.C_MAX_PAYLOAD_BYTES(C_MAX_PAYLOAD_BYTES),
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.C_LOG_NUM_TAGS(C_LOG_NUM_TAGS),
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.C_FPGA_ID(C_FPGA_ID)
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)
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a10gx_riffa_i(.*);
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// --------------------------------------------------------------------
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a10gx_sys #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH), .B(RR_B))
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a10gx_sys_i(.chnl_bus(chnl_bus[0]), .*);
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// --------------------------------------------------------------------
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endmodule
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