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qaztronic |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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module
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amm_checker
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#(
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A = 32, // address bus width
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N = 8, // data bus width in bytes
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B = 7 // burstcount width
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)
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(
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amm_if amm_s,
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amm_if amm_m,
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input clk, // amm_monitor_clk.clk
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input reset // amm_monitor_clk_reset.reset
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);
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// --------------------------------------------------------------------
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//
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localparam A_S = A - $clog2(N) - 1;
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// --------------------------------------------------------------------
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//
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altera_avalon_mm_monitor #(
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.AV_ADDRESS_W (A),
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.AV_SYMBOL_W (8),
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.AV_NUMSYMBOLS (N),
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.AV_BURSTCOUNT_W (B),
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.USE_READ (1),
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.USE_WRITE (1),
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.USE_ADDRESS (1),
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.USE_BYTE_ENABLE (1),
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.USE_BURSTCOUNT (1),
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.USE_READ_DATA (1),
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.USE_READ_DATA_VALID (1),
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.USE_WRITE_DATA (1),
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.USE_BEGIN_TRANSFER (0),
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.USE_BEGIN_BURST_TRANSFER (0),
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.USE_WAIT_REQUEST (1),
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.AV_CONSTANT_BURST_BEHAVIOR (1),
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.AV_BURST_LINEWRAP (0),
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.AV_BURST_BNDR_ONLY (0),
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.AV_READ_TIMEOUT (256),
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.AV_WRITE_TIMEOUT (256),
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.AV_WAITREQUEST_TIMEOUT (1024),
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.AV_MAX_PENDING_READS (3),
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.AV_MAX_PENDING_WRITES (3),
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.AV_FIX_READ_LATENCY (0),
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.AV_MAX_READ_LATENCY (100),
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.AV_MAX_WAITREQUESTED_READ (100),
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.AV_MAX_WAITREQUESTED_WRITE (100),
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.MASTER_ADDRESS_TYPE ("SYMBOLS"),
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.SLAVE_ADDRESS_TYPE ("WORDS"),
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.VHDL_ID (0),
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.AV_READRESPONSE_W (8),
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.AV_WRITERESPONSE_W (8),
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.USE_ARBITERLOCK (0),
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.USE_LOCK (0),
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.USE_DEBUGACCESS (0),
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.USE_TRANSACTIONID (0),
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.USE_WRITERESPONSE (0),
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.USE_READRESPONSE (0),
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.USE_CLKEN (0),
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.AV_MAX_CONTINUOUS_READ (5),
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.AV_MAX_CONTINUOUS_WRITE (5),
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.AV_MAX_CONTINUOUS_WAITREQUEST (5),
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.AV_MAX_CONTINUOUS_READDATAVALID (5),
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.AV_READ_WAIT_TIME (1),
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.AV_WRITE_WAIT_TIME (0),
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.REGISTER_WAITREQUEST (0),
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.AV_REGISTERINCOMINGSIGNALS (0)
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) amm_monitor (
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.clk (clk), // clk.clk
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.reset (reset), // clk_reset.reset
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.avs_waitrequest (amm_s.waitrequest), // s0.waitrequest
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.avs_write (amm_s.write), // .write
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.avs_read (amm_s.read), // .read
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.avs_address (amm_s.address[A_S:0]), // .address
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.avs_byteenable (amm_s.byteenable), // .byteenable
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.avs_burstcount (amm_s.burstcount), // .burstcount
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.avs_readdata (amm_s.readdata), // .readdata
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.avs_readdatavalid (amm_s.readdatavalid), // .readdatavalid
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.avs_writedata (amm_s.writedata), // .writedata
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.avm_waitrequest (amm_m.waitrequest), // m0.waitrequest
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.avm_write (amm_m.write), // .write
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.avm_read (amm_m.read), // .read
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.avm_address (amm_m.address), // .address
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.avm_byteenable (amm_m.byteenable), // .byteenable
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.avm_burstcount (amm_m.burstcount), // .burstcount
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.avm_readdata (amm_m.readdata), // .readdata
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.avm_readdatavalid (amm_m.readdatavalid), // .readdatavalid
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.avm_writedata (amm_m.writedata), // .writedata
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.avs_begintransfer (1'b0), // (terminated)
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.avm_begintransfer (), // (terminated)
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.avs_beginbursttransfer (1'b0), // (terminated)
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.avm_beginbursttransfer (), // (terminated)
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.avs_transactionid (8'b00000000), // (terminated)
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.avm_transactionid (), // (terminated)
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.avs_response (), // (terminated)
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.avm_response (2'b00), // (terminated)
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.avs_readid (), // (terminated)
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.avm_readid (8'b00000000), // (terminated)
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.avs_writeresponserequest (1'b0), // (terminated)
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.avm_writeresponserequest (), // (terminated)
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.avs_writeresponsevalid (), // (terminated)
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.avm_writeresponsevalid (1'b0), // (terminated)
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.avs_writeid (), // (terminated)
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.avm_writeid (8'b00000000), // (terminated)
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.avs_arbiterlock (1'b0), // (terminated)
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.avm_arbiterlock (), // (terminated)
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.avs_lock (1'b0), // (terminated)
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.avm_lock (), // (terminated)
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.avs_debugaccess (1'b0), // (terminated)
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.avm_debugaccess (), // (terminated)
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.avs_clken (1'b1), // (terminated)
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.avm_clken (), // (terminated)
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.avm_readresponse (8'b00000000), // (terminated)
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.avs_readresponse (), // (terminated)
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.avm_writeresponse (8'b00000000), // (terminated)
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.avs_writeresponse () // (terminated)
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);
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endmodule
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