Subversion Repositories qaz_libs

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////

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//// This source file may be used and distributed without         ////

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//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

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//// This source file is free software; you can redistribute it   ////

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//////////////////////////////////////////////////////////////////////

`timescale 1ps/1ps

module the_test(input tb_clk, input tb_rst);

  // --------------------------------------------------------------------

  //

  import verbosity_pkg::*;

  // --------------------------------------------------------------------

  //

  task run_the_test;

    // --------------------------------------------------------------------

    // insert test below

    // --------------------------------------------------------------------

    $display("^^^---------------------------------");

    $display("^^^ %16.t | Testbench begun.\n", $time);

    $display("^^^---------------------------------");

    // --------------------------------------------------------------------

    // --------------------------------------------------------------------

    tb_top.tb.timeout_stop(50us);

    // --------------------------------------------------------------------

    // set_verbosity(VERBOSITY_DEBUG);

    tb_top.ast_source_i.bfm.init();

    tb_top.ast_sink_i.bfm.init();

    // --------------------------------------------------------------------

    wait(~tb_rst);

    // --------------------------------------------------------------------

    #200ns;

    tb_top.ast_source_i.bfm.set_transaction_data(32'h0000_0000);

    tb_top.ast_source_i.bfm.set_transaction_sop(1);

    tb_top.ast_source_i.bfm.set_transaction_eop(0);

    tb_top.ast_source_i.bfm.push_transaction();

    tb_top.ast_source_i.bfm.set_transaction_data(32'h1111_1111);

    tb_top.ast_source_i.bfm.set_transaction_sop(0);

    tb_top.ast_source_i.bfm.set_transaction_eop(0);

    tb_top.ast_source_i.bfm.push_transaction();

    tb_top.ast_source_i.bfm.set_transaction_data(32'h2222_2222);

    tb_top.ast_source_i.bfm.set_transaction_sop(0);

    tb_top.ast_source_i.bfm.set_transaction_eop(1);

    tb_top.ast_source_i.bfm.push_transaction();

    tb_top.ast_source_i.bfm.set_transaction_data(32'h3333_3333);

    tb_top.ast_source_i.bfm.set_transaction_sop(1);

    tb_top.ast_source_i.bfm.set_transaction_eop(0);

    tb_top.ast_source_i.bfm.push_transaction();

    tb_top.ast_source_i.bfm.set_transaction_data(32'h4444_4444);

    tb_top.ast_source_i.bfm.set_transaction_sop(0);

    tb_top.ast_source_i.bfm.set_transaction_eop(0);

    tb_top.ast_source_i.bfm.push_transaction();

    tb_top.ast_source_i.bfm.set_transaction_data(32'h5555_5555);

    tb_top.ast_source_i.bfm.set_transaction_sop(0);

    tb_top.ast_source_i.bfm.set_transaction_eop(1);

    tb_top.ast_source_i.bfm.push_transaction();

    // --------------------------------------------------------------------

    #200ns;

    @(posedge tb_clk) tb_top.ast_sink_i.bfm.set_ready(1);

    @(posedge tb_clk) tb_top.ast_sink_i.bfm.set_ready(0);

    repeat(2) @(posedge tb_clk);

    tb_top.ast_sink_i.bfm.set_ready(1);

    @(posedge tb_clk) tb_top.ast_sink_i.bfm.set_ready(0);

    repeat(3) @(posedge tb_clk);

    tb_top.ast_sink_i.bfm.set_ready(1);

    repeat(3) @(posedge tb_clk);

    tb_top.ast_sink_i.bfm.set_ready(0);

    repeat(10) @(posedge tb_clk);

    tb_top.ast_sink_i.bfm.set_ready(1);

    @(posedge tb_clk) tb_top.ast_sink_i.bfm.set_ready(0);

    // --------------------------------------------------------------------

    #1us;

    // --------------------------------------------------------------------

    // insert test above

    // --------------------------------------------------------------------

  endtask

// --------------------------------------------------------------------

//

endmodule