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qaztronic |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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`timescale 1ps/1ps
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module the_test(input tb_clk, input tb_rst);
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// --------------------------------------------------------------------
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//
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import verbosity_pkg::*;
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// --------------------------------------------------------------------
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//
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task run_the_test;
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// --------------------------------------------------------------------
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// insert test below
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// --------------------------------------------------------------------
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$display("^^^---------------------------------");
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$display("^^^ %16.t | Testbench begun.\n", $time);
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$display("^^^---------------------------------");
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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tb_top.tb.timeout_stop(50us);
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// --------------------------------------------------------------------
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// set_verbosity(VERBOSITY_DEBUG);
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qaztronic |
tb_top.ast_source_i.bfm.init();
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tb_top.ast_sink_i.bfm.init();
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qaztronic |
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// --------------------------------------------------------------------
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wait(~tb_rst);
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// --------------------------------------------------------------------
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#200ns;
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tb_top.ast_source_i.bfm.set_transaction_data(32'h0000_0000);
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tb_top.ast_source_i.bfm.set_transaction_sop(1);
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tb_top.ast_source_i.bfm.set_transaction_eop(0);
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tb_top.ast_source_i.bfm.push_transaction();
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tb_top.ast_source_i.bfm.set_transaction_data(32'h1111_1111);
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tb_top.ast_source_i.bfm.set_transaction_sop(0);
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tb_top.ast_source_i.bfm.set_transaction_eop(0);
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tb_top.ast_source_i.bfm.push_transaction();
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tb_top.ast_source_i.bfm.set_transaction_data(32'h2222_2222);
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tb_top.ast_source_i.bfm.set_transaction_sop(0);
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tb_top.ast_source_i.bfm.set_transaction_eop(1);
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tb_top.ast_source_i.bfm.push_transaction();
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tb_top.ast_source_i.bfm.set_transaction_data(32'h3333_3333);
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tb_top.ast_source_i.bfm.set_transaction_sop(1);
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tb_top.ast_source_i.bfm.set_transaction_eop(0);
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tb_top.ast_source_i.bfm.push_transaction();
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tb_top.ast_source_i.bfm.set_transaction_data(32'h4444_4444);
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tb_top.ast_source_i.bfm.set_transaction_sop(0);
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tb_top.ast_source_i.bfm.set_transaction_eop(0);
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tb_top.ast_source_i.bfm.push_transaction();
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tb_top.ast_source_i.bfm.set_transaction_data(32'h5555_5555);
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tb_top.ast_source_i.bfm.set_transaction_sop(0);
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tb_top.ast_source_i.bfm.set_transaction_eop(1);
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tb_top.ast_source_i.bfm.push_transaction();
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// --------------------------------------------------------------------
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#200ns;
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@(posedge tb_clk) tb_top.ast_sink_i.bfm.set_ready(1);
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@(posedge tb_clk) tb_top.ast_sink_i.bfm.set_ready(0);
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repeat(2) @(posedge tb_clk);
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tb_top.ast_sink_i.bfm.set_ready(1);
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@(posedge tb_clk) tb_top.ast_sink_i.bfm.set_ready(0);
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repeat(3) @(posedge tb_clk);
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tb_top.ast_sink_i.bfm.set_ready(1);
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repeat(3) @(posedge tb_clk);
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tb_top.ast_sink_i.bfm.set_ready(0);
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repeat(10) @(posedge tb_clk);
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tb_top.ast_sink_i.bfm.set_ready(1);
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@(posedge tb_clk) tb_top.ast_sink_i.bfm.set_ready(0);
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// --------------------------------------------------------------------
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#1us;
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// --------------------------------------------------------------------
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// insert test above
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// --------------------------------------------------------------------
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endtask
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// --------------------------------------------------------------------
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//
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endmodule
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