OpenCores
URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

Subversion Repositories qaz_libs

[/] [qaz_libs/] [trunk/] [axi4_lib/] [src/] [axi4_if.sv] - Blame information for rev 30

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 23 qaztronic
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
4
////                                                              ////
5
//// This source file may be used and distributed without         ////
6
//// restriction provided that this copyright statement is not    ////
7
//// removed from the file and that any derivative work contains  ////
8
//// the original copyright notice and the associated disclaimer. ////
9
////                                                              ////
10
//// This source file is free software; you can redistribute it   ////
11
//// and/or modify it under the terms of the GNU Lesser General   ////
12
//// Public License as published by the Free Software Foundation; ////
13
//// either version 2.1 of the License, or (at your option) any   ////
14
//// later version.                                               ////
15
////                                                              ////
16
//// This source is distributed in the hope that it will be       ////
17
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
18
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
19
//// PURPOSE.  See the GNU Lesser General Public License for more ////
20
//// details.                                                     ////
21
////                                                              ////
22
//// You should have received a copy of the GNU Lesser General    ////
23
//// Public License along with this source; if not, download it   ////
24
//// from http://www.opencores.org/lgpl.shtml                     ////
25
////                                                              ////
26
//////////////////////////////////////////////////////////////////////
27
 
28
 
29
interface
30
  axi4_if
31
  #(
32 29 qaztronic
    A = 32, // address bus width
33
    N = 8,  // data bus width in bytes
34
    I = 1   // ID width
35 23 qaztronic
  )
36
  (
37 29 qaztronic
    input           aresetn,
38
    input           aclk
39 23 qaztronic
  );
40
 
41 29 qaztronic
  logic [(A-1):0]    araddr;
42
  logic [1:0]        arburst;
43
  logic [3:0]        arcache;
44
  logic [(I-1):0]    arid;
45
  logic [7:0]        arlen;
46
  logic              arlock;
47
  logic [2:0]        arprot;
48
  logic [3:0]        arqos;
49
  logic              arready;
50
  logic [3:0]        arregion;
51
  logic [2:0]        arsize;
52
  logic              arvalid;
53
  logic [(A-1):0]    awaddr;
54
  logic [1:0]        awburst;
55
  logic [3:0]        awcache;
56
  logic [(I-1):0]    awid;
57
  logic [7:0]        awlen;
58
  logic              awlock;
59
  logic [2:0]        awprot;
60
  logic [3:0]        awqos;
61
  logic              awready;
62
  logic [3:0]        awregion;
63
  logic [2:0]        awsize;
64
  logic              awvalid;
65
  logic [(I-1):0]    bid;
66
  logic              bready;
67
  logic [1:0]        bresp;
68
  logic              bvalid;
69
  logic [(8*N)-1:0]  rdata;
70
  logic [(I-1):0]    rid;
71
  logic              rlast;
72
  logic              rready;
73
  logic [1:0]        rresp;
74
  logic              rvalid;
75
  logic [(8*N)-1:0]  wdata;
76
  logic [(I-1):0]    wid;
77
  logic              wlast;
78
  logic              wready;
79
  logic [N-1:0]      wstrb;
80
  logic              wvalid;
81 23 qaztronic
 
82
 
83 29 qaztronic
// --------------------------------------------------------------------
84
//
85
 
86
endinterface
87
 
88
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.