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//// Copyright (C) 2017 Authors and OPENCORES.ORG                 ////

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//////////////////////////////////////////////////////////////////////

module

  axis_interleave

  #(

    N, // data bus width in bytes

    I = 1, // TID width

    D = 1, // TDEST width

    U = 1  // TUSER width

  )

  (

    axis_if axis_in [1:0],

    axis_if axis_out,

    input   aclk,

    input   aresetn

  );

  // --------------------------------------------------------------------

  //  state machine binary definitions

  enum reg [1:0]

    {

      EVEN  = 2'b01,

      ODD   = 2'b10

    } state, next_state;

  // --------------------------------------------------------------------

  //  state machine flop

  always_ff @(posedge aclk)

    if(~aresetn)

      state <= EVEN;

    else

      state <= next_state;

  // --------------------------------------------------------------------

  //  state machine

  always_comb

    case(state)

      EVEN:     if(axis_in[0].tvalid)

                  next_state <= ODD;

                else

                  next_state <= EVEN;

      ODD:      if(axis_in[1].tvalid)

                  next_state <= EVEN;

                else

                  next_state <= ODD;

      default:  next_state <= EVEN;

    endcase

  // --------------------------------------------------------------------

  //

  wire select = (state == EVEN) ? 0 : 1;

  axis_mux #(.N(N), .I(I), .D(D), .U(U))

    axis_mux_i(.*);

// --------------------------------------------------------------------

//

endmodule