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//////////////////////////////////////////////////////////////////////

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//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////

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//// This source file may be used and distributed without         ////

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//// This source file is free software; you can redistribute it   ////

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//////////////////////////////////////////////////////////////////////

module

  axis_mux

  #(

    N,      // data bus width in bytes

    I = 1,  // TID width

    D = 1,  // TDEST width

    U = 1,  // TUSER width

    USE_TSTRB = 0,  //  set to 1 to enable, 0 to disable

    USE_TKEEP = 0   //  set to 1 to enable, 0 to disable

  )

  (

    input   select,

    axis_if axis_in[1:0],

    axis_if axis_out,

    input   aclk,

    input   aresetn

  );

  // --------------------------------------------------------------------

  //

  axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_mux_out(.*);

  assign axis_in[0].tready = select ? 0                   : axis_mux_out.tready;

  assign axis_in[1].tready = select ? axis_mux_out.tready : 0;

  assign axis_mux_out.tvalid = select ? axis_in[1].tvalid : axis_in[0].tvalid;

  assign axis_mux_out.tdata  = select ? axis_in[1].tdata  : axis_in[0].tdata;

  assign axis_mux_out.tstrb  = select ? axis_in[1].tstrb  : axis_in[0].tstrb;

  assign axis_mux_out.tkeep  = select ? axis_in[1].tkeep  : axis_in[0].tkeep;

  assign axis_mux_out.tlast  = select ? axis_in[1].tlast  : axis_in[0].tlast;

  assign axis_mux_out.tid    = select ? axis_in[1].tid    : axis_in[0].tid;

  assign axis_mux_out.tdest  = select ? axis_in[1].tdest  : axis_in[0].tdest;

  assign axis_mux_out.tuser  = select ? axis_in[1].tuser  : axis_in[0].tuser;

  // --------------------------------------------------------------------

  //

  axis_register_slice

    #(

      .N(N),

      .I(I),

      .D(D),

      .U(U),

      .USE_TSTRB(0),

      .USE_TKEEP(0)

    )

    axis_register_slice_i

    (

      .axis_in(axis_mux_out), // slave

      .axis_out(axis_out),    // master

      .*

    );

// --------------------------------------------------------------------

//

endmodule