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//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////

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//////////////////////////////////////////////////////////////////////

module tb_top();

  // --------------------------------------------------------------------

  // test bench clock & reset

  wire clk_200mhz;

  wire tb_clk   = clk_200mhz;

  wire tb_rst;

  wire aclk     = tb_clk;

  wire aresetn  = ~tb_rst;

  tb_base #(.PERIOD(5_000)) tb(clk_200mhz, tb_rst);

  wire clk_100mhz;

  tb_clk #(.PERIOD(10_000)) tb_100mhz_clk(clk_100mhz);

  // --------------------------------------------------------------------

  //

  localparam DSIZE = 8;

  localparam ASIZE = 4;

  wire [DSIZE-1:0]  rdata;

  wire              wfull;

  wire              rempty;

  wire [DSIZE-1:0]  wdata = 0;

  wire              winc = 0;

  wire              wclk = clk_100mhz;

  wire              wrst_n = ~tb_rst;

  wire              rinc = 0;

  wire              rclk = clk_200mhz;

  wire              rrst_n = ~tb_rst;

  fifo1 #(.DSIZE(8), .ASIZE(4))

    dut(.*);

    // (

      // output [DSIZE-1:0]  rdata,

      // output              wfull,

      // output              rempty,

      // input [DSIZE-1:0]   wdata,

      // input winc, wclk, wrst_n,

      // input rinc, rclk, rrst_n

    // );

  // --------------------------------------------------------------------

  // sim models

  //  |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |

  // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/

  //  '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '

  // --------------------------------------------------------------------

  //

  //  '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '

  // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\

  //  |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |

  // sim models

  // --------------------------------------------------------------------

  // --------------------------------------------------------------------

  //  debug wires

  // --------------------------------------------------------------------

  // test

  the_test test( tb_clk, tb_rst );

  initial

    begin

      test.run_the_test();

      $display("^^^---------------------------------");

      $display("^^^ %16.t | Testbench done.", $time);

      $display("^^^---------------------------------");

      $display("^^^---------------------------------");

      $stop();

    end

endmodule