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qaztronic |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2018 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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class fifo_driver
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extends uvm_driver #(fifo_sequence_item);
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`uvm_component_utils(fifo_driver)
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// --------------------------------------------------------------------
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virtual fifo_if #(.W(W), .D(D)) vif;
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//--------------------------------------------------------------------
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function void set_default;
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vif.cb.wr_en <= 0;
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vif.cb.rd_en <= 0;
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vif.cb.wr_data <= 'x;
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endfunction: set_default
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//--------------------------------------------------------------------
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virtual task run_phase(uvm_phase phase);
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fifo_sequence_item item;
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super.run_phase(phase);
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set_default();
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forever
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begin
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wait(~vif.cb.reset);
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vif.zero_cycle_delay();
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seq_item_port.get_next_item(item);
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repeat(item.delay) @(vif.cb);
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if((item.command == FIFO_WR) || (item.command == FIFO_BOTH))
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begin
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if(vif.wr_full)
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`uvm_error(get_name(), "writing to full FIFO!")
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vif.cb.wr_data <= item.wr_data;
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vif.cb.wr_en <= 1;
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end
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if((item.command == FIFO_RD) || (item.command == FIFO_BOTH))
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begin
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if(vif.rd_empty)
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`uvm_error(get_name(), "reading empty FIFO!")
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item.rd_data = vif.cb.rd_data;
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vif.cb.rd_en <= 1;
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end
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@(vif.cb);
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item.wr_full = vif.wr_full;
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item.rd_empty = vif.rd_empty;
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item.count = vif.count;
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set_default();
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seq_item_port.item_done();
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end
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endtask : run_phase
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//--------------------------------------------------------------------
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function new(string name, uvm_component parent);
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super.new(name, parent);
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endfunction
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// --------------------------------------------------------------------
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endclass : fifo_driver
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