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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
 
module
  tiny_sync_fifo
  #(
    W
  )
  (
    output  reg       wr_full,
    input   [W-1:0]   wr_data,
    input             wr_en,
 
    output  reg       rd_empty,
    output  [W-1:0]   rd_data,
    input             rd_en,
 
    input             clk,
    input             reset
  );
 
  // --------------------------------------------------------------------
  //
  wire  writing = wr_en & ~wr_full;
  wire  reading = rd_en & ~rd_empty;
 
 
  // --------------------------------------------------------------------
  //
  reg [1:0] rd_ptr_r;
  reg [1:0] next_rd_ptr_r;
 
  always_comb
    if(reset)
      next_rd_ptr_r = 0;
    else if(reading)
      next_rd_ptr_r = rd_ptr_r + 1;
    else
      next_rd_ptr_r = rd_ptr_r;
 
  always_ff @(posedge clk)
    rd_ptr_r <= next_rd_ptr_r;
 
 
  // --------------------------------------------------------------------
  //
  reg [1:0] wr_ptr_r;
  reg [1:0] next_wr_ptr_r;
 
  always_comb
    if(reset)
      next_wr_ptr_r = 0;
    else if(writing)
      next_wr_ptr_r = wr_ptr_r + 1;
    else
      next_wr_ptr_r = wr_ptr_r;
 
  always_ff @(posedge clk)
    wr_ptr_r <= next_wr_ptr_r;
 
 
  // --------------------------------------------------------------------
  //
  wire empty_w = (next_wr_ptr_r == next_rd_ptr_r);
 
  always_ff @(posedge clk)
    if(reset)
      rd_empty <= 1;
    else
      rd_empty <= empty_w;
 
 
  // --------------------------------------------------------------------
  //
  wire full_w = ({~next_wr_ptr_r[1],next_wr_ptr_r[0]} == next_rd_ptr_r);
 
  always_ff @(posedge clk)
    if(reset)
      wr_full <= 0;
    else
      wr_full <= full_w;
 
 
  // --------------------------------------------------------------------
  //
  reg   [W-1:0] data_0_r;
  reg   [W-1:0] data_1_r;
  wire  [W-1:0] wr_data_mux = rd_ptr_r[0] ? data_1_r : data_0_r;
  assign rd_data = wr_data_mux;
 
  always_ff @(posedge clk)
    if(writing)
      if(wr_ptr_r[0])
        data_1_r <= wr_data;
      else
        data_0_r <= wr_data;
 
 
// --------------------------------------------------------------------
// synthesis translate_off
  always_ff @(posedge clk)
    if(wr_en & wr_full)
      $stop;
  always_ff @(posedge clk)
    if(rd_en & rd_empty)
      $stop;
// synthesis translate_on
// --------------------------------------------------------------------
 
 
// --------------------------------------------------------------------
//
endmodule

Line No.	Rev	Author	Line
1	34	qaztronic	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Copyright (C) 2015 Authors and OPENCORES.ORG ////`
4			`//// ////`
5			`//// This source file may be used and distributed without ////`
6			`//// restriction provided that this copyright statement is not ////`
7			`//// removed from the file and that any derivative work contains ////`
8			`//// the original copyright notice and the associated disclaimer. ////`
9			`//// ////`
10			`//// This source file is free software; you can redistribute it ////`
11			`//// and/or modify it under the terms of the GNU Lesser General ////`
12			`//// Public License as published by the Free Software Foundation; ////`
13			`//// either version 2.1 of the License, or (at your option) any ////`
14			`//// later version. ////`
15			`//// ////`
16			`//// This source is distributed in the hope that it will be ////`
17			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
18			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
19			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
20			`//// details. ////`
21			`//// ////`
22			`//// You should have received a copy of the GNU Lesser General ////`
23			`//// Public License along with this source; if not, download it ////`
24			`//// from http://www.opencores.org/lgpl.shtml ////`
25			`//// ////`
26			`//////////////////////////////////////////////////////////////////////`
27
28
29			`module`
30			`tiny_sync_fifo`
31			`#(`
32	36	qaztronic	`W`
33	34	qaztronic	`)`
34			`(`
35			`output reg wr_full,`
36			`input [W-1:0] wr_data,`
37			`input wr_en,`
38
39			`output reg rd_empty,`
40			`output [W-1:0] rd_data,`
41			`input rd_en,`
42
43			`input clk,`
44			`input reset`
45			`);`
46
47			`// --------------------------------------------------------------------`
48			`//`
49			`wire writing = wr_en & ~wr_full;`
50			`wire reading = rd_en & ~rd_empty;`
51
52
53			`// --------------------------------------------------------------------`
54			`//`
55			`reg [1:0] rd_ptr_r;`
56			`reg [1:0] next_rd_ptr_r;`
57
58			`always_comb`
59			`if(reset)`
60			`next_rd_ptr_r = 0;`
61			`else if(reading)`
62			`next_rd_ptr_r = rd_ptr_r + 1;`
63			`else`
64			`next_rd_ptr_r = rd_ptr_r;`
65
66			`always_ff @(posedge clk)`
67			`rd_ptr_r <= next_rd_ptr_r;`
68
69
70			`// --------------------------------------------------------------------`
71			`//`
72			`reg [1:0] wr_ptr_r;`
73			`reg [1:0] next_wr_ptr_r;`
74
75			`always_comb`
76			`if(reset)`
77			`next_wr_ptr_r = 0;`
78			`else if(writing)`
79			`next_wr_ptr_r = wr_ptr_r + 1;`
80			`else`
81			`next_wr_ptr_r = wr_ptr_r;`
82
83			`always_ff @(posedge clk)`
84			`wr_ptr_r <= next_wr_ptr_r;`
85
86
87			`// --------------------------------------------------------------------`
88			`//`
89			`wire empty_w = (next_wr_ptr_r == next_rd_ptr_r);`
90
91			`always_ff @(posedge clk)`
92			`if(reset)`
93			`rd_empty <= 1;`
94			`else`
95			`rd_empty <= empty_w;`
96
97
98			`// --------------------------------------------------------------------`
99			`//`
100			`wire full_w = ({~next_wr_ptr_r[1],next_wr_ptr_r[0]} == next_rd_ptr_r);`
101
102			`always_ff @(posedge clk)`
103			`if(reset)`
104			`wr_full <= 0;`
105			`else`
106			`wr_full <= full_w;`
107
108
109			`// --------------------------------------------------------------------`
110			`//`
111	36	qaztronic	`reg [W-1:0] data_0_r;`
112			`reg [W-1:0] data_1_r;`
113			`wire [W-1:0] wr_data_mux = rd_ptr_r[0] ? data_1_r : data_0_r;`
114	34	qaztronic	`assign rd_data = wr_data_mux;`
115
116			`always_ff @(posedge clk)`
117			`if(writing)`
118			`if(wr_ptr_r[0])`
119			`data_1_r <= wr_data;`
120			`else`
121			`data_0_r <= wr_data;`
122
123
124			`// --------------------------------------------------------------------`
125			`// synthesis translate_off`
126			`always_ff @(posedge clk)`
127			`if(wr_en & wr_full)`
128			`$stop;`
129			`always_ff @(posedge clk)`
130			`if(rd_en & rd_empty)`
131			`$stop;`
132			`// synthesis translate_on`
133			`// --------------------------------------------------------------------`
134
135
136			`// --------------------------------------------------------------------`
137			`//`
138			`endmodule`

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[/] [qaz_libs/] [trunk/] [basal/] [src/] [FIFOs/] [tiny_sync_fifo.sv] - Blame information for rev 47