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//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2019 Authors and OPENCORES.ORG                 ////

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//// This source file may be used and distributed without         ////

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//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

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//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

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//////////////////////////////////////////////////////////////////////

module

  axis_rom

  #(

    int N,

    int A,

    string FILE_NAME,

    int START=0,

    int STOP=2**A

  )

  (

    axis_if axis_out,

    input   aclk,

    input   aresetn

  );

  // --------------------------------------------------------------------

  wire wr_full;

  wire rd_empty;

  wire rd_en = axis_out.tready & axis_out.tvalid;

  // --------------------------------------------------------------------

  enum reg [2:0]

    {

      INIT    = 3'b001,

      STALLED = 3'b010,

      PRIMED  = 3'b100

    } state, next_state;

  // --------------------------------------------------------------------

  always_ff @(posedge aclk)

    if(~aresetn)

      state <= INIT;

    else

      state <= next_state;

  // --------------------------------------------------------------------

  always_comb

    case(state)

      INIT:       next_state <= STALLED;

      STALLED:    if(~wr_full)

                    next_state <= PRIMED;

                  else

                    next_state <= STALLED;

      PRIMED:     if(rd_empty | (~wr_full & rd_en))

                    next_state <= PRIMED;

                  else

                    next_state <= STALLED;

      default:    next_state <= INIT;

    endcase

  // --------------------------------------------------------------------

  wire [(N*8)-1:0]  q;

  reg [(A-1):0] addr;

  rom #((N*8), A, FILE_NAME) rom(.clk(aclk), .*);

  // --------------------------------------------------------------------

  wire [N*8:0] wr_data;

  wire [N*8:0] rd_data;

  wire wr_en = (state == PRIMED);

  tiny_sync_fifo #((N*8)+1) fifo(.clk(aclk), .reset(~aresetn), .*);

  // --------------------------------------------------------------------

  reg increment;

  always_comb

    case({state, next_state})

      {STALLED,  PRIMED}: increment <= 1;

      {PRIMED,   PRIMED}: increment <= 1;

      default:            increment <= 0;

    endcase

  // --------------------------------------------------------------------

  wire stop = increment & (addr >= STOP - START - 1);

  always_ff @(posedge aclk)

    if(~aresetn | stop)

      addr <= 0;

    else if(increment)

      addr <= addr + 1;

  // --------------------------------------------------------------------

  reg tlast;

  always_ff @(posedge aclk)

    if(stop)

      tlast <= 1;

    else if(~aresetn | wr_en)

      tlast <= 0;

  // --------------------------------------------------------------------

  assign axis_out.tvalid = ~rd_empty;

  assign {axis_out.tlast, axis_out.tdata} = rd_data;

  assign wr_data = {tlast, q};

// --------------------------------------------------------------------

endmodule