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//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////

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//////////////////////////////////////////////////////////////////////

module

  sr_latch

  (

    input       set,

    input       reset,

    output reg  out,

    input       clock

  );

  // --------------------------------------------------------------------

  //

  always @(posedge clock)

    if(reset)

      out <= 0;

    else if(set)

      out <= 1;

endmodule