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//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////

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//////////////////////////////////////////////////////////////////////

module

  synchronizer

  #(

    parameter SIZE = 32

  )

  (

    input       [SIZE-1:0]  in,

    output reg  [SIZE-1:0]  out,

    input                   in_clock,

    input                   out_clock

  );

  // --------------------------------------------------------------------

  //  in sync flop

  reg [SIZE-1:0] in_r;

  always @(posedge in_clock)

    in_r <= in;

  // --------------------------------------------------------------------

  //  out sync flops

  reg [SIZE-1:0] out_r;

  always @(posedge out_clock)

  begin

    out_r   <= in_r;

    out     <= out_r;

  end

endmodule