OpenCores
URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

Subversion Repositories qaz_libs

[/] [qaz_libs/] [trunk/] [coaxpress/] [cx_bit_align.v] - Blame information for rev 30

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 qaztronic
//
2
//
3
//
4
 
5
 
6
module
7
  cx_bit_align
8
  (
9
    input               data_in,
10
    output reg  [9:0]   data_out,
11
    output              clock,
12
    output              strobe,
13
    input               data_sent_lsb,
14
    input               reset
15
  );
16
 
17
  // using big endian as presented in US4,486,739
18
  localparam K27_7_10b = 10'b110110_1000;  //  K27.7 Start of data packet indication
19
  localparam K28_0_10b = 10'b001111_0100;  //  K28.0 GPIO indication
20
  localparam K28_6_10b = 10'b001111_0110;  //  K28.6 I/O acknowledgement
21
  localparam K28_1_10b = 10'b001111_1001;  //  K28.1 Used for alignment
22
  localparam K28_2_10b = 10'b001111_0101;  //  K28.2 Rising trigger indication
23
  localparam K28_3_10b = 10'b001111_0011;  //  K28.3 Stream marker – see section 7.2
24
  localparam K28_4_10b = 10'b001111_0010;  //  K28.4 Falling trigger indication
25
  localparam K28_5_10b = 10'b001111_1010;  //  K28.5 Used for alignment
26
  localparam K28_7_10b = 10'b001111_1000;  //  K29.7 End of data packet indication
27
 
28
  localparam D21_5_10b = 10'b101010_1010;
29
 
30
//  wire clock_n;
31
//  assign  clock = clock_n;
32
 
33
  // --------------------------------------------------------------------
34
  //
35
  recover_clock
36
    i_recover_clock
37
    (
38
      .in(data_in),
39
      .clock(clock)
40
    );
41
 
42
 
43
  // --------------------------------------------------------------------
44
  // four word shift register
45
  reg [39:0] data_in_r;
46
 
47
  always @( negedge clock )
48
    if( data_sent_lsb )
49
      data_in_r <= { data_in_r[38:0], data_in };
50
    else
51
      data_in_r <= { data_in, data_in_r[39:1] };
52
 
53
 
54
  // --------------------------------------------------------------------
55
  //
56
  integer bit_count = 0;
57
 
58
  always @( negedge clock )
59
    if( bit_count == 9 )
60
      bit_count <= 0;
61
    else
62
      bit_count <= bit_count + 1;
63
 
64
 
65
  // --------------------------------------------------------------------
66
  //
67
  wire p3_is_D21_5_msb = (data_in_r[39:30] == D21_5_10b) | (data_in_r[39:30]  == ~D21_5_10b);
68
  wire p2_is_K28_1_msb = (data_in_r[29:20] == K28_1_10b) | (data_in_r[29:20]  == ~K28_1_10b);
69
  wire p1_is_K28_1_msb = (data_in_r[19:10] == K28_1_10b) | (data_in_r[19:10]  == ~K28_1_10b);
70
  wire p0_is_K28_5_msb = (data_in_r[9:0]   == K28_5_10b) | (data_in_r[9:0]    == ~K28_5_10b);
71
 
72
  wire p3_is_D21_5_lsb = (data_in_r[9:0]    == D21_5_10b) | (data_in_r[9:0]    == ~D21_5_10b);
73
  wire p2_is_K28_1_lsb = (data_in_r[19:10]  == K28_1_10b) | (data_in_r[19:10]  == ~K28_1_10b);
74
  wire p1_is_K28_1_lsb = (data_in_r[29:20]  == K28_1_10b) | (data_in_r[29:20]  == ~K28_1_10b);
75
  wire p0_is_K28_5_lsb = (data_in_r[39:30]  == K28_5_10b) | (data_in_r[39:30]  == ~K28_5_10b);
76
 
77
  wire found_idle_word = data_sent_lsb ?  (p0_is_K28_5_lsb & p1_is_K28_1_lsb & p2_is_K28_1_lsb & p3_is_D21_5_lsb) :
78
                                          (p0_is_K28_5_msb & p1_is_K28_1_msb & p2_is_K28_1_msb & p3_is_D21_5_msb);
79
 
80
  integer bit_select = 'hx;
81
 
82
  always @( posedge clock )
83
    if( reset )
84
      bit_select <= 'hx;
85
    else if( found_idle_word )
86
      bit_select <= bit_count;
87
 
88
 
89
  // --------------------------------------------------------------------
90
  //  register parallel outputs in litle endian bit order
91
  integer i;
92
 
93
  always @( posedge clock )
94
    if( bit_count == bit_select )
95
      for( i = 0; i < 10; i = i + 1 )
96
        data_out[i] <= data_in_r[9-i];
97
 
98
 
99
  // --------------------------------------------------------------------
100
  // debug  --  look for control codes
101
`ifdef DEBUG_COAXPRESS
102
  wire dbg_p0_is_K27_7 = (data_in_r[9:0]   == K27_7_10b) | (data_in_r[9:0]    == ~K27_7_10b);
103
  wire dbg_p0_is_K28_0 = (data_in_r[9:0]   == K28_0_10b) | (data_in_r[9:0]    == ~K28_0_10b);
104
  wire dbg_p0_is_K28_6 = (data_in_r[9:0]   == K28_6_10b) | (data_in_r[9:0]    == ~K28_6_10b);
105
  wire dbg_p0_is_K28_1 = (data_in_r[9:0]   == K28_1_10b) | (data_in_r[9:0]    == ~K28_1_10b);
106
  wire dbg_p0_is_K28_2 = (data_in_r[9:0]   == K28_2_10b) | (data_in_r[9:0]    == ~K28_2_10b);
107
  wire dbg_p0_is_K28_3 = (data_in_r[9:0]   == K28_3_10b) | (data_in_r[9:0]    == ~K28_3_10b);
108
  wire dbg_p0_is_K28_4 = (data_in_r[9:0]   == K28_4_10b) | (data_in_r[9:0]    == ~K28_4_10b);
109
  wire dbg_p0_is_K28_5 = (data_in_r[9:0]   == K28_5_10b) | (data_in_r[9:0]    == ~K28_5_10b);
110
  wire dbg_p0_is_K28_7 = (data_in_r[9:0]   == K28_7_10b) | (data_in_r[9:0]    == ~K28_7_10b);
111
  wire dbg_p0_is_D21_5 = (data_in_r[9:0]   == D21_5_10b) | (data_in_r[9:0]    == ~D21_5_10b);
112
 
113
  // debug  --  four word shift register, reverse bit order
114
  reg [39:0] dbg_data_in_n_r;
115
 
116
  always @( negedge clock )
117
    dbg_data_in_n_r <= { data_in, dbg_data_in_n_r[39:1] };
118
 
119
  wire dbg_p0_is_K27_7_n = (dbg_data_in_n_r[9:0]   == K27_7_10b) | (dbg_data_in_n_r[9:0]    == ~K27_7_10b);
120
  wire dbg_p0_is_K28_0_n = (dbg_data_in_n_r[9:0]   == K28_0_10b) | (dbg_data_in_n_r[9:0]    == ~K28_0_10b);
121
  wire dbg_p0_is_K28_6_n = (dbg_data_in_n_r[9:0]   == K28_6_10b) | (dbg_data_in_n_r[9:0]    == ~K28_6_10b);
122
  wire dbg_p0_is_K28_1_n = (dbg_data_in_n_r[9:0]   == K28_1_10b) | (dbg_data_in_n_r[9:0]    == ~K28_1_10b);
123
  wire dbg_p0_is_K28_2_n = (dbg_data_in_n_r[9:0]   == K28_2_10b) | (dbg_data_in_n_r[9:0]    == ~K28_2_10b);
124
  wire dbg_p0_is_K28_3_n = (dbg_data_in_n_r[9:0]   == K28_3_10b) | (dbg_data_in_n_r[9:0]    == ~K28_3_10b);
125
  wire dbg_p0_is_K28_4_n = (dbg_data_in_n_r[9:0]   == K28_4_10b) | (dbg_data_in_n_r[9:0]    == ~K28_4_10b);
126
  wire dbg_p0_is_K28_5_n = (dbg_data_in_n_r[9:0]   == K28_5_10b) | (dbg_data_in_n_r[9:0]    == ~K28_5_10b);
127
  wire dbg_p0_is_K28_7_n = (dbg_data_in_n_r[9:0]   == K28_7_10b) | (dbg_data_in_n_r[9:0]    == ~K28_7_10b);
128
 
129
  // debug  --  assume bit select
130
  reg [9:0] dbg_data_out;
131
 
132
  always @( posedge clock )
133
    if( bit_count == 2 )
134
      dbg_data_out <= data_in_r[9:0];
135
 
136
  wire dbg_data_out_K28_5 = (dbg_data_out   == K28_5_10b) | (dbg_data_out    == ~K28_5_10b);
137
  wire dbg_data_out_K28_1 = (dbg_data_out   == K28_1_10b) | (dbg_data_out    == ~K28_1_10b);
138
  wire dbg_data_out_D21_5 = (dbg_data_out   == D21_5_10b) | (dbg_data_out    == ~D21_5_10b);
139
`endif
140
 
141
 
142
  // --------------------------------------------------------------------
143
  //  register parallel outputs in litle endian bit order
144
  assign strobe = (bit_count === bit_select);
145
 
146
endmodule
147
 
148
 
149
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.