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[/] [qaz_libs/] [trunk/] [scripts/] [sim_procs.do] - Blame information for rev 50

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# //////////////////////////////////////////////////////////////////////
# ////                                                              ////
# //// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
# ////                                                              ////
# //// This source file may be used and distributed without         ////
# //// restriction provided that this copyright statement is not    ////
# //// removed from the file and that any derivative work contains  ////
# //// the original copyright notice and the associated disclaimer. ////
# ////                                                              ////
# //// This source file is free software; you can redistribute it   ////
# //// and/or modify it under the terms of the GNU Lesser General   ////
# //// Public License as published by the Free Software Foundation; ////
# //// either version 2.1 of the License, or (at your option) any   ////
# //// later version.                                               ////
# ////                                                              ////
# //// This source is distributed in the hope that it will be       ////
# //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
# //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
# //// PURPOSE.  See the GNU Lesser General Public License for more ////
# //// details.                                                     ////
# ////                                                              ////
# //// You should have received a copy of the GNU Lesser General    ////
# //// Public License along with this source; if not, download it   ////
# //// from http://www.opencores.org/lgpl.shtml                     ////
# ////                                                              ////
# //////////////////////////////////////////////////////////////////////
 
 
# ------------------------------------
#
proc sim_compile_lib {lib target} {
 
  global env
 
  echo "INFO: compiling $target rtl"
 
  foreach filename [glob -nocomplain -directory ${lib}/sim/libs/${target}_verilog/ *.f] {
    echo "INFO: compiling $filename"
    vlog -f $filename
  }
 
  foreach filename [glob -nocomplain -directory ${lib}/sim/libs/${target}_VHDL/ *.f] {
    echo "INFO: compiling $filename"
    vcom -explicit -f $filename
  }
}
 
 
# ------------------------------------
#
proc sim_compile_all { target } {
 
  global env
 
  echo "INFO: compiling $target rtl"
 
  foreach filename [glob -nocomplain -directory ../../libs/${target}_verilog/ *.f] {
    echo "INFO: compiling $filename"
    vlog -f $filename
  }
 
  foreach filename [glob -nocomplain -directory ../../libs/${target}_VHDL/ *.f] {
    echo "INFO: compiling $filename"
    vcom -explicit -f $filename
  }
}
 
 
# ------------------------------------
#
proc sim_run_sim {  } {
 
  if { [file exists ./pre_sim.do] } {
    echo "INFO: found ./pre_sim.do"
    do ./pre_sim.do
  }
 
  if {[file exists ./sim.do]} {
    do ./sim.do
  } elseif {[file exists ../../libs/sim.do]} {
    do ../../libs/sim.do
  } elseif {[file exists ../../libs/altera_sim.f]} {
    vsim -novopt -f ../../libs/altera_sim.f -l transcript.txt work.tb_top
  } elseif {[file exists ../../libs/xilinx_sim.f]} {
    vsim -novopt -f ../../libs/xilinx_sim.f -l transcript.txt work.tb_top work.glbl
  }
 
  if { [file exists ./wave.do] } {
    do ./wave.do
  }
 
  if { [file exists ./post_sim.do] } {
    echo "INFO: found ./post_sim.do"
    do ./post_sim.do
  }
}
 
 
# ------------------------------------
#
proc sim_run_test {  } {
 
  global env
 
  # unique setup
  if { [file exists ./setup_test.do] } {
    do ./setup_test.do
  }
 
  if { [info exists env(MAKEFILE_TEST_RUN)] } {
    vlog +define+MAKEFILE_TEST_RUN ../../src/tb_top.v
  } else {
    sim_run_sim
  }
 
  run -all
}
 
 
# ------------------------------------
#
proc sim_restart {  } {
 
  global env
 
  # work in progress files to compile
  if { [file exists ./wip.do] } {
    echo "INFO: found ./wip.do"
    do ./wip.do
  }
 
  if { [file exists ./pre_sim.do] } {
    echo "INFO: found ./pre_sim.do"
    do ./pre_sim.do
  }
 
  if { [string equal nodesign [runStatus]] } {
    sim_run_sim
  } else {
    restart -force
  }
 
  run -all
  echo "INFO: run -all done."
 
  if { [file exists ./post_sim.do] } {
    echo "INFO: found ./post_sim.do"
    do ./post_sim.do
  }
}
 
 
# ------------------------------------
#
proc make_lib { lib {rebuild 0} } {
 
  if {[file exists $lib/_info]} {
    echo "INFO: Simulation library $lib already exists"
 
    if { $rebuild != 0 } {
      echo "INFO: Rebuilding library. Deleting ./$lib and recompiling all"
      quit -sim
      file delete -force ./$lib
      vlib $lib
      vmap $lib $lib
    }
 
  } else {
      vlib $lib
      vmap $lib $lib
  }
}

Line No.	Rev	Author	Line
1	23	qaztronic	`# //////////////////////////////////////////////////////////////////////`
2			`# //// ////`
3			`# //// Copyright (C) 2015 Authors and OPENCORES.ORG ////`
4			`# //// ////`
5			`# //// This source file may be used and distributed without ////`
6			`# //// restriction provided that this copyright statement is not ////`
7			`# //// removed from the file and that any derivative work contains ////`
8			`# //// the original copyright notice and the associated disclaimer. ////`
9			`# //// ////`
10			`# //// This source file is free software; you can redistribute it ////`
11			`# //// and/or modify it under the terms of the GNU Lesser General ////`
12			`# //// Public License as published by the Free Software Foundation; ////`
13			`# //// either version 2.1 of the License, or (at your option) any ////`
14			`# //// later version. ////`
15			`# //// ////`
16			`# //// This source is distributed in the hope that it will be ////`
17			`# //// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
18			`# //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
19			`# //// PURPOSE. See the GNU Lesser General Public License for more ////`
20			`# //// details. ////`
21			`# //// ////`
22			`# //// You should have received a copy of the GNU Lesser General ////`
23			`# //// Public License along with this source; if not, download it ////`
24			`# //// from http://www.opencores.org/lgpl.shtml ////`
25			`# //// ////`
26			`# //////////////////////////////////////////////////////////////////////`
27
28
29			`# ------------------------------------`
30			`#`
31	31	qaztronic	`proc sim_compile_lib {lib target} {`
32
33			`global env`
34
35			`echo "INFO: compiling $target rtl"`
36	36	qaztronic
37	31	qaztronic	`foreach filename [glob -nocomplain -directory ${lib}/sim/libs/${target}_verilog/ *.f] {`
38			`echo "INFO: compiling $filename"`
39			`vlog -f $filename`
40			`}`
41	36	qaztronic
42	31	qaztronic	`foreach filename [glob -nocomplain -directory ${lib}/sim/libs/${target}_VHDL/ *.f] {`
43			`echo "INFO: compiling $filename"`
44			`vcom -explicit -f $filename`
45			`}`
46			`}`
47
48
49			`# ------------------------------------`
50			`#`
51	23	qaztronic	`proc sim_compile_all { target } {`
52
53			`global env`
54
55			`echo "INFO: compiling $target rtl"`
56	36	qaztronic
57	23	qaztronic	`foreach filename [glob -nocomplain -directory ../../libs/${target}_verilog/ *.f] {`
58			`echo "INFO: compiling $filename"`
59			`vlog -f $filename`
60			`}`
61	36	qaztronic
62	23	qaztronic	`foreach filename [glob -nocomplain -directory ../../libs/${target}_VHDL/ *.f] {`
63			`echo "INFO: compiling $filename"`
64			`vcom -explicit -f $filename`
65			`}`
66			`}`
67
68
69			`# ------------------------------------`
70			`#`
71			`proc sim_run_sim { } {`
72
73	36	qaztronic	`if { [file exists ./pre_sim.do] } {`
74			`echo "INFO: found ./pre_sim.do"`
75			`do ./pre_sim.do`
76			`}`
77
78	23	qaztronic	`if {[file exists ./sim.do]} {`
79			`do ./sim.do`
80			`} elseif {[file exists ../../libs/sim.do]} {`
81			`do ../../libs/sim.do`
82			`} elseif {[file exists ../../libs/altera_sim.f]} {`
83			`vsim -novopt -f ../../libs/altera_sim.f -l transcript.txt work.tb_top`
84			`} elseif {[file exists ../../libs/xilinx_sim.f]} {`
85			`vsim -novopt -f ../../libs/xilinx_sim.f -l transcript.txt work.tb_top work.glbl`
86			`}`
87	36	qaztronic
88	23	qaztronic	`if { [file exists ./wave.do] } {`
89			`do ./wave.do`
90			`}`
91	36	qaztronic
92			`if { [file exists ./post_sim.do] } {`
93			`echo "INFO: found ./post_sim.do"`
94			`do ./post_sim.do`
95			`}`
96	23	qaztronic	`}`
97
98
99			`# ------------------------------------`
100			`#`
101			`proc sim_run_test { } {`
102
103			`global env`
104
105			`# unique setup`
106			`if { [file exists ./setup_test.do] } {`
107			`do ./setup_test.do`
108			`}`
109
110			`if { [info exists env(MAKEFILE_TEST_RUN)] } {`
111			`vlog +define+MAKEFILE_TEST_RUN ../../src/tb_top.v`
112			`} else {`
113			`sim_run_sim`
114			`}`
115
116			`run -all`
117			`}`
118
119
120			`# ------------------------------------`
121			`#`
122			`proc sim_restart { } {`
123
124			`global env`
125
126			`# work in progress files to compile`
127			`if { [file exists ./wip.do] } {`
128			`echo "INFO: found ./wip.do"`
129			`do ./wip.do`
130			`}`
131	36	qaztronic
132			`if { [file exists ./pre_sim.do] } {`
133			`echo "INFO: found ./pre_sim.do"`
134			`do ./pre_sim.do`
135			`}`
136
137	23	qaztronic	`if { [string equal nodesign [runStatus]] } {`
138			`sim_run_sim`
139			`} else {`
140			`restart -force`
141			`}`
142
143			`run -all`
144	36	qaztronic	`echo "INFO: run -all done."`
145
146			`if { [file exists ./post_sim.do] } {`
147			`echo "INFO: found ./post_sim.do"`
148			`do ./post_sim.do`
149			`}`
150	23	qaztronic	`}`
151
152
153			`# ------------------------------------`
154			`#`
155			`proc make_lib { lib {rebuild 0} } {`
156
157			`if {[file exists $lib/_info]} {`
158			`echo "INFO: Simulation library $lib already exists"`
159	36	qaztronic
160	23	qaztronic	`if { $rebuild != 0 } {`
161			`echo "INFO: Rebuilding library. Deleting ./$lib and recompiling all"`
162			`quit -sim`
163			`file delete -force ./$lib`
164			`vlib $lib`
165			`vmap $lib $lib`
166			`}`
167	36	qaztronic
168	23	qaztronic	`} else {`
169			`vlib $lib`
170			`vmap $lib $lib`
171			`}`
172			`}`

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[/] [qaz_libs/] [trunk/] [scripts/] [sim_procs.do] - Blame information for rev 50