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qaztronic |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2019 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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module
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avf_line_buffer_merge #(N, U, L)
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(
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axis_if merge_in[L],
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axis_if axis_out,
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input [L-2:0] initialized,
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input init,
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input flush,
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input enable,
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input aclk,
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input aresetn
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);
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// --------------------------------------------------------------------
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localparam W = (N*8) + U + 1; // tdata + tuser + tlast
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// --------------------------------------------------------------------
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wire int_done[L];
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assign int_done[0] = ~init;
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generate
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for(genvar j = 1; j < L; j++)
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begin: trailing_gen
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assign int_done[j] = initialized[j-1];
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end
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endgenerate
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// --------------------------------------------------------------------
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wire [L-1:0] wr_full;
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wire wr_en[L];
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wire [L-1:0] rd_empty;
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wire [W-1:0] rd_data[L];
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wire rd_en = axis_out.tready & axis_out.tvalid;
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wire [L-1:0] valid;
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wire all_valid = &valid;
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wire all_not_full = ~(|wr_full);
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wire all_not_empty = ~(|rd_empty);
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wire tlast[L];
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wire [U-1:0] tuser[L];
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wire [(N*8)-1:0] tdata[L];
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generate
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for(genvar j = 0; j < L; j++)
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begin: row_gen
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tiny_sync_fifo #(W)
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tiny_sync_fifo_i
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(
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.wr_full(wr_full[j]),
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.wr_data({merge_in[j].tlast, merge_in[j].tuser, merge_in[j].tdata}),
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.wr_en(wr_en[j]),
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.rd_empty(rd_empty[j]),
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.rd_data(rd_data[j]),
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// .rd_en(rd_en[j]),
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.rd_en(rd_en),
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.clk(aclk),
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.reset(~aresetn),
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.*
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);
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assign wr_en[j] = ~init & ~flush & merge_in[j].tready & merge_in[j].tvalid;
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// assign merge_in[j].tready = flush | (init & ~int_done[j]) | (all_valid & all_not_full); // fixme
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assign merge_in[j].tready = (init & ~int_done[j]) | (all_valid & all_not_full);
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assign valid[j] = merge_in[j].tvalid;
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assign {tlast[j], tuser[j], tdata[j]} = rd_data[j];
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end
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endgenerate
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// --------------------------------------------------------------------
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assign axis_out.tvalid = all_not_empty;
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assign axis_out.tdata = {tdata[2], tdata[1], tdata[0]};
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assign axis_out.tlast = tlast[0];
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assign axis_out.tuser[1:0] = tuser[0][1:0];
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assign axis_out.tuser[2] = tuser[0][2];
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// --------------------------------------------------------------------
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endmodule
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