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mgraep |
-- Copyright (c) 2013 Malte Graeper (mgraep@t-online.de) All rights reserved.
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mgraep |
library IEEE;
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use IEEE.std_logic_1164.all;
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library work;
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use work.qfp_p.all;
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package qfp32_add_p is
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type qfp32_SCMD_ADD_t is (QFP_ADD,QFP_SUB);
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constant QFP_SCMD_ADD : qfp_scmd_t := "00";
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constant QFP_SCMD_SUB : qfp_scmd_t := "01";
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end package qfp32_add_p;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library work;
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use work.qfp_p.all;
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use work.cla_p.all;
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use work.qfp32_add_p.all;
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entity qfp32_add is
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port (
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clk_i : in std_ulogic;
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reset_n_i : in std_ulogic;
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cmd_i : in qfp_scmd_t;
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start_i : in std_ulogic;
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ready_o : out std_ulogic;
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regA_i : in qfp32_t;
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regB_i : in qfp32_t;
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complete_o : out std_ulogic;
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result_o : out qfp32_raw_t;
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cmp_le_o : out std_ulogic);-- regA <= regB
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end qfp32_add;
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architecture Rtl of qfp32_add is
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signal p1_gt : std_ulogic;
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signal p1_fmt : qfp_fmt_t;
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signal p1_mant_a : unsigned(29 downto 0);
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signal p1_mant_b : unsigned(29 downto 0);
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signal p1_cy : std_ulogic;
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signal p1_op_a : unsigned(29 downto 0);
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signal p1_op_b : unsigned(29 downto 0);
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signal p1_clag1 : cla_level_t(7 downto 0);
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signal p1_clag2 : cla_level_t(1 downto 0);
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signal p1_cmp_gt : std_ulogic;
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signal p1_is_add : std_ulogic;
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signal p1_exp1 : std_ulogic_vector(2 downto 0);
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signal p2_complete : std_ulogic;
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signal p2_gt : std_ulogic;
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signal p2_fmt : qfp_fmt_t;
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signal p2_cy : std_ulogic;
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signal p2_op_a : unsigned(29 downto 0);
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signal p2_op_b : unsigned(29 downto 0);
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signal p2_clag1 : cla_level_t(7 downto 0);
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signal p2_clag2 : cla_level_t(1 downto 0);
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signal p2_is_add : std_ulogic;
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signal p2_exp1 : std_ulogic_vector(2 downto 0);
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signal p2_exp2 : std_ulogic_vector(8 downto 0);
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signal p2_result : unsigned(29 downto 0);
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signal p2_sign : std_ulogic;
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signal p2_cmp_gt : std_ulogic;
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begin -- Rtl
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process (clk_i, reset_n_i)
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begin -- process
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if reset_n_i = '0' then -- asynchronous reset (active low)
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p2_gt <= '0';
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p2_fmt <= (to_unsigned(0,2),'0');
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p2_is_add <= '0';
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p2_cy <= '0';
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p2_op_a <= to_unsigned(0,30);
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p2_op_b <= to_unsigned(0,30);
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p2_clag1 <= (others => ('0','0'));
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p2_clag2 <= (others => ('0','0'));
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p2_complete <= '0';
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p2_cmp_gt <= '0';
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--p2_exp1 <= (others => '0');-- 6Mhz faster design without this reset value
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elsif clk_i'event and clk_i = '1' then -- rising clock edge
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p2_complete <= start_i;
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if start_i = '1' then
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p2_gt <= p1_gt;
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p2_fmt <= p1_fmt;
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p2_is_add <= p1_is_add;
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p2_cy <= p1_cy;
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p2_op_a <= p1_op_a;
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p2_op_b <= p1_op_b;
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p2_clag1 <= p1_clag1;
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p2_clag2 <= p1_clag2;
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p2_cmp_gt <= p1_cmp_gt;
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p2_exp1 <= p1_exp1;
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end if;
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end if;
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end process;
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pp: process (cmd_i, p1_clag1, p1_clag2, p1_cy, p1_fmt.exp, p1_gt,
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p1_mant_a(0), p1_mant_a(29 downto 1), p1_mant_b(0),
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p1_mant_b(29 downto 1), p1_op_a, p1_op_b, p2_clag1, p2_exp1,
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p2_exp2, p2_fmt.exp, p2_fmt.sign, p2_is_add, p2_op_a, p2_op_b,
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p2_result(28 downto 0), p2_result(29), p2_sign, regA_i.fmt.exp,
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regA_i.fmt.sign, regA_i.mant, regB_i.fmt.exp, regB_i.fmt.sign,
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regB_i.mant)
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begin -- process
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--------------------------------------------------------------------------------------------------------------------
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-- stage 1
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--------------------------------------------------------------------------------------------------------------------
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-- check if mantissa of regb > rega
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p1_gt <= '0';
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if regb_i.fmt.exp > rega_i.fmt.exp or (regb_i.fmt.exp = rega_i.fmt.exp and fast_gt(regb_i.mant,rega_i.mant)) then
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p1_gt <= '1';
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end if;
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-- adjust mantissa to be aligned
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if regA_i.fmt.exp < regB_i.fmt.exp then
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p1_fmt.exp <= regB_i.fmt.exp;
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else
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p1_fmt.exp <= regA_i.fmt.exp;
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end if;
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-- determine sign
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if p1_gt = '1' then -- b > a
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-- greater value determines sign; invert sign if b > a and will be substracted
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if cmd_i = QFP_SCMD_SUB then
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p1_fmt.sign <= not regB_i.fmt.sign;
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else
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p1_fmt.sign <= regB_i.fmt.sign;
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end if;
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else
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p1_fmt.sign <= regA_i.fmt.sign;
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end if;
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-- extend for rounding
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p1_mant_a <= fast_shift(regA_i.mant & '0',to_integer(p1_fmt.exp-regA_i.fmt.exp)*8,'1');
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p1_mant_b <= fast_shift(regB_i.mant & '0',to_integer(p1_fmt.exp-regB_i.fmt.exp)*8,'1');
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-- negate operands for subtraction
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p1_cy <= '0';
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p1_is_add <= '0';
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p1_op_a <= '0' & p1_mant_a(29 downto 1);
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p1_op_b <= '0' & p1_mant_b(29 downto 1);
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if (cmd_i = QFP_SCMD_ADD and (regA_i.fmt.sign xor regB_i.fmt.sign) = '1') or
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(cmd_i = QFP_SCMD_SUB and (regA_i.fmt.sign xor regB_i.fmt.sign) = '0') then
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-- substraction
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if p1_gt = '1' then
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p1_op_a <= not ('0' & p1_mant_a(29 downto 1));
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p1_cy <= not p1_mant_a(0);-- use rounding
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else
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p1_op_b <= not ('0' & p1_mant_b(29 downto 1));
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p1_cy <= not p1_mant_b(0);-- use rounding
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end if;
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else -- addition
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p1_cy <= p1_mant_a(0) or p1_mant_b(0);-- rounding up
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p1_is_add <= '1';
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end if;
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-- calc greater than b > a
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p1_cmp_gt <= p1_gt;
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if regA_i.fmt.sign /= regB_i.fmt.sign then
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p1_cmp_gt <= regA_i.fmt.sign;
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elsif regA_i.fmt.sign = '1' then
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p1_cmp_gt <= not p1_gt;
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end if;
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-- calculate pre carry (first level of carray lookahead adder)
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p1_clag1 <= CLALevelMk(p1_op_a,p1_op_b,4);
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-- second level
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p1_clag2 <= CLALevelMk(p1_clag1,4);
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-- expand first level carry
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p1_exp1 <= CLAExpandCy(p1_clag2,p1_cy);
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--------------------------------------------------------------------------------------------------------------------
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-- stage 2
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--------------------------------------------------------------------------------------------------------------------
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-- expand second level carry
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p2_exp2 <= CLAExpandCy(p2_clag1,p2_exp1);
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-- propagate carry (level 2)
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p2_result <= CLAParallelAdd(p2_op_a,p2_op_b,p2_exp2);
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p2_sign <= p2_fmt.sign;
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result_o.extMant <= p2_result(28 downto 0) & (23 downto 0 => '0');
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result_o.ov <= "0000" & (p2_result(29) and p2_is_add); -- allow overflow only for real additions
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result_o.exp <= '0' & p2_fmt.exp;
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result_o.sign <= p2_sign;-- and not p2_cmp_eq;
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end process pp;
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cmp_le_o <= not p2_cmp_gt;-- less equal than
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ready_o <= '1';
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complete_o <= p2_complete;
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end Rtl;
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