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mgraep |
-- Copyright (c) 2013 Malte Graeper (mgraep@t-online.de) All rights reserved.
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mgraep |
library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library work;
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use work.qfp_p.all;
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use work.qfp32_add_p.all;
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use work.qfp32_misc_p.all;
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package qfp32_unit_p is
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type qfp_cmd_t is record
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unit : unsigned(2 downto 0);
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sub_cmd : qfp_scmd_t;
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end record qfp_cmd_t;
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constant QFP_UNIT_ADD : unsigned(2 downto 0) := to_unsigned(0,3);
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constant QFP_UNIT_MUL : unsigned(2 downto 0) := to_unsigned(1,3);
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constant QFP_UNIT_RECP : unsigned(2 downto 0) := to_unsigned(2,3);
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constant QFP_UNIT_MISC : unsigned(2 downto 0) := to_unsigned(3,3);
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constant QFP_UNIT_NONE : unsigned(2 downto 0) := to_unsigned(5,3);
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constant QFP_UNIT_DIV : unsigned(2 downto 0) := to_unsigned(4,3);
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constant qfp_config_add : natural := 2**to_integer(QFP_UNIT_ADD);
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constant qfp_config_mul : natural := 2**to_integer(QFP_UNIT_MUL);
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constant qfp_config_recp : natural := 2**to_integer(QFP_UNIT_RECP);
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constant qfp_config_misc : natural := 2**to_integer(QFP_UNIT_MISC);
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constant qfp_config_div : natural := 2**to_integer(QFP_UNIT_DIV);
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constant qfp_config_all : natural := qfp_config_add+qfp_config_mul+qfp_config_recp+qfp_config_misc+qfp_config_div;
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component qfp32_add is
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port (
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clk_i : in std_ulogic;
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reset_n_i : in std_ulogic;
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cmd_i : in qfp_scmd_t;
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start_i : in std_ulogic;
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ready_o : out std_ulogic;
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regA_i : in qfp32_t;
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regB_i : in qfp32_t;
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complete_o : out std_ulogic;
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result_o : out qfp32_raw_t;
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cmp_eq_o : out std_ulogic;
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cmp_gt_o : out std_ulogic);
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end component qfp32_add;
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component qfp32_mul is
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port (
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clk_i : in std_ulogic;
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reset_n_i : in std_ulogic;
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start_i : in std_ulogic;
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ready_o : out std_ulogic;
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regA_i : in qfp32_t;
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regB_i : in qfp32_t;
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complete_o : out std_ulogic;
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result_o : out qfp32_raw_t);
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end component qfp32_mul;
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component qfp32_recp is
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port (
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clk_i : in std_ulogic;
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reset_n_i : in std_ulogic;
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start_i : in std_ulogic;
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ready_o : out std_ulogic;
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regA_i : in qfp32_t;
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complete_o : out std_ulogic;
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result_o : out qfp32_t);
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end component qfp32_recp;
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component qfp32_divider is
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port (
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clk_i : in std_ulogic;
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reset_n_i : in std_ulogic;
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start_i : in std_ulogic;
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ready_o : out std_ulogic;
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regA_i : in qfp32_t;
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regB_i : in qfp32_t;
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complete_o : out std_ulogic;
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result_o : out qfp32_raw_t);
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end component qfp32_divider;
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component qfp32_misc is
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port (
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clk_i : in std_ulogic;
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reset_n_i : in std_ulogic;
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cmd_i : in qfp_scmd_t;
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start_i : in std_ulogic;
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ready_o : out std_ulogic;
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regA_i : in qfp32_t;
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regB_i : in qfp32_t;
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complete_o : out std_ulogic;
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result_o : out qfp32_raw_t);
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end component qfp32_misc;
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component qfp_norm is
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port (
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clk_i : in std_ulogic;
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reset_n_i : in std_ulogic;
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raw_i : in qfp32_raw_t;
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result_o : out qfp32_t;
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result_zero_o : out std_ulogic);
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end component qfp_norm;
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end package qfp32_unit_p;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library work;
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use work.qfp_p.all;
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use work.qfp32_unit_p.all;
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use work.qfp32_norm_p.all;
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use work.qfp32_misc_p.all;
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entity qfp_unit is
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generic (
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config : natural := qfp_config_all);
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port (
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clk_i : in std_ulogic;
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reset_n_i : in std_ulogic;
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cmd_i : in qfp_cmd_t;
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ready_o : out std_ulogic;
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start_i : in std_ulogic;
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regA_i : in std_ulogic_vector(31 downto 0);
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regB_i : in std_ulogic_vector(31 downto 0);
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result_o : out std_ulogic_vector(31 downto 0);
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cmp_gt_o : out std_ulogic;
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cmp_z_o : out std_ulogic;
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complete_o : out std_ulogic);
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end entity qfp_unit;
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architecture Rtl of qfp_unit is
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constant units_config : unsigned(5 downto 0) := to_unsigned(config,6);
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type qfp32_vector_t is array (natural range <>) of qfp32_raw_t;
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function "sll" (ARG: std_ulogic_vector; COUNT: integer) return std_ulogic_vector is
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begin
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return To_StdULogicVector(std_logic_vector(unsigned(ARG) sll COUNT));
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end "sll";
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signal units_start : std_ulogic_vector(5 downto 0);
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signal units_ready : std_ulogic_vector(5 downto 0);
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signal units_complete : std_ulogic_vector(5 downto 0);
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signal units_result : qfp32_vector_t(5 downto 0);
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signal i : natural range 0 to 5;
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signal j : natural range 0 to 5;
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signal regA : qfp32_t;
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signal regB : qfp32_t;
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signal cmp_le : std_ulogic;
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signal result : qfp32_t;
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signal active_unit : unsigned(2 downto 0);
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signal sign_ext : std_ulogic;
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signal raw_result : qfp32_raw_t;
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signal result_zero : std_ulogic;
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begin -- architecture Rtl
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qfp32_add_1: entity work.qfp32_add
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port map (
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clk_i => clk_i,
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reset_n_i => reset_n_i,
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cmd_i => cmd_i.sub_cmd,
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start_i => units_start(0),
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ready_o => units_ready(0),
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regA_i => regA,
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regB_i => regB,
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complete_o => units_complete(0),
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result_o => units_result(0),
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cmp_le_o => cmp_le);
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qfp32_mul_1: entity work.qfp32_mul
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port map (
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clk_i => clk_i,
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reset_n_i => reset_n_i,
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start_i => units_start(1),
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ready_o => units_ready(1),
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regA_i => regA,
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regB_i => regB,
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complete_o => units_complete(1),
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result_o => units_result(1));
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qfp32_recp_1: entity work.qfp32_recp
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port map (
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clk_i => clk_i,
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reset_n_i => reset_n_i,
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start_i => units_start(2),
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ready_o => units_ready(2),
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regA_i => regA,
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complete_o => units_complete(2),
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result_o => units_result(2));
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qfp32_divider_1: entity work.qfp32_divider
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port map (
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clk_i => clk_i,
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reset_n_i => reset_n_i,
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start_i => units_start(4),
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ready_o => units_ready(4),
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regA_i => regA,
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regB_i => regB,
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complete_o => units_complete(4),
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result_o => units_result(4));
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qfp32_misc_1: entity work.qfp32_misc
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port map (
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clk_i => clk_i,
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reset_n_i => reset_n_i,
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cmd_i => cmd_i.sub_cmd,
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start_i => units_start(3),
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ready_o => units_ready(3),
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regA_i => regA,
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regB_i => regB,
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complete_o => units_complete(3),
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result_o => units_result(3));
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qfp_norm_1: entity work.qfp_norm
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port map (
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clk_i => clk_i,
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reset_n_i => reset_n_i,
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raw_i => raw_result,
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result_o => result,
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result_zero_o => result_zero);
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raw_result <= units_result(i);
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process (clk_i, reset_n_i) is
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begin -- process
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if reset_n_i = '0' then -- asynchronous reset (active low)
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active_unit <= QFP_UNIT_NONE;
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elsif clk_i'event and clk_i = '1' then -- rising clock edge
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active_unit <= cmd_i.unit;
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end if;
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end process;
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units_result(to_integer(QFP_UNIT_NONE)) <= (unsigned(regA_i(28 downto 0)) & X"000000","00000",'0' & unsigned(regA_i(30 downto 29)),regA_i(31));
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units_ready(to_integer(QFP_UNIT_NONE)) <= '1';
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units_complete(to_integer(QFP_UNIT_NONE)) <= '0';
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i <= to_integer(cmd_i.unit);
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j <= to_integer(active_unit);
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-- start unit
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units_start <= ("000001" sll i) when units_config(i) = '1' and start_i = '1' else (others => '0');
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-- convert from q to integer
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sign_ext <= '1' when cmd_i.unit = to_unsigned(3,3) and cmd_i.sub_cmd = QFP_SCMD_Q2I else '0';
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regA <= (unsigned(regA_i(28 downto 0)),(unsigned(regA_i(30 downto 29)),regA_i(31)));
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regB <= (unsigned(regB_i(28 downto 0)),(unsigned(regB_i(30 downto 29)),regB_i(31)));
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result_o(31) <= result.fmt.sign;
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result_o(30 downto 29) <= std_ulogic_vector(result.fmt.exp) when sign_ext = '0' else result.fmt.sign & result.fmt.sign;
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result_o(28 downto 0) <= std_ulogic_vector(result.mant);
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-- add/sub: 2 cycles, fully pipelined
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-- mul: 3 cycles, delay 2 cycles
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-- recp: 31 cycles, delay 30 cycles
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-- misc: 1 cycle, delay 1 cycle
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-- div: 32cycles, delay 31 cycles
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ready_o <= units_ready(j);
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complete_o <= units_complete(j);
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-- only valid for sub
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cmp_gt_o <= not result_zero and cmp_le;
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cmp_z_o <= result_zero;
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end architecture Rtl;
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