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vinogradov |
//////////////////////////////////////////////////////////////////////////////////////////////
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// Project Qrisc32 is risc cpu implementation, purpose is studying
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// Digital System Design course at Kyoung Hee University during my PhD earning
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// Copyright (C) 2010 Vinogradov Viacheslav
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2.1 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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//
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//
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//////////////////////////////////////////////////////////////////////////////////////////////
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module mem#(size=256,adr_limit=64)(
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input clk,
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input[31:0] add_r,add_w,data_w,
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input rd,wr,
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output bit[31:0] data_r,
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output req
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,input stop_enable//=1 will stop on each problem(non align access and out of adr access)
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,output bit stop_active//=1 will indicate about stop signal
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,input verbose
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);
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bit[31:0] sram[size-1:0];
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assign req = 1'b0;
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wire[$bits(size)-1:0]add_r_word =add_r[31:2];
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wire[$bits(size)-1:0]add_w_word =add_w[31:2];
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always@(posedge clk)
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begin
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stop_active=0;
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if(wr)
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begin
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sram[add_w_word]<=data_w;
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if(verbose)
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$display(".................................[%m] write at address %08x with data %08x",add_w,data_w);
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end
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data_r <= sram[add_r_word];
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if(rd)
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begin
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if(verbose)
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$display(".................................[%m] read at address %08x with data %08x",add_r,sram[add_r_word]);
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end
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if(wr && add_w>adr_limit*4)
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begin
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if(verbose)
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$display(".................................[%m] write out of limit address %08x",add_w);
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stop_active=1;
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if(stop_enable)$stop;
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end
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if(rd && add_r>adr_limit*4)
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begin
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if(verbose)
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$display(".................................[%m] read out of limit address %08x",add_r);
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if(stop_enable)$stop;
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stop_active=1;
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end
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if(add_r[1:0]!=0 && rd)
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begin
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if(verbose)
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$display(".................................[%m] read by non align address %08x",add_r);
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if(stop_enable)$stop;
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stop_active=1;
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end
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if(add_w[1:0]!=0 && wr)
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begin
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if(verbose)
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$display(".................................[%m] write by non align address %08x",add_w);
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if(stop_enable)$stop;
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stop_active=1;
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end
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end
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endmodule
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