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vinogradov |
//////////////////////////////////////////////////////////////////////////////////////////////
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// Project Qrisc32 is risc cpu implementation, purpose is studying
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// Digital System Design course at Kyoung Hee University during my PhD earning
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// Copyright (C) 2010 Vinogradov Viacheslav
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2.1 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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//
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//
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//////////////////////////////////////////////////////////////////////////////////////////////
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import risc_pack::*;
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module qrisc32_EX(
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input clk,reset,pipe_stall,
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input pipe_struct pipe_ex_in,
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output pipe_struct pipe_ex_out,
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output bit new_address_valid,//to mem stage
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output bit[31:0] new_address//to mem stage
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);
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import risc_pack::*;
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bit flagZ_w, flagC_w;
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bit flagZ, flagC;
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wire signed[31:0] r2 = pipe_ex_in.val_r2;
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wire signed[3:0] inc_r2 = pipe_ex_in.incr_r2;
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wire signed[31:0] r2_add = r2 + inc_r2;
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wire[32:0] summ_result = pipe_ex_in.val_r1 + pipe_ex_in.val_r2;
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pipe_struct pipe_ex_out_w;
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always_comb
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begin
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pipe_ex_out_w=pipe_ex_in;
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flagZ_w=0;
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flagC_w=0;
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if(pipe_ex_in.ldrf_op)
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begin
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if( (pipe_ex_in.jmpz && flagZ)
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|| (pipe_ex_in.jmpnz && ~flagZ)
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|| (pipe_ex_in.jmpc && flagC)
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|| (pipe_ex_in.jmpnc && ~flagC)
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)
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pipe_ex_out_w.val_dst=pipe_ex_in.val_r1;
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else
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pipe_ex_out_w.val_dst=pipe_ex_in.val_r2;
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end
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else if(pipe_ex_in.and_op)
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begin
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pipe_ex_out_w.val_dst=pipe_ex_in.val_r1 & pipe_ex_in.val_r2;
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flagC_w=0;
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flagZ_w=(pipe_ex_out_w.val_dst==0)?1:0;
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end
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else if(pipe_ex_in.or_op)
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begin
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pipe_ex_out_w.val_dst=pipe_ex_in.val_r1 | pipe_ex_in.val_r2;
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flagC_w=0;
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flagZ_w=(pipe_ex_out_w.val_dst==0)?1:0;
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end
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else if(pipe_ex_in.xor_op)
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begin
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pipe_ex_out_w.val_dst=pipe_ex_in.val_r1 ^ pipe_ex_in.val_r2;
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flagC_w=0;
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flagZ_w=(pipe_ex_out_w.val_dst==0)?1:0;
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end
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else if(pipe_ex_in.add_op//simple addition operation
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|| pipe_ex_in.jmpunc //jump unconditional calculate address = R1+R2(offset)
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//jump conditional calculate address = R1+R2(offset) and check flags
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|| pipe_ex_in.jmpz || pipe_ex_in.jmpnz || pipe_ex_in.jmpc || pipe_ex_in.jmpnc)
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begin
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{flagC_w,pipe_ex_out_w.val_dst}=summ_result;
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flagZ_w=(pipe_ex_out_w.val_dst==0)?1:0;
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end
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else if(pipe_ex_in.mul_op)
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begin
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{flagC_w,pipe_ex_out_w.val_dst}=pipe_ex_in.val_r1 * pipe_ex_in.val_r2;
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flagZ_w=(pipe_ex_out_w.val_dst==0)?1:0;
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end
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else if(pipe_ex_in.shl_op)
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begin
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{flagC_w,pipe_ex_out_w.val_dst}=pipe_ex_in.val_r1 << pipe_ex_in.val_r2;
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flagZ_w=(pipe_ex_out_w.val_dst==0)?1:0;
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end
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else if(pipe_ex_in.shr_op)
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begin
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{pipe_ex_out_w.val_dst,flagC_w}={pipe_ex_in.val_r1,1'b0 }>> pipe_ex_in.val_r2;
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flagZ_w=(pipe_ex_out_w.val_dst==0)?1:0;
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end
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else if(pipe_ex_in.cmp_op)
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begin
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flagZ_w=(pipe_ex_out_w.val_r1==pipe_ex_out_w.val_r2)?1:0;
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flagC_w=(pipe_ex_out_w.val_r1>=pipe_ex_out_w.val_r2)?0:1;
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end
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pipe_ex_out_w.val_r2 = (pipe_ex_out_w.incr_r2_enable)?r2_add:pipe_ex_out_w.val_r2;
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end
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always@(posedge clk)
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begin
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flagZ<=
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(pipe_ex_in.and_op | pipe_ex_in.or_op | pipe_ex_in.xor_op | pipe_ex_in.add_op
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| pipe_ex_in.mul_op | pipe_ex_in.shl_op | pipe_ex_in.shr_op | pipe_ex_in.cmp_op)?flagZ_w:flagZ;
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flagC<=
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(pipe_ex_in.and_op | pipe_ex_in.or_op | pipe_ex_in.xor_op | pipe_ex_in.add_op
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| pipe_ex_in.mul_op | pipe_ex_in.shl_op | pipe_ex_in.shr_op | pipe_ex_in.cmp_op)?flagC_w:flagC;
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if(pipe_ex_in.jmpunc || (pipe_ex_in.jmpz & flagZ) ||(pipe_ex_in.jmpnz & !flagZ)||
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(pipe_ex_in.jmpc & flagC) ||(pipe_ex_in.jmpnc & !flagC) )
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begin
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new_address_valid<=~pipe_ex_in.ldrf_op;
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new_address<=pipe_ex_out_w.val_dst;
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end
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else
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new_address_valid<=0;
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if(~pipe_stall)
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begin
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pipe_ex_out<=pipe_ex_out_w;
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if(pipe_ex_in.read_mem| pipe_ex_in.write_mem)
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pipe_ex_out.val_r1<=summ_result;//address for accessing
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end
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end
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endmodule
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