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vinogradov |
//////////////////////////////////////////////////////////////////////////////////////////////
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// Project Qrisc32 is risc cpu implementation, purpose is studying
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// Digital System Design course at Kyoung Hee University during my PhD earning
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// Copyright (C) 2010 Vinogradov Viacheslav
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2.1 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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//
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//
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//////////////////////////////////////////////////////////////////////////////////////////////
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import risc_pack::*;
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module qrisc32_ID(
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input clk,reset,
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input [31:0] instruction,
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input [31:0] pc,
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input pipe_stall,//feed back from MEM stage
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input pipe_struct pipe_wb_mem,//for memory read
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input pipe_struct pipe_wb_ex,//for R2 register and ALU operations only
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output pipe_struct pipe_id_out,
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input verbose
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);
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import risc_pack::*;
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bit[31:0] rf[31:0];//32 regs width is 32
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bit[31:0] offset_w;
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pipe_struct pipe_id_out_w;
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bit[31:0] nop_counter;
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bit[31:0] jmp_counter;
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bit[31:0] alu_counter;
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bit[31:0] oth_counter;
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//comb part
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always_comb
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begin
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pipe_id_out_w.dst_r = instruction[04:00];
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pipe_id_out_w.src_r1 = instruction[09:05];
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pipe_id_out_w.src_r2 = instruction[14:10];
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pipe_id_out_w.incr_r2 = 0;
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pipe_id_out_w.incr_r2_enable = 1;
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pipe_id_out_w.read_mem = 0;
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pipe_id_out_w.write_mem = 0;
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pipe_id_out_w.write_reg = 0;
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pipe_id_out_w.mul_op = 0;
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pipe_id_out_w.add_op = 0;
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pipe_id_out_w.or_op = 0;
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pipe_id_out_w.and_op = 0;
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pipe_id_out_w.xor_op = 0;
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pipe_id_out_w.shl_op = 0;
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pipe_id_out_w.shr_op = 0;
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pipe_id_out_w.cmp_op = 0;
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pipe_id_out_w.ldrf_op = 0;
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pipe_id_out_w.jmpunc = 0;
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pipe_id_out_w.jmpz = 0;
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pipe_id_out_w.jmpnz = 0;
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pipe_id_out_w.jmpc = 0;
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pipe_id_out_w.jmpnc = 0;
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pipe_id_out_w.val_r1 = (pipe_wb_mem.write_reg && pipe_wb_mem.dst_r==pipe_id_out_w.src_r1)?
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pipe_wb_mem.val_dst://forward from memory read
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//(pipe_wb_mem.incr_r2_enable && pipe_wb_mem.src_r2==pipe_id_out_w.src_r1)?
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//pipe_wb_mem.val_r2://forward from mem stage R2 register
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(pipe_wb_ex.write_reg && pipe_wb_ex.dst_r==pipe_id_out_w.src_r1)?
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pipe_wb_ex.val_dst://forward from execution stage DST register
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(pipe_wb_ex.incr_r2_enable && pipe_wb_ex.src_r2==pipe_id_out_w.src_r1)?
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pipe_wb_ex.val_r2://forward from execution stage R2 register
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rf[pipe_id_out_w.src_r1];//otherwise from register file
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pipe_id_out_w.val_r2 = (pipe_wb_mem.write_reg && pipe_wb_mem.dst_r==pipe_id_out_w.src_r2)?
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pipe_wb_mem.val_dst://forward from memory read
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//(pipe_wb_mem.incr_r2_enable && pipe_wb_mem.src_r2==pipe_id_out_w.src_r2)?
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//pipe_wb_mem.val_r2://forward from mem stage R2 register
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(pipe_wb_ex.write_reg && pipe_wb_ex.dst_r==pipe_id_out_w.src_r2)?
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pipe_wb_ex.val_dst://forward from execution stage DST register
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(pipe_wb_ex.incr_r2_enable && pipe_wb_ex.src_r2==pipe_id_out_w.src_r2)?
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pipe_wb_ex.val_r2://forward from execution stage R2 register
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rf[pipe_id_out_w.src_r2];//otherwise from register file
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pipe_id_out_w.val_dst = (pipe_wb_mem.write_reg && pipe_wb_mem.dst_r==pipe_id_out_w.dst_r)?
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pipe_wb_mem.val_dst://forward from memory read
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//(pipe_wb_mem.incr_r2_enable && pipe_wb_mem.src_r2==pipe_id_out_w.dst_r)?
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//pipe_wb_mem.val_r2://forward from mem stage R2 register
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(pipe_wb_ex.write_reg && pipe_wb_ex.dst_r==pipe_id_out_w.dst_r)?
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pipe_wb_ex.val_dst://forward from execution stage DST register
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(pipe_wb_ex.incr_r2_enable && pipe_wb_ex.src_r2==pipe_id_out_w.dst_r)?
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pipe_wb_ex.val_r2://forward from execution stage R2 register
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rf[pipe_id_out_w.dst_r];//otherwise from register file
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offset_w = (instruction[25])?pipe_id_out_w.val_r2:{{17{instruction[24]}},instruction[24:10]};//17 bit sign + 15 bit offset
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case(instruction[24:22])
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0:begin pipe_id_out_w.incr_r2=4'd0;pipe_id_out_w.incr_r2_enable = 0;end
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1:pipe_id_out_w.incr_r2=4'd1;
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2:pipe_id_out_w.incr_r2=4'd2;
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3:pipe_id_out_w.incr_r2=4'd4;
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4:begin pipe_id_out_w.incr_r2=4'd0;pipe_id_out_w.incr_r2_enable = 0;end
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5:pipe_id_out_w.incr_r2=-4'd1;
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6:pipe_id_out_w.incr_r2=-4'd2;
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7:pipe_id_out_w.incr_r2=-4'd4;
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endcase
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case(instruction[31:28])
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//load and store
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LDR:
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case(instruction[27:26])
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2'b00:
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begin
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pipe_id_out_w.write_reg = (pipe_id_out_w.dst_r!=pipe_id_out_w.src_r1)?1:0;//write from reg src1 to reg dst
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//pipe_id_out_w.incr_r2_enable = pipe_id_out_w.write_reg;
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pipe_id_out_w.val_dst = pipe_id_out_w.val_r1;
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end
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2'b01:
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begin
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pipe_id_out_w.val_dst[31:16] = instruction[20:5];
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pipe_id_out_w.write_reg = 1;//write from reg src1 to reg dst
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pipe_id_out_w.incr_r2_enable = 0;
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end
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2'b10:
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begin
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pipe_id_out_w.val_dst[15:0] = instruction[20:5];
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pipe_id_out_w.write_reg = 1;//write from reg src1 to reg dst
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pipe_id_out_w.incr_r2_enable = 0;
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end
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2'b11:
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begin
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pipe_id_out_w.read_mem = 1;//read from mem by Rscr2+Rsrc1 and then write to register
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pipe_id_out_w.write_reg = 1;//write from reg src1 to reg dst
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pipe_id_out_w.incr_r2_enable = instruction[25];
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pipe_id_out_w.val_r2 = offset_w;
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end
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endcase
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STR:
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case(instruction[27:26])
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//2'b11:
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default:
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begin
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pipe_id_out_w.write_mem = 1;//write Rdst to mem by Rscr2+Rsrc1
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pipe_id_out_w.val_r2 = offset_w;
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pipe_id_out_w.incr_r2_enable = instruction[25];
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end
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endcase
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//jumps
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JMPUNC:
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case(instruction[27:26])
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2'b00:
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begin
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pipe_id_out_w.val_r1 =instruction[25:0];
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pipe_id_out_w.val_r2 ='0;//no offset
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pipe_id_out_w.incr_r2_enable = 0;
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pipe_id_out_w.jmpunc = 1;
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end
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2'b01://relative jump
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begin
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pipe_id_out_w.val_r1 =pc;
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pipe_id_out_w.val_r2 =offset_w;//offset
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pipe_id_out_w.incr_r2_enable = instruction[25];
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pipe_id_out_w.jmpunc = 1;
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end
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2'b10://call
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begin
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pipe_id_out_w.val_r1 =pc;
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pipe_id_out_w.val_r2 =offset_w;//offset
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pipe_id_out_w.val_dst =pc;//return address
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pipe_id_out_w.incr_r2_enable = instruction[25];
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pipe_id_out_w.jmpunc = 1;
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pipe_id_out_w.write_reg = 1;
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end
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2'b11://ret
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begin
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pipe_id_out_w.val_r1 =pipe_id_out_w.val_dst;
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pipe_id_out_w.val_r2 ='0;//offset
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pipe_id_out_w.incr_r2_enable = instruction[25];
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pipe_id_out_w.jmpunc = 1;
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end
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endcase
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JMPF:
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case(instruction[27:26])
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2'b00://jmpz
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begin
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pipe_id_out_w.val_r1 =pc;
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pipe_id_out_w.val_r2 =offset_w;//offset
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pipe_id_out_w.incr_r2_enable = instruction[25];
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pipe_id_out_w.jmpz = 1;
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end
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2'b01://jmpnz
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begin
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pipe_id_out_w.val_r1 =pc;
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pipe_id_out_w.val_r2 =offset_w;//offset
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pipe_id_out_w.incr_r2_enable = instruction[25];
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pipe_id_out_w.jmpnz = 1;
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end
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2'b10://jmpc
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begin
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pipe_id_out_w.val_r1 =pc;
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pipe_id_out_w.val_r2 =offset_w;//offset
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pipe_id_out_w.incr_r2_enable = instruction[25];
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pipe_id_out_w.jmpc = 1;
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end
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2'b11://jmpnc
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begin
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pipe_id_out_w.val_r1 =pc;
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pipe_id_out_w.val_r2 =offset_w;//offset
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pipe_id_out_w.incr_r2_enable = instruction[25];
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pipe_id_out_w.jmpnc = 1;
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end
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endcase
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//Arithmetic
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ALU:
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case(instruction[27:25])
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3'd0:
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begin
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pipe_id_out_w.write_reg = 1;
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pipe_id_out_w.and_op = 1;
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end
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3'd1:
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begin
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pipe_id_out_w.write_reg = 1;
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pipe_id_out_w.or_op = 1;
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end
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3'd2:
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begin
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pipe_id_out_w.write_reg = 1;
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pipe_id_out_w.xor_op = 1;
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end
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| 251 |
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3'd3:
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| 252 |
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begin
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pipe_id_out_w.write_reg = 1;
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pipe_id_out_w.add_op = 1;
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end
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| 256 |
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3'd4:
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| 257 |
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begin
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pipe_id_out_w.write_reg = 1;
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| 259 |
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pipe_id_out_w.mul_op = 1;
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| 260 |
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end
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| 261 |
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3'd5:
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| 262 |
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begin
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| 263 |
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pipe_id_out_w.write_reg = 1;
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| 264 |
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pipe_id_out_w.shl_op = 1;
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| 265 |
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end
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| 266 |
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3'd6:
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| 267 |
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begin
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| 268 |
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pipe_id_out_w.write_reg = 1;
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| 269 |
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pipe_id_out_w.shr_op = 1;
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| 270 |
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end
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| 271 |
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//cmp_op =7
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| 272 |
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default:
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| 273 |
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begin
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| 274 |
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//pipe_id_out_w.write_reg = 0;
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| 275 |
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pipe_id_out_w.cmp_op = 1;
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| 276 |
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end
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| 277 |
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endcase
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| 278 |
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| 279 |
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LDRF:
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| 280 |
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case(instruction[27:26])
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| 281 |
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2'b00://ldrz
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| 282 |
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begin
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| 283 |
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pipe_id_out_w.jmpz = 1;
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| 284 |
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pipe_id_out_w.ldrf_op = 1;
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| 285 |
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pipe_id_out_w.write_reg = 1;
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| 286 |
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end
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| 287 |
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2'b01://ldrnz
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| 288 |
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begin
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| 289 |
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pipe_id_out_w.jmpnz = 1;
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| 290 |
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pipe_id_out_w.ldrf_op = 1;
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| 291 |
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pipe_id_out_w.write_reg = 1;
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| 292 |
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end
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| 293 |
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2'b10://ldrc
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| 294 |
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begin
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| 295 |
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pipe_id_out_w.ldrf_op = 1;
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| 296 |
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pipe_id_out_w.jmpc = 1;
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| 297 |
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pipe_id_out_w.write_reg = 1;
|
| 298 |
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end
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| 299 |
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2'b11://ldrnc
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| 300 |
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begin
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| 301 |
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pipe_id_out_w.ldrf_op = 1;
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| 302 |
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pipe_id_out_w.jmpnc = 1;
|
| 303 |
|
|
pipe_id_out_w.write_reg = 1;
|
| 304 |
|
|
end
|
| 305 |
|
|
endcase
|
| 306 |
|
|
|
| 307 |
|
|
default:
|
| 308 |
|
|
begin
|
| 309 |
|
|
pipe_id_out_w='0;
|
| 310 |
|
|
end
|
| 311 |
|
|
endcase
|
| 312 |
|
|
end
|
| 313 |
|
|
|
| 314 |
|
|
always@(posedge clk)// or posedge reset)
|
| 315 |
|
|
if(reset)
|
| 316 |
|
|
begin
|
| 317 |
|
|
pipe_id_out<='0;
|
| 318 |
|
|
for(int i=0;i<32;i++)
|
| 319 |
|
|
rf[i]<='0;
|
| 320 |
|
|
nop_counter<='0;
|
| 321 |
|
|
jmp_counter<='0;
|
| 322 |
|
|
alu_counter<='0;
|
| 323 |
|
|
oth_counter<='0;
|
| 324 |
|
|
end
|
| 325 |
|
|
else
|
| 326 |
|
|
begin
|
| 327 |
|
|
if(instruction==0)
|
| 328 |
|
|
nop_counter<=nop_counter+1;
|
| 329 |
|
|
else
|
| 330 |
|
|
if(instruction[31:28]==JMPUNC || instruction[31:28]==JMPF)
|
| 331 |
|
|
jmp_counter<=jmp_counter+1;
|
| 332 |
|
|
else
|
| 333 |
|
|
if(instruction[31:28]==ALU)
|
| 334 |
|
|
alu_counter<=alu_counter+1;
|
| 335 |
|
|
else
|
| 336 |
|
|
oth_counter<=oth_counter+1;
|
| 337 |
|
|
|
| 338 |
|
|
if(~pipe_stall)
|
| 339 |
|
|
pipe_id_out<=pipe_id_out_w;
|
| 340 |
|
|
|
| 341 |
|
|
if(pipe_wb_ex.write_reg)//from ex stage DST register
|
| 342 |
|
|
rf[pipe_wb_ex.dst_r]<=pipe_wb_ex.val_dst;
|
| 343 |
|
|
|
| 344 |
|
|
if(pipe_wb_ex.incr_r2_enable)//from ex stage R2 register
|
| 345 |
|
|
rf[pipe_wb_ex.src_r2]<=pipe_wb_ex.val_r2;
|
| 346 |
|
|
|
| 347 |
|
|
if(pipe_wb_mem.write_reg)//from memory read stage
|
| 348 |
|
|
rf[pipe_wb_mem.dst_r]<=pipe_wb_mem.val_dst;
|
| 349 |
|
|
|
| 350 |
|
|
//if(pipe_wb_mem.incr_r2_enable)//from mem stage R2 register
|
| 351 |
|
|
// rf[pipe_wb_mem.src_r2]<=pipe_wb_mem.val_r2;
|
| 352 |
|
|
|
| 353 |
|
|
|
| 354 |
|
|
//synthesys translate_off
|
| 355 |
|
|
if(verbose)
|
| 356 |
|
|
begin
|
| 357 |
|
|
if(~pipe_stall)
|
| 358 |
|
|
begin
|
| 359 |
|
|
case(instruction[31:28])
|
| 360 |
|
|
//load and store
|
| 361 |
|
|
LDR:
|
| 362 |
|
|
case(instruction[27:26])
|
| 363 |
|
|
2'b00:$display("LDR R%0d, R%0d, R%0d+%d",pipe_id_out_w.dst_r,pipe_id_out_w.src_r1,pipe_id_out_w.src_r2,$signed(pipe_id_out_w.incr_r2));
|
| 364 |
|
|
2'b01:$display("LDRH R%0d,0x%x",pipe_id_out_w.dst_r,instruction[20:5]);
|
| 365 |
|
|
2'b10:$display("LDRL R%0d,0x%x",pipe_id_out_w.dst_r,instruction[20:5]);
|
| 366 |
|
|
2'b11:$display("LDRP R%0d,[R%0d +%0d],R%0d+%d",pipe_id_out_w.dst_r,pipe_id_out_w.src_r1,$signed(offset_w),pipe_id_out_w.src_r2,$signed(pipe_id_out_w.incr_r2));
|
| 367 |
|
|
endcase
|
| 368 |
|
|
|
| 369 |
|
|
STR:
|
| 370 |
|
|
case(instruction[27:26])
|
| 371 |
|
|
default:$display("STR R%0d,[R%0d +%0d],R%0d+%d",pipe_id_out_w.dst_r,pipe_id_out_w.src_r1,$signed(offset_w),pipe_id_out_w.src_r2,$signed(pipe_id_out_w.incr_r2));
|
| 372 |
|
|
endcase
|
| 373 |
|
|
|
| 374 |
|
|
//jumps
|
| 375 |
|
|
JMPUNC:
|
| 376 |
|
|
case(instruction[27:26])
|
| 377 |
|
|
2'b00:$display("JMP 0x%0x",instruction[25:0]);
|
| 378 |
|
|
2'b01://relative jump
|
| 379 |
|
|
$display("JMPR PC 0x%0x + offset %0d",pc,$signed(offset_w));
|
| 380 |
|
|
2'b10://call
|
| 381 |
|
|
$display("CALLR PC 0x%0x + offset %0d",pc,$signed(offset_w));
|
| 382 |
|
|
2'b11://ret
|
| 383 |
|
|
$display("RET to 0x%0x",pipe_id_out_w.val_dst);
|
| 384 |
|
|
endcase
|
| 385 |
|
|
|
| 386 |
|
|
JMPF:
|
| 387 |
|
|
case(instruction[27:26])
|
| 388 |
|
|
2'b00://jmpz
|
| 389 |
|
|
$display("JMPZ PC 0x%0x + offset %0d",pc,$signed(offset_w));
|
| 390 |
|
|
2'b01://jmpnz
|
| 391 |
|
|
$display("JMPNZ PC 0x%0x + offset %0d",pc,$signed(offset_w));
|
| 392 |
|
|
2'b10://jmpc
|
| 393 |
|
|
$display("JMPC PC 0x%0x + offset %0d",pc,$signed(offset_w));
|
| 394 |
|
|
2'b11://jmpnc
|
| 395 |
|
|
$display("JMPNC PC 0x%0x + offset %0d",pc,$signed(offset_w));
|
| 396 |
|
|
endcase
|
| 397 |
|
|
|
| 398 |
|
|
//Arithmetic
|
| 399 |
|
|
ALU:
|
| 400 |
|
|
case(instruction[27:25])
|
| 401 |
|
|
3'd0:$display("AND R%0d,R%0d,R%0d+%d",pipe_id_out_w.dst_r,pipe_id_out_w.src_r1,pipe_id_out_w.src_r2,$signed(pipe_id_out_w.incr_r2));
|
| 402 |
|
|
3'd1:$display("OR R%0d,R%0d,R%0d+%d",pipe_id_out_w.dst_r,pipe_id_out_w.src_r1,pipe_id_out_w.src_r2,$signed(pipe_id_out_w.incr_r2));
|
| 403 |
|
|
3'd2:$display("XOR R%0d,R%0d,R%0d+%d",pipe_id_out_w.dst_r,pipe_id_out_w.src_r1,pipe_id_out_w.src_r2,$signed(pipe_id_out_w.incr_r2));
|
| 404 |
|
|
3'd3:$display("ADD R%0d,R%0d,R%0d+%d",pipe_id_out_w.dst_r,pipe_id_out_w.src_r1,pipe_id_out_w.src_r2,$signed(pipe_id_out_w.incr_r2));
|
| 405 |
|
|
3'd4:$display("MUL R%0d,R%0d,R%0d+%d",pipe_id_out_w.dst_r,pipe_id_out_w.src_r1,pipe_id_out_w.src_r2,$signed(pipe_id_out_w.incr_r2));
|
| 406 |
|
|
3'd5:$display("SHL R%0d,R%0d,R%0d+%d",pipe_id_out_w.dst_r,pipe_id_out_w.src_r1,pipe_id_out_w.src_r2,$signed(pipe_id_out_w.incr_r2));
|
| 407 |
|
|
3'd6:$display("SHR R%0d,R%0d,R%0d+%d",pipe_id_out_w.dst_r,pipe_id_out_w.src_r1,pipe_id_out_w.src_r2,$signed(pipe_id_out_w.incr_r2));
|
| 408 |
|
|
default:$display("CMP R%0d with R%0d+%d",pipe_id_out_w.src_r1,pipe_id_out_w.src_r2,$signed(pipe_id_out_w.incr_r2));
|
| 409 |
|
|
endcase
|
| 410 |
|
|
|
| 411 |
|
|
LDRF:
|
| 412 |
|
|
case(instruction[27:26])
|
| 413 |
|
|
2'b00://ldrz
|
| 414 |
|
|
$display("LDRZ R%0d,R%0d,R%0d+%d",pipe_id_out_w.dst_r,pipe_id_out_w.src_r1,pipe_id_out_w.src_r2,$signed(pipe_id_out_w.incr_r2));
|
| 415 |
|
|
2'b01://ldrnz
|
| 416 |
|
|
$display("LDRNZ R%0d,R%0d,R%0d+%d",pipe_id_out_w.dst_r,pipe_id_out_w.src_r1,pipe_id_out_w.src_r2,$signed(pipe_id_out_w.incr_r2));
|
| 417 |
|
|
2'b10://ldrc
|
| 418 |
|
|
$display("LDRC R%0d,R%0d,R%0d+%d",pipe_id_out_w.dst_r,pipe_id_out_w.src_r1,pipe_id_out_w.src_r2,$signed(pipe_id_out_w.incr_r2));
|
| 419 |
|
|
2'b11://ldrnc
|
| 420 |
|
|
$display("LDRNC R%0d,R%0d,R%0d+%d",pipe_id_out_w.dst_r,pipe_id_out_w.src_r1,pipe_id_out_w.src_r2,$signed(pipe_id_out_w.incr_r2));
|
| 421 |
|
|
endcase
|
| 422 |
|
|
|
| 423 |
|
|
default:
|
| 424 |
|
|
if(!reset)
|
| 425 |
|
|
begin
|
| 426 |
|
|
$display("Unknown Command %x",instruction[31:28]);
|
| 427 |
|
|
$stop;
|
| 428 |
|
|
end
|
| 429 |
|
|
endcase
|
| 430 |
|
|
end
|
| 431 |
|
|
else
|
| 432 |
|
|
$display("[ID stage] STALLED!",instruction[31:28]);
|
| 433 |
|
|
end
|
| 434 |
|
|
//synthesys translate_on
|
| 435 |
|
|
end
|
| 436 |
|
|
|
| 437 |
|
|
endmodule
|
