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vinogradov |
//////////////////////////////////////////////////////////////////////////////////////////////
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// Project Qrisc32 is risc cpu implementation, purpose is studying
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// Digital System Design course at Kyoung Hee University during my PhD earning
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// Copyright (C) 2010 Vinogradov Viacheslav
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2.1 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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//
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//
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//////////////////////////////////////////////////////////////////////////////////////////////
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import risc_pack::*;
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module qrisc32_IF(
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input clk,reset,
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interface avm_instructions,//avalon master port only for reading instructions
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input pipe_stall,//feed back from MEM stage
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input new_address_valid,//feed back from EX stage
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input[31:0] new_address,//feed back from EX stage
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output bit[31:0] instruction,
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output bit[31:0] pc
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);
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import risc_pack::*;
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bit[2:0] offset_w;//
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bit[31:0] base_w;//
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wire[31:0] jump_address_w = base_w+offset_w;
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wire if_stall = avm_instructions.wait_req | pipe_stall;
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bit[31:0] stalled_adr0;
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bit[31:0] stalled_adr1;
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always_comb
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begin
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pc<=avm_instructions.address_r;//
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base_w=avm_instructions.address_r;
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offset_w=4;
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if(if_stall)
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offset_w=0;
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else
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if(new_address_valid)
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begin
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base_w=new_address;
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offset_w=0;
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end
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end
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always@(posedge clk)// or posedge reset)
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if(reset)
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begin
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avm_instructions.address_r<='0;//reset address!
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avm_instructions.rd<=1;//forever =1
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instruction<='0;//=ldr R0,R0 =nop
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end
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else
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begin
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if(~if_stall)
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begin
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instruction<=avm_instructions.data_r;
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avm_instructions.address_r<=jump_address_w;
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stalled_adr0<=jump_address_w;
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stalled_adr1<=stalled_adr0;
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end
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else
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begin
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avm_instructions.address_r<=stalled_adr0;
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//instruction<='0;
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//instruction<=avm_instructions.data_r;
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$display("[IF stage] Stalled->%s",(pipe_stall)?"Mem stage is stalled":"Fetching is stalled");
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end
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end
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endmodule
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