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vinogradov |
//////////////////////////////////////////////////////////////////////////////////////////////
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// Project Qrisc32 is risc cpu implementation, purpose is studying
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// Digital System Design course at Kyoung Hee University during my PhD earning
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// Copyright (C) 2010 Vinogradov Viacheslav
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2.1 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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//
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//
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//////////////////////////////////////////////////////////////////////////////////////////////
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import risc_pack::*;
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module qrisc32_MEM(
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input clk,reset,
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interface avm_data_read,//avalon master port only for reading data
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interface avm_data_write,//avalon master port only for writing data
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input pipe_struct pipe_mem_in,
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output pipe_struct pipe_mem_out,
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output bit pipe_stall,
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input verbose
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);
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import risc_pack::*;
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bit rd_stall;
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bit wr_stall;
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wire[31:0] addr_w = pipe_mem_in.val_r1;
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pipe_struct pipe_mem_in0,pipe_mem_in1;
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always_comb
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pipe_stall<=rd_stall | wr_stall;
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always@(posedge clk)
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if(reset)
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begin
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avm_data_read.address_r<='0;
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avm_data_read.rd<='0;
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avm_data_read.wr<='0;
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rd_stall<=0;
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pipe_mem_out<='0;
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pipe_mem_in0<='0;
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pipe_mem_in1<='0;
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end
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else
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begin
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if(pipe_mem_in.read_mem==1)
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avm_data_read.address_r<=addr_w;//asserted addr
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avm_data_read.rd<=pipe_mem_in.read_mem;//||pipe_mem_in0.read_mem||pipe_mem_in1.read_mem;
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pipe_mem_in0<=pipe_mem_in;//addr asserted
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pipe_mem_in1<=pipe_mem_in0;//just wait cycle
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if(avm_data_read.wait_req==0 && pipe_mem_in1.read_mem==1)// it has been read ok(sram access is 2 cycles)
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begin
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//if(~pipe_mem_in.write_reg)
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begin
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if(verbose)
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$display("[MEM stage] access to dst register");
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rd_stall<=0;
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pipe_mem_out<=pipe_mem_in;
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pipe_mem_out.dst_r<=pipe_mem_in1.dst_r;
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pipe_mem_out.val_dst<=avm_data_read.data_r;//result of read
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pipe_mem_out.write_reg<=1;
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end
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//else
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//if(~pipe_mem_in.incr_r2_enable)
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//begin
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// if(verbose)
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// $display("[MEM stage] access to src2 register");
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// rd_stall<=0;
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// pipe_mem_out<=pipe_mem_in;
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//
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// pipe_mem_out.src_r2<=pipe_mem_in1.dst_r;
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// pipe_mem_out.incr_r2_enable<=1;
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// pipe_mem_out.val_r2<=avm_data_read.data_r;//result of read
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//end
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//else
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//begin
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// if(verbose)
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// $display("[MEM stage] access to dst register and STALL pipeline!");
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// rd_stall<=1;
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// pipe_mem_out<=pipe_mem_in1;
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// pipe_mem_out.val_dst<=avm_data_read.data_r;//result of read
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//end
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end
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else
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begin
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rd_stall<=0;
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if(rd_stall)//if previous op was stalled
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begin
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pipe_mem_out<=pipe_mem_in0;
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end
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else
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begin
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pipe_mem_out<=pipe_mem_in;
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if(pipe_mem_in.read_mem)//if read access then
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pipe_mem_out.write_reg<='0;//clear write bit register
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end
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end
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end
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always@(posedge clk)
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if(reset)
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begin
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avm_data_write.address_r<='0;
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avm_data_write.data_w<='0;
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avm_data_write.rd<='0;
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avm_data_write.wr<='0;
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wr_stall<='0;
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end
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else
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begin
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if(pipe_mem_in.write_mem)
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begin
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avm_data_write.address_r<=addr_w;
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avm_data_write.data_w<=pipe_mem_in.val_dst;
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avm_data_write.wr<=1;
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wr_stall<=0;
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end
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else
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begin
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avm_data_write.wr<='0;
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wr_stall<=0;
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end
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end
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endmodule
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