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////////////////////////////////////////////////////////////////////////////////
//
// Filename:    llqspi.v
//
// Project:     Wishbone Controlled Quad SPI Flash Controller
//
// Purpose:     Reads/writes a word (user selectable number of bytes) of data
//              to/from a Quad SPI port.  The port is understood to be 
//              a normal SPI port unless the driver requests four bit mode.
//              When not in use, unlike our previous SPI work, no bits will
//              toggle.
//
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015,2017, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
// target there if the PDF file isn't present.)  If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
`default_nettype        none
//
`define QSPI_IDLE       3'h0
`define QSPI_START      3'h1
`define QSPI_BITS       3'h2
`define QSPI_READY      3'h3
`define QSPI_HOLDING    3'h4
`define QSPI_STOP       3'h5
`define QSPI_STOP_B     3'h6
 
// Modes
`define QSPI_MOD_SPI    2'b00
`define QSPI_MOD_QOUT   2'b10
`define QSPI_MOD_QIN    2'b11
 
module  llqspi(i_clk,
                // Module interface
                i_wr, i_hold, i_word, i_len, i_spd, i_dir,
                        o_word, o_valid, o_busy,
                // QSPI interface
                o_sck, o_cs_n, o_mod, o_dat, i_dat);
        input   wire            i_clk;
        // Chip interface
        //      Can send info
        //              i_dir = 1, i_spd = 0, i_hold = 0, i_wr = 1,
        //                      i_word = { 1'b0, 32'info to send },
        //                      i_len = # of bytes in word-1
        input   wire            i_wr, i_hold;
        input   wire    [31:0]   i_word;
        input   wire    [1:0]    i_len;  // 0=>8bits, 1=>16 bits, 2=>24 bits, 3=>32 bits
        input   wire            i_spd; // 0 -> normal QPI, 1 -> QSPI
        input   wire            i_dir; // 0 -> read, 1 -> write to SPI
        output  reg     [31:0]   o_word;
        output  reg             o_valid, o_busy;
        // Interface with the QSPI lines
        output  reg             o_sck;
        output  reg             o_cs_n;
        output  reg     [1:0]    o_mod;
        output  reg     [3:0]    o_dat;
        input           [3:0]    i_dat;
 
        // output       wire    [22:0]  o_dbg;
        // assign       o_dbg = { state, spi_len,
                // o_busy, o_valid, o_cs_n, o_sck, o_mod, o_dat, i_dat };
 
        // Timing:
        //
        //      Tick    Clk     BSY/WR  CS_n    BIT/MO  STATE
        //       0      1       0/0     1        -      
        //       1      1       0/1     1        -
        //       2      1       1/0     0         -      QSPI_START
        //       3      0        1/0     0         -      QSPI_START
        //       4      0        1/0     0         0      QSPI_BITS
        //       5      1       1/0     0         0      QSPI_BITS
        //       6      0        1/0     0         1      QSPI_BITS
        //       7      1       1/0     0         1      QSPI_BITS
        //       8      0        1/0     0         2      QSPI_BITS
        //       9      1       1/0     0         2      QSPI_BITS
        //      10      0        1/0     0         3      QSPI_BITS
        //      11      1       1/0     0         3      QSPI_BITS
        //      12      0        1/0     0         4      QSPI_BITS
        //      13      1       1/0     0         4      QSPI_BITS
        //      14      0        1/0     0         5      QSPI_BITS
        //      15      1       1/0     0         5      QSPI_BITS
        //      16      0        1/0     0         6      QSPI_BITS
        //      17      1       1/1     0         6      QSPI_BITS
        //      18      0        1/1     0         7      QSPI_READY
        //      19      1       0/1     0         7      QSPI_READY
        //      20      0        1/0/V   0         8      QSPI_BITS
        //      21      1       1/0     0         8      QSPI_BITS
        //      22      0        1/0     0         9      QSPI_BITS
        //      23      1       1/0     0         9      QSPI_BITS
        //      24      0        1/0     0        10      QSPI_BITS
        //      25      1       1/0     0        10      QSPI_BITS
        //      26      0        1/0     0        11      QSPI_BITS
        //      27      1       1/0     0        11      QSPI_BITS
        //      28      0        1/0     0        12      QSPI_BITS
        //      29      1       1/0     0        12      QSPI_BITS
        //      30      0        1/0     0        13      QSPI_BITS
        //      31      1       1/0     0        13      QSPI_BITS
        //      32      0        1/0     0        14      QSPI_BITS
        //      33      1       1/0     0        14      QSPI_BITS
        //      34      0        1/0     0        15      QSPI_READY
        //      35      1       1/0     0        15      QSPI_READY
        //      36      1       1/0/V   0         -      QSPI_STOP
        //      37      1       1/0     0         -      QSPI_STOPB
        //      38      1       1/0     1        -      QSPI_IDLE
        //      39      1       0/0     1        -
        // Now, let's switch from single bit to quad mode
        //      40      1       0/0     1        -      QSPI_IDLE
        //      41      1       0/1     1        -      QSPI_IDLE
        //      42      1       1/0     0         -      QSPI_START
        //      43      0        1/0     0         -      QSPI_START
        //      44      0        1/0     0         0      QSPI_BITS
        //      45      1       1/0     0         0      QSPI_BITS
        //      46      0        1/0     0         1      QSPI_BITS
        //      47      1       1/0     0         1      QSPI_BITS
        //      48      0        1/0     0         2      QSPI_BITS
        //      49      1       1/0     0         2      QSPI_BITS
        //      50      0        1/0     0         3      QSPI_BITS
        //      51      1       1/0     0         3      QSPI_BITS
        //      52      0        1/0     0         4      QSPI_BITS
        //      53      1       1/0     0         4      QSPI_BITS
        //      54      0        1/0     0         5      QSPI_BITS
        //      55      1       1/0     0         5      QSPI_BITS
        //      56      0        1/0     0         6      QSPI_BITS
        //      57      1       1/1/QR  0         6      QSPI_BITS
        //      58      0        1/1/QR  0         7      QSPI_READY
        //      59      1       0/1/QR  0         7      QSPI_READY
        //      60      0        1/0/?/V 0         8-11   QSPI_BITS
        //      61      1       1/0/?   0         8-11   QSPI_BITS
        //      62      0        1/0/?   0         12-15  QSPI_BITS
        //      63      1       1/0/?   0         12-15  QSPI_BITS
        //      64      1       1/0/?/V 0        -       QSPI_STOP
        //      65      1       1/0/?   0        -       QSPI_STOPB
        //      66      1       1/0/?   1       -       QSPI_IDLE
        //      67      1       0/0     1       -       QSPI_IDLE
        // Now let's try something entirely in Quad read mode, from the
        // beginning
        //      68      1       0/1/QR  1       -       QSPI_IDLE
        //      69      1       1/0     0        -       QSPI_START
        //      70      0        1/0     0        -       QSPI_START
        //      71      0        1/0     0        0-3     QSPI_BITS
        //      72      1       1/0     0        0-3     QSPI_BITS
        //      73      0        1/1/QR  0        4-7     QSPI_BITS
        //      74      1       0/1/QR  0        4-7     QSPI_BITS
        //      75      0        1/?/?/V 0        8-11    QSPI_BITS
        //      76      1       1/?/?   0        8-11    QSPI_BITS
        //      77      0        1/1/QR  0        12-15   QSPI_BITS
        //      78      1       0/1/QR  0        12-15   QSPI_BITS
        //      79      0        1/?/?/V 0        16-19   QSPI_BITS
        //      80      1       1/0     0        16-19   QSPI_BITS
        //      81      0        1/0     0        20-23   QSPI_BITS
        //      82      1       1/0     0        20-23   QSPI_BITS
        //      83      1       1/0/V   0        -       QSPI_STOP
        //      84      1       1/0     0        -       QSPI_STOPB
        //      85      1       1/0     1       -       QSPI_IDLE
        //      86      1       0/0     1       -       QSPI_IDLE
 
        wire    i_miso;
        assign  i_miso = i_dat[1];
 
        reg             r_spd, r_dir;
        reg     [5:0]    spi_len;
        reg     [31:0]   r_word;
        reg     [30:0]   r_input;
        reg     [2:0]    state;
        initial state = `QSPI_IDLE;
        initial o_sck   = 1'b1;
        initial o_cs_n  = 1'b1;
        initial o_dat   = 4'hd;
        initial o_valid = 1'b0;
        initial o_busy  = 1'b0;
        initial r_input = 31'h000;
        initial o_mod   = `QSPI_MOD_SPI;
        always @(posedge i_clk)
                if ((state == `QSPI_IDLE)&&(o_sck))
                begin
                        o_cs_n <= 1'b1;
                        o_valid <= 1'b0;
                        o_busy  <= 1'b0;
                        o_mod <= `QSPI_MOD_SPI;
                        r_word <= i_word;
                        r_spd <= i_spd;
                        r_dir <= i_dir;
                        if (i_wr)
                        begin
                                state <= `QSPI_START;
                                spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8;
                                o_cs_n <= 1'b0;
                                // o_sck <= 1'b1;
                                o_busy <= 1'b1;
                        end
                end else if (state == `QSPI_START)
                begin // We come in here with sck high, stay here 'til sck is low
                        o_sck <= 1'b0;
                        if (o_sck == 1'b0)
                        begin
                                state <= `QSPI_BITS;
                                spi_len<= spi_len - ( (r_spd)? 6'h4 : 6'h1 );
                                if (r_spd)
                                        r_word <= { r_word[27:0], 4'h0 };
                                else
                                        r_word <= { r_word[30:0], 1'b0 };
                        end
                        o_mod <= (r_spd) ? { 1'b1, r_dir } : `QSPI_MOD_SPI;
                        o_cs_n <= 1'b0;
                        o_busy <= 1'b1;
                        o_valid <= 1'b0;
                        if (r_spd)
                                o_dat <= r_word[31:28];
                        else
                                o_dat <= { 3'b110, r_word[31] };
                end else if (~o_sck)
                begin
                        o_sck <= 1'b1;
                        o_busy <= ((state != `QSPI_READY)||(~i_wr));
                        o_valid <= 1'b0;
                end else if (state == `QSPI_BITS)
                begin
                        // Should enter into here with at least a spi_len
                        // of one, perhaps more
                        o_sck <= 1'b0;
                        o_busy <= 1'b1;
                        if (r_spd)
                        begin
                                o_dat <= r_word[31:28];
                                r_word <= { r_word[27:0], 4'h0 };
                                spi_len <= spi_len - 6'h4;
                                if (spi_len == 6'h4)
                                        state <= `QSPI_READY;
                        end else begin
                                o_dat <= { 3'b110, r_word[31] };
                                r_word <= { r_word[30:0], 1'b0 };
                                spi_len <= spi_len - 6'h1;
                                if (spi_len == 6'h1)
                                        state <= `QSPI_READY;
                        end
 
                        o_valid <= 1'b0;
                        if (~o_mod[1])
                                r_input <= { r_input[29:0], i_miso };
                        else if (o_mod[1])
                                r_input <= { r_input[26:0], i_dat };
                end else if (state == `QSPI_READY)
                begin
                        o_valid <= 1'b0;
                        o_cs_n <= 1'b0;
                        o_busy <= 1'b1;
                        // This is the state on the last clock (both low and
                        // high clocks) of the data.  Data is valid during
                        // this state.  Here we chose to either STOP or
                        // continue and transmit more.
                        o_sck <= (i_hold); // No clocks while holding
                        r_spd <= i_spd;
                        r_dir <= i_dir;
                        if (i_spd)
                        begin
                                r_word <= { i_word[27:0], 4'h0 };
                                spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8 - 6'h4;
                        end else begin
                                r_word <= { i_word[30:0], 1'b0 };
                                spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8 - 6'h1;
                        end
                        if((~o_busy)&&(i_wr))// Acknowledge a new request
                        begin
                                state <= `QSPI_BITS;
                                o_busy <= 1'b1;
                                o_sck <= 1'b0;
 
                                // Read the new request off the bus
                                // Set up the first bits on the bus
                                o_mod <= (i_spd) ? { 1'b1, i_dir } : `QSPI_MOD_SPI;
                                if (i_spd)
                                        o_dat <= i_word[31:28];
                                else
                                        o_dat <= { 3'b110, i_word[31] };
 
                        end else begin
                                o_sck <= 1'b1;
                                state <= (i_hold)?`QSPI_HOLDING : `QSPI_STOP;
                                o_busy <= (~i_hold);
                        end
 
                        // Read a bit upon any transition
                        o_valid <= 1'b1;
                        if (~o_mod[1])
                        begin
                                r_input <= { r_input[29:0], i_miso };
                                o_word  <= { r_input[30:0], i_miso };
                        end else if (o_mod[1])
                        begin
                                r_input <= { r_input[26:0], i_dat };
                                o_word  <= { r_input[27:0], i_dat };
                        end
                end else if (state == `QSPI_HOLDING)
                begin
                        // We need this state so that the o_valid signal
                        // can get strobed with our last result.  Otherwise
                        // we could just sit in READY waiting for a new command.
                        //
                        // Incidentally, the change producing this state was
                        // the result of a nasty race condition.  See the
                        // commends in wbqspiflash for more details.
                        //
                        o_valid <= 1'b0;
                        o_cs_n <= 1'b0;
                        o_busy <= 1'b0;
                        if((~o_busy)&&(i_wr))// Acknowledge a new request
                        begin
                                state  <= `QSPI_BITS;
                                o_busy <= 1'b1;
                                o_sck  <= 1'b0;
 
                                // Read the new request off the bus
                                r_spd <= i_spd;
                                r_dir <= i_dir;
                                // Set up the first bits on the bus
                                o_mod<=(i_spd)?{ 1'b1, i_dir } : `QSPI_MOD_SPI;
                                if (i_spd)
                                begin
                                        o_dat <= i_word[31:28];
                                        r_word <= { i_word[27:0], 4'h0 };
                                        spi_len<= { 1'b0, i_len, 3'b100 };
                                end else begin
                                        o_dat <= { 3'b110, i_word[31] };
                                        r_word <= { i_word[30:0], 1'b0 };
                                        spi_len<= { 1'b0, i_len, 3'b111 };
                                end
                        end else begin
                                o_sck <= 1'b1;
                                state <= (i_hold)?`QSPI_HOLDING : `QSPI_STOP;
                                o_busy <= (~i_hold);
                        end
                end else if (state == `QSPI_STOP)
                begin
                        o_sck   <= 1'b1; // Stop the clock
                        o_valid <= 1'b0; // Output may have just been valid, but no more
                        o_busy  <= 1'b1; // Still busy till port is clear
                        state <= `QSPI_STOP_B;
                        o_mod <= `QSPI_MOD_SPI;
                end else if (state == `QSPI_STOP_B)
                begin
                        o_cs_n <= 1'b1;
                        o_sck <= 1'b1;
                        // Do I need this????
                        // spi_len <= 3; // Minimum CS high time before next cmd
                        state <= `QSPI_IDLE;
                        o_valid <= 1'b0;
                        o_busy <= 1'b1;
                        o_mod <= `QSPI_MOD_SPI;
                end else begin // Invalid states, should never get here
                        state   <= `QSPI_STOP;
                        o_valid <= 1'b0;
                        o_busy  <= 1'b1;
                        o_cs_n  <= 1'b1;
                        o_sck   <= 1'b1;
                        o_mod   <= `QSPI_MOD_SPI;
                        o_dat   <= 4'hd;
                end
 
endmodule
 

Line No.	Rev	Author	Line
1	16	dgisselq	`////////////////////////////////////////////////////////////////////////////////`
2	2	dgisselq	`//`
3			`// Filename: llqspi.v`
4			`//`
5	3	dgisselq	`// Project: Wishbone Controlled Quad SPI Flash Controller`
6	2	dgisselq	`//`
7			`// Purpose: Reads/writes a word (user selectable number of bytes) of data`
8			`// to/from a Quad SPI port. The port is understood to be`
9			`// a normal SPI port unless the driver requests four bit mode.`
10			`// When not in use, unlike our previous SPI work, no bits will`
11			`// toggle.`
12			`//`
13	16	dgisselq	`// Creator: Dan Gisselquist, Ph.D.`
14	8	dgisselq	`// Gisselquist Technology, LLC`
15	2	dgisselq	`//`
16	16	dgisselq	`////////////////////////////////////////////////////////////////////////////////`
17	2	dgisselq	`//`
18	16	dgisselq	`// Copyright (C) 2015,2017, Gisselquist Technology, LLC`
19	2	dgisselq	`//`
20	3	dgisselq	`// This program is free software (firmware): you can redistribute it and/or`
21			`// modify it under the terms of the GNU General Public License as published`
22			`// by the Free Software Foundation, either version 3 of the License, or (at`
23			`// your option) any later version.`
24			`//`
25			`// This program is distributed in the hope that it will be useful, but WITHOUT`
26			`// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or`
27			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
28			`// for more details.`
29			`//`
30			`// You should have received a copy of the GNU General Public License along`
31	16	dgisselq	`// with this program. (It's in the $(ROOT)/doc directory. Run make with no`
32	3	dgisselq	`// target there if the PDF file isn't present.) If not, see`
33			`// <http://www.gnu.org/licenses/> for a copy.`
34			`//`
35			`// License: GPL, v3, as defined and found on www.gnu.org,`
36			`// http://www.gnu.org/licenses/gpl.html`
37			`//`
38			`//`
39	16	dgisselq	`////////////////////////////////////////////////////////////////////////////////`
40	14	dgisselq	`//`
41			`//`
42			`default_nettype none
43			`//`
44	4	dgisselq	`define QSPI_IDLE 3'h0
45			`define QSPI_START 3'h1
46			`define QSPI_BITS 3'h2
47			`define QSPI_READY 3'h3
48			`define QSPI_HOLDING 3'h4
49			`define QSPI_STOP 3'h5
50			`define QSPI_STOP_B 3'h6
51	2	dgisselq
52			`// Modes`
53			`define QSPI_MOD_SPI 2'b00
54			`define QSPI_MOD_QOUT 2'b10
55			`define QSPI_MOD_QIN 2'b11
56
57			`module llqspi(i_clk,`
58			`// Module interface`
59			`i_wr, i_hold, i_word, i_len, i_spd, i_dir,`
60			`o_word, o_valid, o_busy,`
61			`// QSPI interface`
62	3	dgisselq	`o_sck, o_cs_n, o_mod, o_dat, i_dat);`
63	14	dgisselq	`input wire i_clk;`
64	2	dgisselq	`// Chip interface`
65			`// Can send info`
66			`// i_dir = 1, i_spd = 0, i_hold = 0, i_wr = 1,`
67			`// i_word = { 1'b0, 32'info to send },`
68			`// i_len = # of bytes in word-1`
69	14	dgisselq	`input wire i_wr, i_hold;`
70			`input wire [31:0] i_word;`
71			`input wire [1:0] i_len; // 0=>8bits, 1=>16 bits, 2=>24 bits, 3=>32 bits`
72			`input wire i_spd; // 0 -> normal QPI, 1 -> QSPI`
73			`input wire i_dir; // 0 -> read, 1 -> write to SPI`
74	2	dgisselq	`output reg [31:0] o_word;`
75			`output reg o_valid, o_busy;`
76			`// Interface with the QSPI lines`
77			`output reg o_sck;`
78			`output reg o_cs_n;`
79			`output reg [1:0] o_mod;`
80			`output reg [3:0] o_dat;`
81			`input [3:0] i_dat;`
82
83	7	dgisselq	`// output wire [22:0] o_dbg;`
84			`// assign o_dbg = { state, spi_len,`
85			`// o_busy, o_valid, o_cs_n, o_sck, o_mod, o_dat, i_dat };`
86
87	2	dgisselq	`// Timing:`
88			`//`
89			`// Tick Clk BSY/WR CS_n BIT/MO STATE`
90			`// 0 1 0/0 1 -`
91			`// 1 1 0/1 1 -`
92			`// 2 1 1/0 0 - QSPI_START`
93			`// 3 0 1/0 0 - QSPI_START`
94			`// 4 0 1/0 0 0 QSPI_BITS`
95			`// 5 1 1/0 0 0 QSPI_BITS`
96			`// 6 0 1/0 0 1 QSPI_BITS`
97			`// 7 1 1/0 0 1 QSPI_BITS`
98			`// 8 0 1/0 0 2 QSPI_BITS`
99			`// 9 1 1/0 0 2 QSPI_BITS`
100			`// 10 0 1/0 0 3 QSPI_BITS`
101			`// 11 1 1/0 0 3 QSPI_BITS`
102			`// 12 0 1/0 0 4 QSPI_BITS`
103			`// 13 1 1/0 0 4 QSPI_BITS`
104			`// 14 0 1/0 0 5 QSPI_BITS`
105			`// 15 1 1/0 0 5 QSPI_BITS`
106			`// 16 0 1/0 0 6 QSPI_BITS`
107			`// 17 1 1/1 0 6 QSPI_BITS`
108			`// 18 0 1/1 0 7 QSPI_READY`
109			`// 19 1 0/1 0 7 QSPI_READY`
110			`// 20 0 1/0/V 0 8 QSPI_BITS`
111			`// 21 1 1/0 0 8 QSPI_BITS`
112			`// 22 0 1/0 0 9 QSPI_BITS`
113			`// 23 1 1/0 0 9 QSPI_BITS`
114			`// 24 0 1/0 0 10 QSPI_BITS`
115			`// 25 1 1/0 0 10 QSPI_BITS`
116			`// 26 0 1/0 0 11 QSPI_BITS`
117			`// 27 1 1/0 0 11 QSPI_BITS`
118			`// 28 0 1/0 0 12 QSPI_BITS`
119			`// 29 1 1/0 0 12 QSPI_BITS`
120			`// 30 0 1/0 0 13 QSPI_BITS`
121			`// 31 1 1/0 0 13 QSPI_BITS`
122			`// 32 0 1/0 0 14 QSPI_BITS`
123			`// 33 1 1/0 0 14 QSPI_BITS`
124			`// 34 0 1/0 0 15 QSPI_READY`
125			`// 35 1 1/0 0 15 QSPI_READY`
126			`// 36 1 1/0/V 0 - QSPI_STOP`
127			`// 37 1 1/0 0 - QSPI_STOPB`
128			`// 38 1 1/0 1 - QSPI_IDLE`
129			`// 39 1 0/0 1 -`
130			`// Now, let's switch from single bit to quad mode`
131			`// 40 1 0/0 1 - QSPI_IDLE`
132			`// 41 1 0/1 1 - QSPI_IDLE`
133			`// 42 1 1/0 0 - QSPI_START`
134			`// 43 0 1/0 0 - QSPI_START`
135			`// 44 0 1/0 0 0 QSPI_BITS`
136			`// 45 1 1/0 0 0 QSPI_BITS`
137			`// 46 0 1/0 0 1 QSPI_BITS`
138			`// 47 1 1/0 0 1 QSPI_BITS`
139			`// 48 0 1/0 0 2 QSPI_BITS`
140			`// 49 1 1/0 0 2 QSPI_BITS`
141			`// 50 0 1/0 0 3 QSPI_BITS`
142			`// 51 1 1/0 0 3 QSPI_BITS`
143			`// 52 0 1/0 0 4 QSPI_BITS`
144			`// 53 1 1/0 0 4 QSPI_BITS`
145			`// 54 0 1/0 0 5 QSPI_BITS`
146			`// 55 1 1/0 0 5 QSPI_BITS`
147			`// 56 0 1/0 0 6 QSPI_BITS`
148			`// 57 1 1/1/QR 0 6 QSPI_BITS`
149			`// 58 0 1/1/QR 0 7 QSPI_READY`
150			`// 59 1 0/1/QR 0 7 QSPI_READY`
151			`// 60 0 1/0/?/V 0 8-11 QSPI_BITS`
152			`// 61 1 1/0/? 0 8-11 QSPI_BITS`
153			`// 62 0 1/0/? 0 12-15 QSPI_BITS`
154			`// 63 1 1/0/? 0 12-15 QSPI_BITS`
155			`// 64 1 1/0/?/V 0 - QSPI_STOP`
156			`// 65 1 1/0/? 0 - QSPI_STOPB`
157			`// 66 1 1/0/? 1 - QSPI_IDLE`
158			`// 67 1 0/0 1 - QSPI_IDLE`
159			`// Now let's try something entirely in Quad read mode, from the`
160			`// beginning`
161			`// 68 1 0/1/QR 1 - QSPI_IDLE`
162			`// 69 1 1/0 0 - QSPI_START`
163			`// 70 0 1/0 0 - QSPI_START`
164			`// 71 0 1/0 0 0-3 QSPI_BITS`
165			`// 72 1 1/0 0 0-3 QSPI_BITS`
166			`// 73 0 1/1/QR 0 4-7 QSPI_BITS`
167			`// 74 1 0/1/QR 0 4-7 QSPI_BITS`
168			`// 75 0 1/?/?/V 0 8-11 QSPI_BITS`
169			`// 76 1 1/?/? 0 8-11 QSPI_BITS`
170			`// 77 0 1/1/QR 0 12-15 QSPI_BITS`
171			`// 78 1 0/1/QR 0 12-15 QSPI_BITS`
172			`// 79 0 1/?/?/V 0 16-19 QSPI_BITS`
173			`// 80 1 1/0 0 16-19 QSPI_BITS`
174			`// 81 0 1/0 0 20-23 QSPI_BITS`
175			`// 82 1 1/0 0 20-23 QSPI_BITS`
176			`// 83 1 1/0/V 0 - QSPI_STOP`
177			`// 84 1 1/0 0 - QSPI_STOPB`
178			`// 85 1 1/0 1 - QSPI_IDLE`
179			`// 86 1 0/0 1 - QSPI_IDLE`
180
181			`wire i_miso;`
182			`assign i_miso = i_dat[1];`
183
184			`reg r_spd, r_dir;`
185			`reg [5:0] spi_len;`
186			`reg [31:0] r_word;`
187			`reg [30:0] r_input;`
188			`reg [2:0] state;`
189			initial state = `QSPI_IDLE;
190			`initial o_sck = 1'b1;`
191			`initial o_cs_n = 1'b1;`
192			`initial o_dat = 4'hd;`
193			`initial o_valid = 1'b0;`
194			`initial o_busy = 1'b0;`
195			`initial r_input = 31'h000;`
196	16	dgisselq	initial o_mod = `QSPI_MOD_SPI;
197	2	dgisselq	`always @(posedge i_clk)`
198			if ((state == `QSPI_IDLE)&&(o_sck))
199			`begin`
200			`o_cs_n <= 1'b1;`
201			`o_valid <= 1'b0;`
202			`o_busy <= 1'b0;`
203			o_mod <= `QSPI_MOD_SPI;
204	16	dgisselq	`r_word <= i_word;`
205			`r_spd <= i_spd;`
206			`r_dir <= i_dir;`
207	2	dgisselq	`if (i_wr)`
208			`begin`
209			state <= `QSPI_START;
210			`spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8;`
211			`o_cs_n <= 1'b0;`
212	16	dgisselq	`// o_sck <= 1'b1;`
213	2	dgisselq	`o_busy <= 1'b1;`
214			`end`
215			end else if (state == `QSPI_START)
216			`begin // We come in here with sck high, stay here 'til sck is low`
217			`o_sck <= 1'b0;`
218			`if (o_sck == 1'b0)`
219			`begin`
220			state <= `QSPI_BITS;
221			`spi_len<= spi_len - ( (r_spd)? 6'h4 : 6'h1 );`
222			`if (r_spd)`
223			`r_word <= { r_word[27:0], 4'h0 };`
224			`else`
225			`r_word <= { r_word[30:0], 1'b0 };`
226			`end`
227			o_mod <= (r_spd) ? { 1'b1, r_dir } : `QSPI_MOD_SPI;
228			`o_cs_n <= 1'b0;`
229			`o_busy <= 1'b1;`
230			`o_valid <= 1'b0;`
231			`if (r_spd)`
232			`o_dat <= r_word[31:28];`
233	16	dgisselq	`else`
234	2	dgisselq	`o_dat <= { 3'b110, r_word[31] };`
235			`end else if (~o_sck)`
236			`begin`
237			`o_sck <= 1'b1;`
238			o_busy <= ((state != `QSPI_READY)\|\|(~i_wr));
239			`o_valid <= 1'b0;`
240			end else if (state == `QSPI_BITS)
241			`begin`
242			`// Should enter into here with at least a spi_len`
243			`// of one, perhaps more`
244			`o_sck <= 1'b0;`
245			`o_busy <= 1'b1;`
246			`if (r_spd)`
247			`begin`
248			`o_dat <= r_word[31:28];`
249			`r_word <= { r_word[27:0], 4'h0 };`
250			`spi_len <= spi_len - 6'h4;`
251			`if (spi_len == 6'h4)`
252			state <= `QSPI_READY;
253			`end else begin`
254			`o_dat <= { 3'b110, r_word[31] };`
255			`r_word <= { r_word[30:0], 1'b0 };`
256			`spi_len <= spi_len - 6'h1;`
257			`if (spi_len == 6'h1)`
258			state <= `QSPI_READY;
259			`end`
260
261			`o_valid <= 1'b0;`
262			`if (~o_mod[1])`
263			`r_input <= { r_input[29:0], i_miso };`
264			`else if (o_mod[1])`
265			`r_input <= { r_input[26:0], i_dat };`
266			end else if (state == `QSPI_READY)
267			`begin`
268			`o_valid <= 1'b0;`
269			`o_cs_n <= 1'b0;`
270			`o_busy <= 1'b1;`
271			`// This is the state on the last clock (both low and`
272			`// high clocks) of the data. Data is valid during`
273			`// this state. Here we chose to either STOP or`
274			`// continue and transmit more.`
275	4	dgisselq	`o_sck <= (i_hold); // No clocks while holding`
276	16	dgisselq	`r_spd <= i_spd;`
277			`r_dir <= i_dir;`
278			`if (i_spd)`
279			`begin`
280			`r_word <= { i_word[27:0], 4'h0 };`
281			`spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8 - 6'h4;`
282			`end else begin`
283			`r_word <= { i_word[30:0], 1'b0 };`
284			`spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8 - 6'h1;`
285			`end`
286	2	dgisselq	`if((~o_busy)&&(i_wr))// Acknowledge a new request`
287			`begin`
288			state <= `QSPI_BITS;
289			`o_busy <= 1'b1;`
290			`o_sck <= 1'b0;`
291
292			`// Read the new request off the bus`
293			`// Set up the first bits on the bus`
294			o_mod <= (i_spd) ? { 1'b1, i_dir } : `QSPI_MOD_SPI;
295			`if (i_spd)`
296			`o_dat <= i_word[31:28];`
297	16	dgisselq	`else`
298	2	dgisselq	`o_dat <= { 3'b110, i_word[31] };`
299
300			`end else begin`
301			`o_sck <= 1'b1;`
302	4	dgisselq	state <= (i_hold)?`QSPI_HOLDING : `QSPI_STOP;
303			`o_busy <= (~i_hold);`
304	16	dgisselq	`end`
305	2	dgisselq
306	16	dgisselq	`// Read a bit upon any transition`
307			`o_valid <= 1'b1;`
308			`if (~o_mod[1])`
309			`begin`
310			`r_input <= { r_input[29:0], i_miso };`
311			`o_word <= { r_input[30:0], i_miso };`
312			`end else if (o_mod[1])`
313			`begin`
314			`r_input <= { r_input[26:0], i_dat };`
315			`o_word <= { r_input[27:0], i_dat };`
316	2	dgisselq	`end`
317	4	dgisselq	end else if (state == `QSPI_HOLDING)
318			`begin`
319			`// We need this state so that the o_valid signal`
320			`// can get strobed with our last result. Otherwise`
321			`// we could just sit in READY waiting for a new command.`
322			`//`
323			`// Incidentally, the change producing this state was`
324			`// the result of a nasty race condition. See the`
325			`// commends in wbqspiflash for more details.`
326			`//`
327			`o_valid <= 1'b0;`
328			`o_cs_n <= 1'b0;`
329			`o_busy <= 1'b0;`
330			`if((~o_busy)&&(i_wr))// Acknowledge a new request`
331			`begin`
332			state <= `QSPI_BITS;
333			`o_busy <= 1'b1;`
334			`o_sck <= 1'b0;`
335
336			`// Read the new request off the bus`
337			`r_spd <= i_spd;`
338			`r_dir <= i_dir;`
339			`// Set up the first bits on the bus`
340			o_mod<=(i_spd)?{ 1'b1, i_dir } : `QSPI_MOD_SPI;
341			`if (i_spd)`
342			`begin`
343			`o_dat <= i_word[31:28];`
344			`r_word <= { i_word[27:0], 4'h0 };`
345			`spi_len<= { 1'b0, i_len, 3'b100 };`
346			`end else begin`
347			`o_dat <= { 3'b110, i_word[31] };`
348			`r_word <= { i_word[30:0], 1'b0 };`
349			`spi_len<= { 1'b0, i_len, 3'b111 };`
350			`end`
351			`end else begin`
352			`o_sck <= 1'b1;`
353			state <= (i_hold)?`QSPI_HOLDING : `QSPI_STOP;
354			`o_busy <= (~i_hold);`
355			`end`
356	2	dgisselq	end else if (state == `QSPI_STOP)
357			`begin`
358			`o_sck <= 1'b1; // Stop the clock`
359			`o_valid <= 1'b0; // Output may have just been valid, but no more`
360			`o_busy <= 1'b1; // Still busy till port is clear`
361			state <= `QSPI_STOP_B;
362			o_mod <= `QSPI_MOD_SPI;
363			end else if (state == `QSPI_STOP_B)
364			`begin`
365			`o_cs_n <= 1'b1;`
366			`o_sck <= 1'b1;`
367			`// Do I need this????`
368			`// spi_len <= 3; // Minimum CS high time before next cmd`
369			state <= `QSPI_IDLE;
370			`o_valid <= 1'b0;`
371			`o_busy <= 1'b1;`
372			o_mod <= `QSPI_MOD_SPI;
373			`end else begin // Invalid states, should never get here`
374			state <= `QSPI_STOP;
375			`o_valid <= 1'b0;`
376			`o_busy <= 1'b1;`
377			`o_cs_n <= 1'b1;`
378			`o_sck <= 1'b1;`
379			o_mod <= `QSPI_MOD_SPI;
380			`o_dat <= 4'hd;`
381			`end`
382
383			`endmodule`
384

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