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///////////////////////////////////////////////////////////////////////////
//
// Filename:    wbspiflash.v
//
// Project:     Wishbone Controlled Quad SPI Flash Controller
//
// Purpose:     Access a Quad SPI flash via a WISHBONE interface.  This
//              includes both read and write (and erase) commands to the SPI
//              flash.  All read/write commands are accomplished using the
//              high speed (4-bit) interface.  Further, the device will be
//              left/kept in the 4-bit read interface mode between accesses,
//              for a minimum read latency.
//
//      Wishbone Registers (See spec sheet for more detail):
//      0: local config(r) / erase commands(w) / deep power down cmds / etc.
//      R: (Write in Progress), (dirty-block), (spi_port_busy), 1'b0, 9'h00,
//              { last_erased_sector, 14'h00 } if (WIP)
//              else { current_sector_being_erased, 14'h00 }
//              current if write in progress, last if written
//      W: (1'b1 to erase), (12'h ignored), next_erased_block, 14'h ignored)
//      1: Configuration register
//      2: Status register (R/w)
//      3: Read ID (read only)
//      (19 bits): Data (R/w, but expect writes to take a while)
//              
//
// Creator:     Dan Gisselquist
//              Gisselquist Technology, LLC
//
///////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.)  If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//
//
///////////////////////////////////////////////////////////////////////////
//
`include "flash_config.v"
//
`define WBQSPI_RESET            0
`define WBQSPI_RESET_QUADMODE   1
`define WBQSPI_IDLE             2
`define WBQSPI_RDIDLE           3       // Idle, but in fast read mode
`define WBQSPI_WBDECODE         4
`define WBQSPI_RD_DUMMY         5
`define WBQSPI_QRD_ADDRESS      6
`define WBQSPI_QRD_DUMMY        7
`define WBQSPI_READ_CMD         8
`define WBQSPI_READ_DATA        9
`define WBQSPI_WAIT_TIL_RDIDLE  10
`define WBQSPI_READ_ID_CMD      11
`define WBQSPI_READ_ID          12
`define WBQSPI_READ_STATUS      13
`define WBQSPI_READ_CONFIG      14
`define WBQSPI_WAIT_TIL_IDLE    15
//
//
`ifndef READ_ONLY
//
`define WBQSPI_WAIT_WIP_CLEAR   16
`define WBQSPI_CHECK_WIP_CLEAR  17
`define WBQSPI_CHECK_WIP_DONE   18
`define WBQSPI_WEN              19
`define WBQSPI_PP               20      // Program page
`define WBQSPI_QPP              21      // Program page, 4 bit mode
`define WBQSPI_WR_DATA          22
`define WBQSPI_WR_BUS_CYCLE     23
`define WBQSPI_WRITE_STATUS     24
`define WBQSPI_WRITE_CONFIG     25
`define WBQSPI_ERASE_WEN        26
`define WBQSPI_ERASE_CMD        27
`define WBQSPI_ERASE_BLOCK      28
`define WBQSPI_CLEAR_STATUS     29
`define WBQSPI_IDLE_CHECK_WIP   30
//
`endif
 
module  wbqspiflash(i_clk_100mhz,
                // Internal wishbone connections
                i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we,
                i_wb_addr, i_wb_data,
                // Wishbone return values
                o_wb_ack, o_wb_stall, o_wb_data,
                // Quad Spi connections to the external device
                o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
                o_interrupt);
        parameter       ADDRESS_WIDTH=22;
        input                   i_clk_100mhz;
        // Wishbone, inputs first
        input                   i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we;
        input           [(ADDRESS_WIDTH-3):0]    i_wb_addr;
        input           [31:0]   i_wb_data;
        // then outputs
        output  reg             o_wb_ack;
        output  reg             o_wb_stall;
        output  reg     [31:0]   o_wb_data;
        // Quad SPI control wires
        output  wire            o_qspi_sck, o_qspi_cs_n;
        output  wire    [1:0]    o_qspi_mod;
        output  wire    [3:0]    o_qspi_dat;
        input           [3:0]    i_qspi_dat;
        // Interrupt line
        output  reg             o_interrupt;
        // output       wire    [31:0]  o_debug;
 
        reg             spi_wr, spi_hold, spi_spd, spi_dir;
        reg     [31:0]   spi_in;
        reg     [1:0]    spi_len;
        wire    [31:0]   spi_out;
        wire            spi_valid, spi_busy;
        wire            w_qspi_sck, w_qspi_cs_n;
        wire    [3:0]    w_qspi_dat;
        wire    [1:0]    w_qspi_mod;
        // wire [22:0]  spi_dbg;
        llqspi  lldriver(i_clk_100mhz,
                        spi_wr, spi_hold, spi_in, spi_len, spi_spd, spi_dir,
                                spi_out, spi_valid, spi_busy,
                        w_qspi_sck, w_qspi_cs_n, w_qspi_mod, w_qspi_dat,
                                i_qspi_dat);
 
        // Erase status tracking
        reg             write_in_progress, write_protect;
        reg     [(ADDRESS_WIDTH-17):0]   erased_sector;
        reg             dirty_sector;
        initial begin
                write_in_progress = 1'b0;
                erased_sector = 0;
                dirty_sector  = 1'b1;
                write_protect = 1'b1;
        end
 
        reg     [7:0]    last_status;
        reg             quad_mode_enabled;
        reg             spif_cmd, spif_override;
        reg     [(ADDRESS_WIDTH-3):0]    spif_addr;
        reg     [31:0]   spif_data;
        reg     [5:0]    state;
        reg             spif_ctrl, spif_req;
        wire    [(ADDRESS_WIDTH-17):0]   spif_sector;
        assign  spif_sector = spif_addr[(ADDRESS_WIDTH-3):14];
 
        // assign       o_debug = { spi_wr, spi_spd, spi_hold, state, spi_dbg };
 
        initial state = `WBQSPI_RESET;
        initial o_wb_ack   = 1'b0;
        initial o_wb_stall = 1'b1;
        initial spi_wr     = 1'b0;
        initial spi_len    = 2'b00;
        initial quad_mode_enabled = 1'b0;
        initial o_interrupt = 1'b0;
        always @(posedge i_clk_100mhz)
        begin
        spif_override <= 1'b0;
        if (state == `WBQSPI_RESET)
        begin
                // From a reset, we should
                //      Enable the Quad I/O mode
                //      Disable the Write protection bits in the status register
                //      Chip should already be up and running, so we can start
                //      immediately ....
                o_wb_ack <= 1'b0;
                o_wb_stall <= 1'b1;
                spi_wr   <= 1'b0;
                spi_hold <= 1'b0;
                spi_spd  <= 1'b0;
                spi_dir  <= 1'b0;
                last_status <= 8'h00;
                state <= `WBQSPI_RESET_QUADMODE;
                spif_req <= 1'b0;
                spif_override <= 1'b1;
                last_status <= 8'hfc; //
                        // This guarantees that we aren't starting in quad
                        // I/O mode, where the FPGA configuration scripts may
                        // have left us.
        end else if (state == `WBQSPI_RESET_QUADMODE)
        begin
                // Okay, so here's the problem: we don't know whether or not
                // the Xilinx loader started us up in Quad Read I/O idle mode.
                // So, thus we need to 
                // Not ready to handle the bus yet, so stall any requests
                o_wb_ack   <= 1'b0;
                o_wb_stall <= 1'b1;
 
                // Do something ...
                if (last_status == 8'h00)
                begin
                        spif_override <= 1'b0;
                        state <= `WBQSPI_IDLE;
                end else begin
                        last_status <= last_status - 8'h1;
                        spif_override <= 1'b1;
                        spif_cmd  <= last_status[3]; // Toggle CS_n
                        spif_ctrl <= last_status[0]; // Toggle clock too
                end
        end else if (state == `WBQSPI_IDLE)
        begin
                o_interrupt <= 1'b0;
                o_wb_stall <= 1'b0;
                o_wb_ack <= 1'b0;
                spif_cmd   <= i_wb_we;
                spif_addr  <= i_wb_addr;
                spif_data  <= i_wb_data;
                spif_ctrl  <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
                spif_req   <= (i_wb_ctrl_stb)||(i_wb_data_stb);
                spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
                spi_hold <= 1'b0;
                spi_spd  <= 1'b0;
                spi_dir <= 1'b0; // Write (for now, 'cause of cmd)
                // Data register access
                if ((i_wb_data_stb)&&(i_wb_cyc))
                begin
 
                        if (i_wb_we) // Request to write a page
                        begin
`ifdef  READ_ONLY
                                o_wb_ack <= 1'b1;
                                o_wb_stall <= 1'b0;
                        end else
`else
                                if((~write_protect)&&(~write_in_progress))
                                begin // 00
                                        spi_wr <= 1'b1;
                                        spi_len <= 2'b00; // 8 bits
                                        // Send a write enable command
                                        spi_in <= { 8'h06, 24'h00 };
                                        state <= `WBQSPI_WEN;
 
                                        o_wb_ack <= 1'b0;
                                        o_wb_stall <= 1'b1;
                                end else if (write_protect)
                                begin // whether or not write-in_progress ...
                                        // Do nothing on a write protect
                                        // violation
                                        //
                                        o_wb_ack <= 1'b1;
                                        o_wb_stall <= 1'b0;
                                end else begin // write is in progress, wait
                                        // for it to complete
                                        state <= `WBQSPI_WAIT_WIP_CLEAR;
                                        o_wb_ack <= 1'b0;
                                        o_wb_stall <= 1'b1;
                                end
                        end else if (~write_in_progress)
`endif
                        begin // Read access, normal mode(s)
                                o_wb_ack   <= 1'b0;
                                o_wb_stall <= 1'b1;
                                spi_wr     <= 1'b1;     // Write cmd to device
                                if (quad_mode_enabled)
                                begin
                                        spi_in <= { 8'heb,
                                                {(24-ADDRESS_WIDTH){1'b0}},
                                                i_wb_addr[(ADDRESS_WIDTH-3):0], 2'b00 };
                                        state <= `WBQSPI_QRD_ADDRESS;
                                        spi_len    <= 2'b00; // single byte, cmd only
                                end else begin
                                        spi_in <= { 8'h0b,
                                                {(24-ADDRESS_WIDTH){1'b0}},
                                                i_wb_addr[(ADDRESS_WIDTH-3):0], 2'b00 };
                                        state <= `WBQSPI_RD_DUMMY;
                                        spi_len    <= 2'b11; // cmd+addr,32bits
                                end
`ifndef READ_ONLY
                        end else begin
                                // A write is in progress ... need to stall
                                // the bus until the write is complete.
                                state <= `WBQSPI_WAIT_WIP_CLEAR;
                                o_wb_ack   <= 1'b0;
                                o_wb_stall <= 1'b1;
`endif
                        end
                end else if ((i_wb_cyc)&&(i_wb_ctrl_stb)&&(i_wb_we))
                begin
`ifdef  READ_ONLY
                        o_wb_ack   <= 1'b1;
                        o_wb_stall <= 1'b0;
`else
                        o_wb_stall <= 1'b1;
                        case(i_wb_addr[1:0])
                        2'b00: begin // Erase command register
                                write_protect <= ~i_wb_data[28];
                                o_wb_stall <= 1'b0;
 
                                if((i_wb_data[31])&&(~write_in_progress))
                                begin
                                        // Command an erase--ack it immediately
 
                                        o_wb_ack <= 1'b1;
                                        o_wb_stall <= 1'b0;
 
                                        if ((i_wb_data[31])&&(~write_protect))
                                        begin
                                                spi_wr <= 1'b1;
                                                spi_len <= 2'b00;
                                                // Send a write enable command
                                                spi_in <= { 8'h06, 24'h00 };
                                                state <= `WBQSPI_ERASE_CMD;
                                                o_wb_stall <= 1'b1;
                                        end
                                end else if (i_wb_data[31])
                                begin
                                        state <= `WBQSPI_WAIT_WIP_CLEAR;
                                        o_wb_ack   <= 1'b1;
                                        o_wb_stall <= 1'b1;
                                end else
                                        o_wb_ack   <= 1'b1;
                                        o_wb_stall <= 1'b0;
                                end
                        2'b01: begin
                                // Write the configuration register
                                o_wb_ack <= 1'b1;
                                o_wb_stall <= 1'b1;
 
                                // Need to send a write enable command first
                                spi_wr <= 1'b1;
                                spi_len <= 2'b00; // 8 bits
                                // Send a write enable command
                                spi_in <= { 8'h06, 24'h00 };
                                state <= `WBQSPI_WRITE_CONFIG;
                                end
                        2'b10: begin
                                // Write the status register
                                o_wb_ack <= 1'b1; // Ack immediately
                                o_wb_stall <= 1'b1; // Stall other cmds
                                // Need to send a write enable command first
                                spi_wr <= 1'b1;
                                spi_len <= 2'b00; // 8 bits
                                // Send a write enable command
                                spi_in <= { 8'h06, 24'h00 };
                                state <= `WBQSPI_WRITE_STATUS;
                                end
                        2'b11: begin // Write the ID register??? makes no sense
                                o_wb_ack <= 1'b1;
                                o_wb_stall <= 1'b0;
                                end
                        endcase
`endif
                end else if ((i_wb_cyc)&&(i_wb_ctrl_stb)) // &&(~i_wb_we))
                begin
                        case(i_wb_addr[1:0])
                        2'b00: begin // Read local register
                                if (write_in_progress) // Read status
                                begin// register, is write still in progress?
                                        state <= `WBQSPI_READ_STATUS;
                                        spi_wr <= 1'b1;
                                        spi_len <= 2'b01;// 8 bits out, 8 bits in
                                        spi_in <= { 8'h05, 24'h00};
 
                                        o_wb_ack <= 1'b0;
                                        o_wb_stall <= 1'b1;
                                end else begin // Return w/o talking to device
                                        o_wb_ack <= 1'b1;
                                        o_wb_stall <= 1'b0;
                                        o_wb_data <= { write_in_progress,
                                                dirty_sector, spi_busy,
                                                ~write_protect,
                                                quad_mode_enabled,
                                                {(29-ADDRESS_WIDTH){1'b0}},
                                                erased_sector, 14'h000 };
                                end end
                        2'b01: begin // Read configuration register
                                state <= `WBQSPI_READ_CONFIG;
                                spi_wr <= 1'b1;
                                spi_len <= 2'b01;
                                spi_in <= { 8'h35, 24'h00};
 
                                o_wb_ack <= 1'b0;
                                o_wb_stall <= 1'b1;
                                end
                        2'b10: begin // Read status register
                                state <= `WBQSPI_READ_STATUS;
                                spi_wr <= 1'b1;
                                spi_len <= 2'b01; // 8 bits out, 8 bits in
                                spi_in <= { 8'h05, 24'h00};
 
                                o_wb_ack <= 1'b0;
                                o_wb_stall <= 1'b1;
                                end
                        2'b11: begin // Read ID register
                                state <= `WBQSPI_READ_ID_CMD;
                                spi_wr <= 1'b1;
                                spi_len <= 2'b00;
                                spi_in <= { 8'h9f, 24'h00};
 
                                o_wb_ack <= 1'b0;
                                o_wb_stall <= 1'b1;
                                end
                        endcase
`ifndef READ_ONLY
                end else if ((~i_wb_cyc)&&(write_in_progress))
                begin
                        state <= `WBQSPI_IDLE_CHECK_WIP;
                        spi_wr <= 1'b1;
                        spi_len <= 2'b01; // 8 bits out, 8 bits in
                        spi_in <= { 8'h05, 24'h00};
 
                        o_wb_ack <= 1'b0;
                        o_wb_stall <= 1'b1;
`endif
                end
        end else if (state == `WBQSPI_RDIDLE)
        begin
                spi_wr <= 1'b0;
                o_wb_stall <= 1'b0;
                o_wb_ack <= 1'b0;
                spif_cmd   <= i_wb_we;
                spif_addr  <= i_wb_addr;
                spif_data  <= i_wb_data;
                spif_ctrl  <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
                spif_req   <= (i_wb_ctrl_stb)||(i_wb_data_stb);
                spi_hold <= 1'b0;
                spi_spd<= 1'b1;
                spi_dir <= 1'b0; // Write (for now)
                if ((i_wb_cyc)&&(i_wb_data_stb)&&(~i_wb_we))
                begin // Continue our read ... send the new address / mode
                        o_wb_stall <= 1'b1;
                        spi_wr <= 1'b1;
                        spi_len <= 2'b10; // Write address, but not mode byte
                        spi_in <= { {(24-ADDRESS_WIDTH){1'b0}},
                                        i_wb_addr[(ADDRESS_WIDTH-3):0], 2'b00, 8'ha0 };
                        state <= `WBQSPI_QRD_DUMMY;
                end else if((i_wb_cyc)&&(i_wb_ctrl_stb)&&(~i_wb_we)&&(i_wb_addr[1:0] == 2'b00))
                begin
                        // A local read that doesn't touch the device, so leave
                        // the device in its current state
                        o_wb_stall <= 1'b0;
                        o_wb_ack <= 1'b1;
                        o_wb_data <= { write_in_progress,
                                        dirty_sector, spi_busy,
                                        ~write_protect,
                                        quad_mode_enabled,
                                        {(29-ADDRESS_WIDTH){1'b0}},
                                        erased_sector, 14'h000 };
                end else if((i_wb_cyc)&&((i_wb_ctrl_stb)||(i_wb_data_stb)))
                begin // Need to release the device from quad mode for all else
                        o_wb_ack   <= 1'b0;
                        o_wb_stall <= 1'b1;
                        spi_wr <= 1'b1;
                        spi_len <= 2'b11;
                        spi_in <= 32'h00;
                        state <= `WBQSPI_WBDECODE;
                end
        end else if (state == `WBQSPI_WBDECODE)
        begin
                // We were in quad SPI read mode, and had to get out.
                // Now we've got a command (not data read) to read and
                // execute.  Accomplish what we would've done while in the
                // IDLE state here, save only that we don't have to worry
                // about data reads, and we need to operate on a stored
                // version of the bus command
                o_wb_stall <= 1'b1;
                o_wb_ack <= 1'b0;
                spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
                spi_hold <= 1'b0;
                spi_spd <= 1'b0;
                spi_dir <= 1'b0;
                spif_req<= (spif_req) && (i_wb_cyc);
                if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // only in full idle ...
                begin
                        // Data register access
                        if (~spif_ctrl)
                        begin
                                if (spif_cmd) // Request to write a page
                                begin
`ifdef  READ_ONLY
                                        o_wb_ack <= spif_req;
                                        o_wb_stall <= 1'b0;
                                        state <= `WBQSPI_IDLE;
`else
                                        if((~write_protect)&&(~write_in_progress))
                                        begin // 00
                                                spi_wr <= 1'b1;
                                                spi_len <= 2'b00; // 8 bits
                                                // Send a write enable command
                                                spi_in <= { 8'h06, 24'h00 };
                                                state <= `WBQSPI_WEN;
 
                                                o_wb_ack <= 1'b0;
                                                o_wb_stall <= 1'b1;
                                        end else if (write_protect)
                                        begin // whether or not write-in_progress ...
                                                // Do nothing on a write protect
                                                // violation
                                                //
                                                o_wb_ack <= spif_req;
                                                o_wb_stall <= 1'b0;
                                                state <= `WBQSPI_IDLE;
                                        end else begin // write is in progress, wait
                                                // for it to complete
                                                state <= `WBQSPI_WAIT_WIP_CLEAR;
                                                o_wb_ack <= 1'b0;
                                                o_wb_stall <= 1'b1;
                                        end
                                // end else if (~write_in_progress) // always true
                                // but ... we wouldn't get here on a normal read access
`endif
                                end else begin
                                        // Something's wrong, we should never
                                        //   get here
                                        // Attempt to go to idle to recover
                                        state <= `WBQSPI_IDLE;
                                end
                        end else if ((spif_ctrl)&&(spif_cmd))
                        begin
`ifdef  READ_ONLY
                                o_wb_ack   <= spif_req;
                                o_wb_stall <= 1'b0;
                                state <= `WBQSPI_IDLE;
`else
                                o_wb_stall <= 1'b1;
                                case(spif_addr[1:0])
                                2'b00: begin // Erase command register
                                        o_wb_ack   <= spif_req;
                                        o_wb_stall <= 1'b0;
                                        state <= `WBQSPI_IDLE;
                                        write_protect <= ~spif_data[28];
                                        // Are we commanding an erase?
                                        // We're in read mode, writes cannot
                                        // be in progress, so ...
                                        if (spif_data[31]) // Command an erase
                                        begin
                                                // Since we're not going back
                                                // to IDLE, we must stall the
                                                // bus here
                                                o_wb_stall <= 1'b1;
                                                spi_wr <= 1'b1;
                                                spi_len <= 2'b00;
                                                // Send a write enable command
                                                spi_in <= { 8'h06, 24'h00 };
                                                state <= `WBQSPI_ERASE_CMD;
                                        end end
                                2'b01: begin
                                        // Write the configuration register
                                        o_wb_ack <= spif_req;
                                        o_wb_stall <= 1'b1;
 
                                        // Need to send a write enable command first
                                        spi_wr <= 1'b1;
                                        spi_len <= 2'b00; // 8 bits
                                        // Send a write enable command
                                        spi_in <= { 8'h06, 24'h00 };
                                        state <= `WBQSPI_WRITE_CONFIG;
                                        end
                                2'b10: begin
                                        // Write the status register
                                        o_wb_ack <= spif_req; // Ack immediately
                                        o_wb_stall <= 1'b1; // Stall other cmds
                                        // Need to send a write enable command first
                                        spi_wr <= 1'b1;
                                        spi_len <= 2'b00; // 8 bits
                                        // Send a write enable command
                                        spi_in <= { 8'h06, 24'h00 };
                                        state <= `WBQSPI_WRITE_STATUS;
                                        end
                                2'b11: begin // Write the ID register??? makes no sense
                                        o_wb_ack <= spif_req;
                                        o_wb_stall <= 1'b0;
                                        state <= `WBQSPI_IDLE;
                                        end
                                endcase
`endif
                        end else begin // on (~spif_we)
                                case(spif_addr[1:0])
                                2'b00: begin // Read local register
                                        // Nonsense case--would've done this
                                        // already
                                        state <= `WBQSPI_IDLE;
                                        o_wb_ack <= spif_req;
                                        o_wb_stall <= 1'b0;
                                        end
                                2'b01: begin // Read configuration register
                                        state <= `WBQSPI_READ_CONFIG;
                                        spi_wr <= 1'b1;
                                        spi_len <= 2'b01;
                                        spi_in <= { 8'h35, 24'h00};
 
                                        o_wb_ack <= 1'b0;
                                        o_wb_stall <= 1'b1;
                                        end
                                2'b10: begin // Read status register
                                        state <= `WBQSPI_READ_STATUS;
                                        spi_wr <= 1'b1;
                                        spi_len <= 2'b01; // 8 bits out, 8 bits in
                                        spi_in <= { 8'h05, 24'h00};
 
                                        o_wb_ack <= 1'b0;
                                        o_wb_stall <= 1'b1;
                                        end
                                2'b11: begin // Read ID register
                                        state <= `WBQSPI_READ_ID_CMD;
                                        spi_wr <= 1'b1;
                                        spi_len <= 2'b00;
                                        spi_in <= { 8'h9f, 24'h00};
 
                                        o_wb_ack <= 1'b0;
                                        o_wb_stall <= 1'b1;
                                        end
                                endcase
                        end
                end
//
//
//      READ DATA section: for both data and commands
//
        end else if (state == `WBQSPI_RD_DUMMY)
        begin
                o_wb_ack   <= 1'b0;
                o_wb_stall <= 1'b1;
 
                spi_wr <= 1'b1; // Non-stop
                // Need to read one byte of dummy data,
                // just to consume 8 clocks
                spi_in <= { 8'h00, 24'h00 };
                spi_len <= 2'b00; // Read 8 bits
                spi_spd <= 1'b0;
                spi_hold <= 1'b0;
                spif_req<= (spif_req) && (i_wb_cyc);
 
                if ((~spi_busy)&&(~o_qspi_cs_n))
                        // Our command was accepted
                        state <= `WBQSPI_READ_CMD;
        end else if (state == `WBQSPI_QRD_ADDRESS)
        begin
                // We come in here immediately upon issuing a QRD read
                // command (8-bits), but we have to pause to give the
                // address (24-bits) and mode (8-bits) in quad speed.
                o_wb_ack   <= 1'b0;
                o_wb_stall <= 1'b1;
 
                spi_wr <= 1'b1; // Non-stop
                spi_in <= { {(24-ADDRESS_WIDTH){1'b0}},
                                spif_addr[(ADDRESS_WIDTH-3):0], 2'b00, 8'ha0 };
                spi_len <= 2'b10; // Write address, not mode byte
                spi_spd <= 1'b1;
                spi_dir <= 1'b0; // Still writing
                spi_hold <= 1'b0;
                spif_req<= (spif_req) && (i_wb_cyc);
 
                if ((~spi_busy)&&(spi_spd))
                        // Our command was accepted
                        state <= `WBQSPI_QRD_DUMMY;
        end else if (state == `WBQSPI_QRD_DUMMY)
        begin
                o_wb_ack   <= 1'b0;
                o_wb_stall <= 1'b1;
 
                spi_wr <= 1'b1; // Non-stop
                spi_in <= { 8'ha0, 24'h00 }; // Mode byte, then 2 bytes dummy
                spi_len <= 2'b10; // Write 24 bits
                spi_spd <= 1'b1;
                spi_dir <= 1'b0; // Still writing
                spi_hold <= 1'b0;
                spif_req<= (spif_req) && (i_wb_cyc);
 
                if ((~spi_busy)&&(spi_in[31:28] == 4'ha))
                        // Our command was accepted
                        state <= `WBQSPI_READ_CMD;
        end else if (state == `WBQSPI_READ_CMD)
        begin // Issue our first command to read 32 bits.
                o_wb_ack   <= 1'b0;
                o_wb_stall <= 1'b1;
 
                spi_wr <= 1'b1;
                spi_in <= { 8'hff, 24'h00 }; // Empty
                spi_len <= 2'b11; // Read 32 bits
                spi_dir <= 1'b1; // Now reading
                spi_hold <= 1'b0;
                spif_req<= (spif_req) && (i_wb_cyc);
                if ((spi_valid)&&(spi_len == 2'b11))
                        state <= `WBQSPI_READ_DATA;
        end else if (state == `WBQSPI_READ_DATA)
        begin
                // Pipelined read support
                spi_wr <=((i_wb_cyc)&&(i_wb_data_stb)&&(~i_wb_we)&&(i_wb_addr== (spif_addr+1)));
                spi_in <= 32'h00;
                spi_len <= 2'b11;
                // Don't adjust the speed here, it was set in the setup
                spi_dir <= 1'b1;        // Now we get to read
                // Don't let the device go to idle until the bus cycle ends.
                //      This actually prevents a *really* nasty race condition,
                //      where the strobe comes in after the lower level device
                //      has decided to stop waiting.  The write is then issued,
                //      but no one is listening.  By leaving the device open,
                //      the device is kept in a state where a valid strobe
                //      here will be useful.  Of course, we don't accept
                //      all commands, just reads.  Further, the strobe needs
                //      to be high for two clocks cycles without changing
                //      anything on the bus--one for us to notice it and pull
                //      our head out of the sand, and a second for whoever
                //      owns the bus to realize their command went through.
                spi_hold <= 1'b1;
                spif_req<= (spif_req) && (i_wb_cyc);
                if ((spi_valid)&&(~spi_in[31]))
                begin // Single pulse acknowledge and write data out
                        o_wb_ack <= spif_req;
                        o_wb_stall <= (~spi_wr);
                        // adjust endian-ness to match the PC
                        o_wb_data <= { spi_out[7:0], spi_out[15:8],
                                spi_out[23:16], spi_out[31:24] };
                        state <= (spi_wr)?`WBQSPI_READ_DATA
                                : ((spi_spd) ? `WBQSPI_WAIT_TIL_RDIDLE : `WBQSPI_WAIT_TIL_IDLE);
                        spif_req <= spi_wr;
                        spi_hold <= (~spi_wr);
                        if (spi_wr)
                                spif_addr <= i_wb_addr;
                end else if (~i_wb_cyc)
                begin // FAIL SAFE: If the bus cycle ends, forget why we're
                        // here, just go back to idle
                        state <= ((spi_spd) ? `WBQSPI_WAIT_TIL_RDIDLE : `WBQSPI_WAIT_TIL_IDLE);
                        spi_hold <= 1'b0;
                        o_wb_ack <= 1'b0;
                        o_wb_stall <= 1'b1;
                end else begin
                        o_wb_ack <= 1'b0;
                        o_wb_stall <= 1'b1;
                end
        end else if (state == `WBQSPI_WAIT_TIL_RDIDLE)
        begin // Wait 'til idle, but then go to fast read idle instead of full
                spi_wr     <= 1'b0;     // idle
                spi_hold   <= 1'b0;
                o_wb_stall <= 1'b1;
                o_wb_ack   <= 1'b0;
                spif_req   <= 1'b0;
                if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // Wait for a full
                begin // clearing of the SPI port before moving on
                        state <= `WBQSPI_RDIDLE;
                        o_wb_stall <= 1'b0;
                        o_wb_ack   <= 1'b0;// Shouldn't be acking anything here
                end
        end else if (state == `WBQSPI_READ_ID_CMD)
        begin // We came into here immediately after issuing a 0x9f command
                // Now we need to read 32 bits of data.  Result should be
                // 0x0102154d (8'h manufacture ID, 16'h device ID, followed
                // by the number of extended bytes available 8'h4d).
                o_wb_ack <= 1'b0;
                o_wb_stall<= 1'b1;
 
                spi_wr <= 1'b1; // No data to send, but need four bytes, since
                spi_len <= 2'b11; // 32 bits of data are ... useful
                spi_in <= 32'h00; // Irrelevant
                spi_spd <= 1'b0; // Slow speed
                spi_dir <= 1'b1; // Reading
                spi_hold <= 1'b0;
                spif_req <= (spif_req) && (i_wb_cyc);
                if ((~spi_busy)&&(~o_qspi_cs_n)&&(spi_len == 2'b11))
                        // Our command was accepted, now go read the result
                        state <= `WBQSPI_READ_ID;
        end else if (state == `WBQSPI_READ_ID)
        begin
                o_wb_ack <= 1'b0; // Assuming we're still waiting
                o_wb_stall <= 1'b1;
 
                spi_wr <= 1'b0; // No more writes, we've already written the cmd
                spi_hold <= 1'b0;
                spif_req <= (spif_req) && (i_wb_cyc);
 
                // Here, we just wait until the result comes back
                // The problem is, the result may be the previous result.
                // So we use spi_len as an indicator
                spi_len <= 2'b00;
                if((spi_valid)&&(spi_len==2'b00))
                begin // Put the results out as soon as possible
                        o_wb_data <= spi_out[31:0];
                        o_wb_ack <= spif_req;
                        spif_req <= 1'b0;
                end else if ((~spi_busy)&&(o_qspi_cs_n))
                begin
                        state <= `WBQSPI_IDLE;
                        o_wb_stall <= 1'b0;
                end
        end else if (state == `WBQSPI_READ_STATUS)
        begin // We enter after the command has been given, for now just
                // read and return
                spi_wr <= 1'b0;
                o_wb_ack <= 1'b0;
                spi_hold <= 1'b0;
                spif_req <= (spif_req) && (i_wb_cyc);
                if (spi_valid)
                begin
                        o_wb_ack <= spif_req;
                        o_wb_stall <= 1'b1;
                        spif_req <= 1'b0;
                        last_status <= spi_out[7:0];
                        write_in_progress <= spi_out[0];
                        if (spif_addr[1:0] == 2'b00) // Local read, checking
                        begin // status, 'cause we're writing
                                o_wb_data <= { spi_out[0],
                                        dirty_sector, spi_busy,
                                        ~write_protect,
                                        quad_mode_enabled,
                                        {(29-ADDRESS_WIDTH){1'b0}},
                                        erased_sector, 14'h000 };
                        end else begin
                                o_wb_data <= { 24'h00, spi_out[7:0] };
                        end
                end
 
                if ((~spi_busy)&&(~spi_wr))
                        state <= `WBQSPI_IDLE;
        end else if (state == `WBQSPI_READ_CONFIG)
        begin // We enter after the command has been given, for now just
                // read and return
                spi_wr <= 1'b0;
                o_wb_ack <= 1'b0;
                o_wb_stall <= 1'b1;
                spi_hold <= 1'b0;
                spif_req <= (spif_req) && (i_wb_cyc);
 
                if (spi_valid)
                begin
                        o_wb_data <= { 24'h00, spi_out[7:0] };
                        quad_mode_enabled <= spi_out[1];
                end
 
                if ((~spi_busy)&&(~spi_wr))
                begin
                        state <= `WBQSPI_IDLE;
                        o_wb_ack   <= spif_req;
                        o_wb_stall <= 1'b0;
                        spif_req <= 1'b0;
                end
 
//
//
//      Write/erase data section
//
`ifndef READ_ONLY
        end else if (state == `WBQSPI_WAIT_WIP_CLEAR)
        begin
                o_wb_stall <= 1'b1;
                o_wb_ack   <= 1'b0;
                spi_wr <= 1'b0;
                spif_req<= (spif_req) && (i_wb_cyc);
                if (~spi_busy)
                begin
                        spi_wr   <= 1'b1;
                        spi_in   <= { 8'h05, 24'h0000 };
                        spi_hold <= 1'b1;
                        spi_len  <= 2'b01; // 16 bits write, so we can read 8
                        state <= `WBQSPI_CHECK_WIP_CLEAR;
                        spi_spd  <= 1'b0; // Slow speed
                        spi_dir  <= 1'b0;
                end
        end else if (state == `WBQSPI_CHECK_WIP_CLEAR)
        begin
                o_wb_stall <= 1'b1;
                o_wb_ack   <= 1'b0;
                // Repeat as often as necessary until we are clear
                spi_wr <= 1'b1;
                spi_in <= 32'h0000; // Values here are actually irrelevant
                spi_hold <= 1'b1;
                spi_len <= 2'b00; // One byte at a time
                spi_spd  <= 1'b0; // Slow speed
                spi_dir  <= 1'b0;
                spif_req<= (spif_req) && (i_wb_cyc);
                if ((spi_valid)&&(~spi_out[0]))
                begin
                        state <= `WBQSPI_CHECK_WIP_DONE;
                        spi_wr   <= 1'b0;
                        spi_hold <= 1'b0;
                        write_in_progress <= 1'b0;
                        last_status <= spi_out[7:0];
                end
        end else if (state == `WBQSPI_CHECK_WIP_DONE)
        begin
                o_wb_stall <= 1'b1;
                o_wb_ack   <= 1'b0;
                // Let's let the SPI port come back to a full idle,
                // and the chip select line go low before continuing
                spi_wr   <= 1'b0;
                spi_len  <= 2'b00;
                spi_hold <= 1'b0;
                spi_spd  <= 1'b0; // Slow speed
                spi_dir  <= 1'b0;
                spif_req<= (spif_req) && (i_wb_cyc);
                if ((o_qspi_cs_n)&&(~spi_busy)) // Chip select line is high, we can continue
                begin
                        spi_wr   <= 1'b0;
                        spi_hold <= 1'b0;
 
                        casez({ spif_cmd, spif_ctrl, spif_addr[1:0] })
                        4'b00??: begin // Read data from ... somewhere
                                spi_wr     <= 1'b1;     // Write cmd to device
                                if (quad_mode_enabled)
                                begin
                                        spi_in <= { 8'heb,
                                                {(24-ADDRESS_WIDTH){1'b0}},
                                                spif_addr[(ADDRESS_WIDTH-3):0], 2'b00 };
                                        state <= `WBQSPI_QRD_ADDRESS;
                                        // spi_len    <= 2'b00; // single byte, cmd only
                                end else begin
                                        spi_in <= { 8'h0b,
                                                {(24-ADDRESS_WIDTH){1'b0}},
                                                spif_addr[(ADDRESS_WIDTH-3):0], 2'b00 };
                                        state <= `WBQSPI_RD_DUMMY;
                                        spi_len    <= 2'b11; // Send cmd and addr
                                end end
                        4'b10??: begin // Write data to ... anywhere
                                spi_wr <= 1'b1;
                                spi_len <= 2'b00; // 8 bits
                                // Send a write enable command
                                spi_in <= { 8'h06, 24'h00 };
                                state <= `WBQSPI_WEN;
                                end
                        4'b0110: begin // Read status register
                                state <= `WBQSPI_READ_STATUS;
                                spi_wr <= 1'b1;
                                spi_len <= 2'b01; // 8 bits out, 8 bits in
                                spi_in <= { 8'h05, 24'h00};
                                end
                        4'b0111: begin
                                state <= `WBQSPI_READ_ID_CMD;
                                spi_wr <= 1'b1;
                                spi_len <= 2'b00;
                                spi_in <= { 8'h9f, 24'h00};
                                end
                        default: begin //
                                o_wb_stall <= 1'b1;
                                o_wb_ack <= spif_req;
                                state <= `WBQSPI_WAIT_TIL_IDLE;
                                end
                        endcase
                // spif_cmd   <= i_wb_we;
                // spif_addr  <= i_wb_addr;
                // spif_data  <= i_wb_data;
                // spif_ctrl  <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
                // spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
                end
        end else if (state == `WBQSPI_WEN)
        begin // We came here after issuing a write enable command
                spi_wr <= 1'b0;
                o_wb_ack <= 1'b0;
                o_wb_stall <= 1'b1;
                spif_req<= (spif_req) && (i_wb_cyc);
                if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // Let's come to a full stop
                        state <= (quad_mode_enabled)?`WBQSPI_QPP:`WBQSPI_PP;
                        // state <= `WBQSPI_PP;
        end else if (state == `WBQSPI_PP)
        begin // We come here under a full stop / full port idle mode
                // Issue our command immediately
                spi_wr <= 1'b1;
                spi_in <= { 8'h02,
                                {(24-ADDRESS_WIDTH){1'b0}},
                                spif_addr[(ADDRESS_WIDTH-3):0], 2'b00 };
                spi_len <= 2'b11;
                spi_hold <= 1'b1;
                spi_spd  <= 1'b0;
                spi_dir  <= 1'b0; // Writing
                spif_req<= (spif_req) && (i_wb_cyc);
 
                // Once we get busy, move on
                if (spi_busy)
                        state <= `WBQSPI_WR_DATA;
                if (spif_sector == erased_sector)
                        dirty_sector <= 1'b1;
        end else if (state == `WBQSPI_QPP)
        begin // We come here under a full stop / full port idle mode
                // Issue our command immediately
                spi_wr <= 1'b1;
                spi_in <= { 8'h32,
                                {(24-ADDRESS_WIDTH){1'b0}},
                                spif_addr[(ADDRESS_WIDTH-3):0], 2'b00 };
                spi_len <= 2'b11;
                spi_hold <= 1'b1;
                spi_spd  <= 1'b0;
                spi_dir  <= 1'b0; // Writing
                spif_req<= (spif_req) && (i_wb_cyc);
 
                // Once we get busy, move on
                if (spi_busy)
                begin
                        // spi_wr is irrelevant here ...
                        // Set the speed value once, but wait til we get busy
                        // to do so.
                        spi_spd <= 1'b1;
                        state <= `WBQSPI_WR_DATA;
                end
                if (spif_sector == erased_sector)
                        dirty_sector <= 1'b1;
        end else if (state == `WBQSPI_WR_DATA)
        begin
                o_wb_stall <= 1'b1;
                o_wb_ack   <= 1'b0;
                spi_wr   <= 1'b1; // write without waiting
                spi_in   <= {
                        spif_data[ 7: 0],
                        spif_data[15: 8],
                        spif_data[23:16],
                        spif_data[31:24] };
                spi_len  <= 2'b11; // Write 4 bytes
                spi_hold <= 1'b1;
                if (~spi_busy)
                begin
                        o_wb_ack <= spif_req; // Ack when command given
                        state <= `WBQSPI_WR_BUS_CYCLE;
                end
                spif_req<= (spif_req) && (i_wb_cyc);
        end else if (state == `WBQSPI_WR_BUS_CYCLE)
        begin
                o_wb_ack <= 1'b0; // Turn off our ack and stall flags
                o_wb_stall <= 1'b1;
                spi_wr <= 1'b0;
                spi_hold <= 1'b1;
                write_in_progress <= 1'b1;
                spif_req<= (spif_req) && (i_wb_cyc);
                if (~i_wb_cyc)
                begin
                        state <= `WBQSPI_WAIT_TIL_IDLE;
                        spi_hold <= 1'b0;
                end else if (spi_wr)
                begin // Give the SPI a chance to get busy on the last write
                        // Do nothing here.
                end else if ((i_wb_data_stb)&&(i_wb_we)
                                &&(i_wb_addr == (spif_addr+1))
                                &&(i_wb_addr[(ADDRESS_WIDTH-3):6]==spif_addr[(ADDRESS_WIDTH-3):6]))
                begin
                        spif_cmd  <= 1'b1;
                        spif_data <= i_wb_data;
                        spif_addr <= i_wb_addr;
                        spif_ctrl  <= 1'b0;
                        spif_req<= 1'b1;
                        // We'll keep the bus stalled on this request
                        // for a while
                        state <= `WBQSPI_WR_DATA;
                        o_wb_ack   <= 1'b0;
                        o_wb_stall <= 1'b0;
                end else if ((i_wb_data_stb|i_wb_ctrl_stb)&&(~o_wb_ack)) // Writing out of bounds
                begin
                        spi_hold <= 1'b0;
                        spi_wr   <= 1'b0;
                        state <= `WBQSPI_WAIT_TIL_IDLE;
                end // Otherwise we stay here
        end else if (state == `WBQSPI_WRITE_CONFIG)
        begin // We enter immediately after commanding a WEN
                o_wb_ack   <= 1'b0;
                o_wb_stall <= 1'b1;
 
                spi_len <= 2'b10;
                spi_in <= { 8'h01, last_status, spif_data[7:0], 8'h00 };
                spi_wr <= 1'b0;
                spi_hold <= 1'b0;
                spif_req <= (spif_req) && (i_wb_cyc);
                if ((~spi_busy)&&(~spi_wr))
                begin
                        spi_wr <= 1'b1;
                        state <= `WBQSPI_WAIT_TIL_IDLE;
                        write_in_progress <= 1'b1;
                        quad_mode_enabled <= spif_data[1];
                end
        end else if (state == `WBQSPI_WRITE_STATUS)
        begin // We enter immediately after commanding a WEN
                o_wb_ack   <= 1'b0;
                o_wb_stall <= 1'b1;
 
                spi_len <= 2'b01;
                spi_in <= { 8'h01, spif_data[7:0], 16'h00 };
                // last_status <= i_wb_data[7:0]; // We'll read this in a moment
                spi_wr <= 1'b0;
                spi_hold <= 1'b0;
                spif_req <= (spif_req) && (i_wb_cyc);
                if ((~spi_busy)&&(~spi_wr))
                begin
                        spi_wr <= 1'b1;
                        last_status <= spif_data[7:0];
                        write_in_progress <= 1'b1;
                        if(((last_status[6])||(last_status[5]))
                                &&((~spif_data[6])&&(~spif_data[5])))
                                state <= `WBQSPI_CLEAR_STATUS;
                        else
                                state <= `WBQSPI_WAIT_TIL_IDLE;
                end
        end else if (state == `WBQSPI_ERASE_CMD)
        begin // Know that WIP is clear on entry, WEN has just been commanded
                spi_wr     <= 1'b0;
                o_wb_ack   <= 1'b0;
                o_wb_stall <= 1'b1;
                spi_hold   <= 1'b0;
                spi_spd <= 1'b0;
                spi_dir <= 1'b0;
                spif_req <= (spif_req) && (i_wb_cyc);
 
                // Here's the erase command
                spi_in <= { 8'hd8, 2'h0, spif_data[19:14], 14'h000, 2'b00 };
                spi_len <= 2'b11; // 32 bit write
                // together with setting our copy of the WIP bit
                write_in_progress <= 1'b1;
                // keeping track of which sector we just erased
                erased_sector <= spif_data[(ADDRESS_WIDTH-3):14];
                // and marking this erase sector as no longer dirty
                dirty_sector <= 1'b0;
 
                // Wait for a full stop before issuing this command
                if ((~spi_busy)&&(~spi_wr)&&(o_qspi_cs_n))
                begin // When our command is accepted, move to the next state
                        spi_wr <= 1'b1;
                        state <= `WBQSPI_ERASE_BLOCK;
                end
        end else if (state == `WBQSPI_ERASE_BLOCK)
        begin
                spi_wr     <= 1'b0;
                spi_hold   <= 1'b0;
                o_wb_stall <= 1'b1;
                o_wb_ack   <= 1'b0;
                spif_req <= (spif_req) && (i_wb_cyc);
                // When the port clears, we can head back to idle
                if ((~spi_busy)&&(~spi_wr))
                begin
                        o_wb_ack <= spif_req;
                        state <= `WBQSPI_IDLE;
                end
        end else if (state == `WBQSPI_CLEAR_STATUS)
        begin // Issue a clear status command
                spi_wr <= 1'b1;
                spi_hold <= 1'b0;
                spi_len <= 2'b00; // 8 bit command
                spi_in <= { 8'h30, 24'h00 };
                spi_spd <= 1'b0;
                spi_dir <= 1'b0;
                last_status[6:5] <= 2'b00;
                spif_req <= (spif_req) && (i_wb_cyc);
                if ((spi_wr)&&(~spi_busy))
                        state <= `WBQSPI_WAIT_TIL_IDLE;
        end else if (state == `WBQSPI_IDLE_CHECK_WIP)
        begin // We are now in read status register mode
 
                // No bus commands have (yet) been given
                o_wb_stall <= 1'b1;
                o_wb_ack   <= 1'b0;
                spif_req <= (spif_req) && (i_wb_cyc);
 
                // Stay in this mode unless/until we get a command, or
                //      the write is over
                spi_wr <= (((~i_wb_cyc)||((~i_wb_data_stb)&&(~i_wb_ctrl_stb)))
                                &&(write_in_progress));
                spi_len <= 2'b00; // 8 bit reads
                spi_spd <= 1'b0;  // SPI, not quad
                spi_dir <= 1'b1;  // Read
                if (spi_valid)
                begin
                        write_in_progress <= spi_out[0];
                        if ((~spi_out[0])&&(write_in_progress))
                                o_interrupt <= 1'b1;
                end else
                        o_interrupt <= 1'b0;
 
                if ((~spi_wr)&&(~spi_busy)&&(o_qspi_cs_n))
                begin // We can now go to idle and process a command
                        o_wb_stall <= 1'b0;
                        o_wb_ack   <= 1'b0;
                        state <= `WBQSPI_IDLE;
                end
`endif //       !READ_ONLY
        end else // if (state == `WBQSPI_WAIT_TIL_IDLE) or anything else
        begin
                spi_wr     <= 1'b0;
                spi_hold   <= 1'b0;
                o_wb_stall <= 1'b1;
                o_wb_ack   <= 1'b0;
                spif_req   <= 1'b0;
                if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // Wait for a full
                begin // clearing of the SPI port before moving on
                        state <= `WBQSPI_IDLE;
                        o_wb_stall <= 1'b0;
                        o_wb_ack   <= 1'b0; // Shouldn't be acking anything here
                end
        end
        end
 
        // Command and control during the reset sequence
        assign  o_qspi_cs_n = (spif_override)?spif_cmd :w_qspi_cs_n;
        assign  o_qspi_sck  = (spif_override)?spif_ctrl:w_qspi_sck;
        assign  o_qspi_mod  = (spif_override)?   2'b01 :w_qspi_mod;
        assign  o_qspi_dat  = (spif_override)?   4'b00 :w_qspi_dat;
endmodule

Line No.	Rev	Author	Line
1	3	dgisselq	`///////////////////////////////////////////////////////////////////////////`
2	2	dgisselq	`//`
3			`// Filename: wbspiflash.v`
4			`//`
5	3	dgisselq	`// Project: Wishbone Controlled Quad SPI Flash Controller`
6	2	dgisselq	`//`
7			`// Purpose: Access a Quad SPI flash via a WISHBONE interface. This`
8			`// includes both read and write (and erase) commands to the SPI`
9			`// flash. All read/write commands are accomplished using the`
10			`// high speed (4-bit) interface. Further, the device will be`
11			`// left/kept in the 4-bit read interface mode between accesses,`
12			`// for a minimum read latency.`
13			`//`
14	3	dgisselq	`// Wishbone Registers (See spec sheet for more detail):`
15	2	dgisselq	`// 0: local config(r) / erase commands(w) / deep power down cmds / etc.`
16			`// R: (Write in Progress), (dirty-block), (spi_port_busy), 1'b0, 9'h00,`
17			`// { last_erased_sector, 14'h00 } if (WIP)`
18			`// else { current_sector_being_erased, 14'h00 }`
19			`// current if write in progress, last if written`
20			`// W: (1'b1 to erase), (12'h ignored), next_erased_block, 14'h ignored)`
21	3	dgisselq	`// 1: Configuration register`
22			`// 2: Status register (R/w)`
23			`// 3: Read ID (read only)`
24	2	dgisselq	`// (19 bits): Data (R/w, but expect writes to take a while)`
25			`//`
26			`//`
27			`// Creator: Dan Gisselquist`
28	8	dgisselq	`// Gisselquist Technology, LLC`
29	2	dgisselq	`//`
30	3	dgisselq	`///////////////////////////////////////////////////////////////////////////`
31	2	dgisselq	`//`
32	3	dgisselq	`// Copyright (C) 2015, Gisselquist Technology, LLC`
33	2	dgisselq	`//`
34	3	dgisselq	`// This program is free software (firmware): you can redistribute it and/or`
35			`// modify it under the terms of the GNU General Public License as published`
36			`// by the Free Software Foundation, either version 3 of the License, or (at`
37			`// your option) any later version.`
38			`//`
39			`// This program is distributed in the hope that it will be useful, but WITHOUT`
40			`// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or`
41			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
42			`// for more details.`
43			`//`
44			`// You should have received a copy of the GNU General Public License along`
45			`// with this program. (It's in the $(ROOT)/doc directory, run make with no`
46			`// target there if the PDF file isn't present.) If not, see`
47			`// <http://www.gnu.org/licenses/> for a copy.`
48			`//`
49			`// License: GPL, v3, as defined and found on www.gnu.org,`
50			`// http://www.gnu.org/licenses/gpl.html`
51			`//`
52			`//`
53			`///////////////////////////////////////////////////////////////////////////`
54	7	dgisselq	`//`
55			`include "flash_config.v"
56			`//`
57	2	dgisselq	`define WBQSPI_RESET 0
58	4	dgisselq	`define WBQSPI_RESET_QUADMODE 1
59	2	dgisselq	`define WBQSPI_IDLE 2
60			`define WBQSPI_RDIDLE 3 // Idle, but in fast read mode
61			`define WBQSPI_WBDECODE 4
62	7	dgisselq	`define WBQSPI_RD_DUMMY 5
63			`define WBQSPI_QRD_ADDRESS 6
64			`define WBQSPI_QRD_DUMMY 7
65			`define WBQSPI_READ_CMD 8
66			`define WBQSPI_READ_DATA 9
67			`define WBQSPI_WAIT_TIL_RDIDLE 10
68			`define WBQSPI_READ_ID_CMD 11
69			`define WBQSPI_READ_ID 12
70			`define WBQSPI_READ_STATUS 13
71			`define WBQSPI_READ_CONFIG 14
72			`define WBQSPI_WAIT_TIL_IDLE 15
73			`//`
74			`//`
75			`ifndef READ_ONLY
76			`//`
77			`define WBQSPI_WAIT_WIP_CLEAR 16
78			`define WBQSPI_CHECK_WIP_CLEAR 17
79			`define WBQSPI_CHECK_WIP_DONE 18
80			`define WBQSPI_WEN 19
81			`define WBQSPI_PP 20 // Program page
82			`define WBQSPI_QPP 21 // Program page, 4 bit mode
83			`define WBQSPI_WR_DATA 22
84			`define WBQSPI_WR_BUS_CYCLE 23
85			`define WBQSPI_WRITE_STATUS 24
86			`define WBQSPI_WRITE_CONFIG 25
87			`define WBQSPI_ERASE_WEN 26
88			`define WBQSPI_ERASE_CMD 27
89			`define WBQSPI_ERASE_BLOCK 28
90			`define WBQSPI_CLEAR_STATUS 29
91			`define WBQSPI_IDLE_CHECK_WIP 30
92			`//`
93			`endif
94	2	dgisselq
95			`module wbqspiflash(i_clk_100mhz,`
96			`// Internal wishbone connections`
97			`i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we,`
98			`i_wb_addr, i_wb_data,`
99			`// Wishbone return values`
100			`o_wb_ack, o_wb_stall, o_wb_data,`
101			`// Quad Spi connections to the external device`
102			`o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,`
103	3	dgisselq	`o_interrupt);`
104	7	dgisselq	`parameter ADDRESS_WIDTH=22;`
105	2	dgisselq	`input i_clk_100mhz;`
106			`// Wishbone, inputs first`
107			`input i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we;`
108	7	dgisselq	`input [(ADDRESS_WIDTH-3):0] i_wb_addr;`
109	2	dgisselq	`input [31:0] i_wb_data;`
110			`// then outputs`
111			`output reg o_wb_ack;`
112			`output reg o_wb_stall;`
113			`output reg [31:0] o_wb_data;`
114			`// Quad SPI control wires`
115			`output wire o_qspi_sck, o_qspi_cs_n;`
116			`output wire [1:0] o_qspi_mod;`
117			`output wire [3:0] o_qspi_dat;`
118			`input [3:0] i_qspi_dat;`
119			`// Interrupt line`
120			`output reg o_interrupt;`
121	7	dgisselq	`// output wire [31:0] o_debug;`
122	2	dgisselq
123			`reg spi_wr, spi_hold, spi_spd, spi_dir;`
124			`reg [31:0] spi_in;`
125			`reg [1:0] spi_len;`
126			`wire [31:0] spi_out;`
127			`wire spi_valid, spi_busy;`
128	4	dgisselq	`wire w_qspi_sck, w_qspi_cs_n;`
129			`wire [3:0] w_qspi_dat;`
130			`wire [1:0] w_qspi_mod;`
131	7	dgisselq	`// wire [22:0] spi_dbg;`
132	2	dgisselq	`llqspi lldriver(i_clk_100mhz,`
133			`spi_wr, spi_hold, spi_in, spi_len, spi_spd, spi_dir,`
134			`spi_out, spi_valid, spi_busy,`
135	4	dgisselq	`w_qspi_sck, w_qspi_cs_n, w_qspi_mod, w_qspi_dat,`
136	3	dgisselq	`i_qspi_dat);`
137	2	dgisselq
138			`// Erase status tracking`
139			`reg write_in_progress, write_protect;`
140	7	dgisselq	`reg [(ADDRESS_WIDTH-17):0] erased_sector;`
141	2	dgisselq	`reg dirty_sector;`
142			`initial begin`
143			`write_in_progress = 1'b0;`
144	7	dgisselq	`erased_sector = 0;`
145	2	dgisselq	`dirty_sector = 1'b1;`
146			`write_protect = 1'b1;`
147			`end`
148
149			`reg [7:0] last_status;`
150			`reg quad_mode_enabled;`
151	4	dgisselq	`reg spif_cmd, spif_override;`
152	7	dgisselq	`reg [(ADDRESS_WIDTH-3):0] spif_addr;`
153	2	dgisselq	`reg [31:0] spif_data;`
154			`reg [5:0] state;`
155			`reg spif_ctrl, spif_req;`
156	7	dgisselq	`wire [(ADDRESS_WIDTH-17):0] spif_sector;`
157			`assign spif_sector = spif_addr[(ADDRESS_WIDTH-3):14];`
158	2	dgisselq
159	7	dgisselq	`// assign o_debug = { spi_wr, spi_spd, spi_hold, state, spi_dbg };`
160
161	2	dgisselq	initial state = `WBQSPI_RESET;
162			`initial o_wb_ack = 1'b0;`
163			`initial o_wb_stall = 1'b1;`
164			`initial spi_wr = 1'b0;`
165			`initial spi_len = 2'b00;`
166			`initial quad_mode_enabled = 1'b0;`
167			`initial o_interrupt = 1'b0;`
168			`always @(posedge i_clk_100mhz)`
169	4	dgisselq	`begin`
170			`spif_override <= 1'b0;`
171	2	dgisselq	if (state == `WBQSPI_RESET)
172			`begin`
173			`// From a reset, we should`
174			`// Enable the Quad I/O mode`
175			`// Disable the Write protection bits in the status register`
176			`// Chip should already be up and running, so we can start`
177			`// immediately ....`
178			`o_wb_ack <= 1'b0;`
179			`o_wb_stall <= 1'b1;`
180	4	dgisselq	`spi_wr <= 1'b0;`
181	2	dgisselq	`spi_hold <= 1'b0;`
182			`spi_spd <= 1'b0;`
183			`spi_dir <= 1'b0;`
184			`last_status <= 8'h00;`
185	4	dgisselq	state <= `WBQSPI_RESET_QUADMODE;
186	2	dgisselq	`spif_req <= 1'b0;`
187	4	dgisselq	`spif_override <= 1'b1;`
188			`last_status <= 8'hfc; //`
189			`// This guarantees that we aren't starting in quad`
190			`// I/O mode, where the FPGA configuration scripts may`
191			`// have left us.`
192			end else if (state == `WBQSPI_RESET_QUADMODE)
193	2	dgisselq	`begin`
194	4	dgisselq	`// Okay, so here's the problem: we don't know whether or not`
195			`// the Xilinx loader started us up in Quad Read I/O idle mode.`
196			`// So, thus we need to`
197			`// Not ready to handle the bus yet, so stall any requests`
198			`o_wb_ack <= 1'b0;`
199			`o_wb_stall <= 1'b1;`
200
201			`// Do something ...`
202			`if (last_status == 8'h00)`
203	2	dgisselq	`begin`
204	4	dgisselq	`spif_override <= 1'b0;`
205			state <= `WBQSPI_IDLE;
206			`end else begin`
207			`last_status <= last_status - 8'h1;`
208			`spif_override <= 1'b1;`
209			`spif_cmd <= last_status[3]; // Toggle CS_n`
210			`spif_ctrl <= last_status[0]; // Toggle clock too`
211	2	dgisselq	`end`
212			end else if (state == `WBQSPI_IDLE)
213			`begin`
214			`o_interrupt <= 1'b0;`
215			`o_wb_stall <= 1'b0;`
216			`o_wb_ack <= 1'b0;`
217			`spif_cmd <= i_wb_we;`
218			`spif_addr <= i_wb_addr;`
219			`spif_data <= i_wb_data;`
220			`spif_ctrl <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);`
221			`spif_req <= (i_wb_ctrl_stb)\|\|(i_wb_data_stb);`
222			`spi_wr <= 1'b0; // Keep the port idle, unless told otherwise`
223			`spi_hold <= 1'b0;`
224			`spi_spd <= 1'b0;`
225			`spi_dir <= 1'b0; // Write (for now, 'cause of cmd)`
226			`// Data register access`
227			`if ((i_wb_data_stb)&&(i_wb_cyc))`
228			`begin`
229
230			`if (i_wb_we) // Request to write a page`
231			`begin`
232	7	dgisselq	`ifdef READ_ONLY
233			`o_wb_ack <= 1'b1;`
234			`o_wb_stall <= 1'b0;`
235			`end else`
236			`else
237	2	dgisselq	`if((~write_protect)&&(~write_in_progress))`
238			`begin // 00`
239			`spi_wr <= 1'b1;`
240			`spi_len <= 2'b00; // 8 bits`
241			`// Send a write enable command`
242			`spi_in <= { 8'h06, 24'h00 };`
243			state <= `WBQSPI_WEN;
244
245			`o_wb_ack <= 1'b0;`
246			`o_wb_stall <= 1'b1;`
247			`end else if (write_protect)`
248			`begin // whether or not write-in_progress ...`
249			`// Do nothing on a write protect`
250			`// violation`
251			`//`
252			`o_wb_ack <= 1'b1;`
253			`o_wb_stall <= 1'b0;`
254			`end else begin // write is in progress, wait`
255			`// for it to complete`
256			state <= `WBQSPI_WAIT_WIP_CLEAR;
257			`o_wb_ack <= 1'b0;`
258			`o_wb_stall <= 1'b1;`
259			`end`
260			`end else if (~write_in_progress)`
261	7	dgisselq	`endif
262	2	dgisselq	`begin // Read access, normal mode(s)`
263			`o_wb_ack <= 1'b0;`
264			`o_wb_stall <= 1'b1;`
265			`spi_wr <= 1'b1; // Write cmd to device`
266			`if (quad_mode_enabled)`
267			`begin`
268	7	dgisselq	`spi_in <= { 8'heb,`
269			`{(24-ADDRESS_WIDTH){1'b0}},`
270			`i_wb_addr[(ADDRESS_WIDTH-3):0], 2'b00 };`
271	2	dgisselq	state <= `WBQSPI_QRD_ADDRESS;
272			`spi_len <= 2'b00; // single byte, cmd only`
273			`end else begin`
274	7	dgisselq	`spi_in <= { 8'h0b,`
275			`{(24-ADDRESS_WIDTH){1'b0}},`
276			`i_wb_addr[(ADDRESS_WIDTH-3):0], 2'b00 };`
277	2	dgisselq	state <= `WBQSPI_RD_DUMMY;
278			`spi_len <= 2'b11; // cmd+addr,32bits`
279			`end`
280	7	dgisselq	`ifndef READ_ONLY
281	2	dgisselq	`end else begin`
282			`// A write is in progress ... need to stall`
283			`// the bus until the write is complete.`
284			state <= `WBQSPI_WAIT_WIP_CLEAR;
285			`o_wb_ack <= 1'b0;`
286			`o_wb_stall <= 1'b1;`
287	7	dgisselq	`endif
288	2	dgisselq	`end`
289			`end else if ((i_wb_cyc)&&(i_wb_ctrl_stb)&&(i_wb_we))`
290			`begin`
291	7	dgisselq	`ifdef READ_ONLY
292			`o_wb_ack <= 1'b1;`
293			`o_wb_stall <= 1'b0;`
294			`else
295	2	dgisselq	`o_wb_stall <= 1'b1;`
296			`case(i_wb_addr[1:0])`
297			`2'b00: begin // Erase command register`
298			`write_protect <= ~i_wb_data[28];`
299			`o_wb_stall <= 1'b0;`
300
301			`if((i_wb_data[31])&&(~write_in_progress))`
302			`begin`
303			`// Command an erase--ack it immediately`
304
305			`o_wb_ack <= 1'b1;`
306			`o_wb_stall <= 1'b0;`
307
308			`if ((i_wb_data[31])&&(~write_protect))`
309			`begin`
310			`spi_wr <= 1'b1;`
311			`spi_len <= 2'b00;`
312			`// Send a write enable command`
313			`spi_in <= { 8'h06, 24'h00 };`
314			state <= `WBQSPI_ERASE_CMD;
315			`o_wb_stall <= 1'b1;`
316			`end`
317			`end else if (i_wb_data[31])`
318			`begin`
319			state <= `WBQSPI_WAIT_WIP_CLEAR;
320			`o_wb_ack <= 1'b1;`
321			`o_wb_stall <= 1'b1;`
322			`end else`
323			`o_wb_ack <= 1'b1;`
324			`o_wb_stall <= 1'b0;`
325			`end`
326			`2'b01: begin`
327			`// Write the configuration register`
328			`o_wb_ack <= 1'b1;`
329			`o_wb_stall <= 1'b1;`
330
331			`// Need to send a write enable command first`
332			`spi_wr <= 1'b1;`
333			`spi_len <= 2'b00; // 8 bits`
334			`// Send a write enable command`
335			`spi_in <= { 8'h06, 24'h00 };`
336			state <= `WBQSPI_WRITE_CONFIG;
337			`end`
338			`2'b10: begin`
339			`// Write the status register`
340			`o_wb_ack <= 1'b1; // Ack immediately`
341			`o_wb_stall <= 1'b1; // Stall other cmds`
342			`// Need to send a write enable command first`
343			`spi_wr <= 1'b1;`
344			`spi_len <= 2'b00; // 8 bits`
345			`// Send a write enable command`
346			`spi_in <= { 8'h06, 24'h00 };`
347			state <= `WBQSPI_WRITE_STATUS;
348			`end`
349			`2'b11: begin // Write the ID register??? makes no sense`
350			`o_wb_ack <= 1'b1;`
351			`o_wb_stall <= 1'b0;`
352			`end`
353			`endcase`
354	7	dgisselq	`endif
355	2	dgisselq	`end else if ((i_wb_cyc)&&(i_wb_ctrl_stb)) // &&(~i_wb_we))`
356			`begin`
357			`case(i_wb_addr[1:0])`
358			`2'b00: begin // Read local register`
359			`if (write_in_progress) // Read status`
360			`begin// register, is write still in progress?`
361			state <= `WBQSPI_READ_STATUS;
362			`spi_wr <= 1'b1;`
363			`spi_len <= 2'b01;// 8 bits out, 8 bits in`
364			`spi_in <= { 8'h05, 24'h00};`
365
366			`o_wb_ack <= 1'b0;`
367			`o_wb_stall <= 1'b1;`
368			`end else begin // Return w/o talking to device`
369			`o_wb_ack <= 1'b1;`
370			`o_wb_stall <= 1'b0;`
371			`o_wb_data <= { write_in_progress,`
372			`dirty_sector, spi_busy,`
373			`~write_protect,`
374			`quad_mode_enabled,`
375	7	dgisselq	`{(29-ADDRESS_WIDTH){1'b0}},`
376	2	dgisselq	`erased_sector, 14'h000 };`
377			`end end`
378			`2'b01: begin // Read configuration register`
379			state <= `WBQSPI_READ_CONFIG;
380			`spi_wr <= 1'b1;`
381			`spi_len <= 2'b01;`
382			`spi_in <= { 8'h35, 24'h00};`
383
384			`o_wb_ack <= 1'b0;`
385			`o_wb_stall <= 1'b1;`
386			`end`
387			`2'b10: begin // Read status register`
388			state <= `WBQSPI_READ_STATUS;
389			`spi_wr <= 1'b1;`
390			`spi_len <= 2'b01; // 8 bits out, 8 bits in`
391			`spi_in <= { 8'h05, 24'h00};`
392
393			`o_wb_ack <= 1'b0;`
394			`o_wb_stall <= 1'b1;`
395			`end`
396			`2'b11: begin // Read ID register`
397			state <= `WBQSPI_READ_ID_CMD;
398			`spi_wr <= 1'b1;`
399			`spi_len <= 2'b00;`
400			`spi_in <= { 8'h9f, 24'h00};`
401
402			`o_wb_ack <= 1'b0;`
403			`o_wb_stall <= 1'b1;`
404			`end`
405			`endcase`
406	7	dgisselq	`ifndef READ_ONLY
407	2	dgisselq	`end else if ((~i_wb_cyc)&&(write_in_progress))`
408			`begin`
409			state <= `WBQSPI_IDLE_CHECK_WIP;
410			`spi_wr <= 1'b1;`
411			`spi_len <= 2'b01; // 8 bits out, 8 bits in`
412			`spi_in <= { 8'h05, 24'h00};`
413
414			`o_wb_ack <= 1'b0;`
415			`o_wb_stall <= 1'b1;`
416	7	dgisselq	`endif
417	2	dgisselq	`end`
418			end else if (state == `WBQSPI_RDIDLE)
419			`begin`
420			`spi_wr <= 1'b0;`
421			`o_wb_stall <= 1'b0;`
422			`o_wb_ack <= 1'b0;`
423			`spif_cmd <= i_wb_we;`
424			`spif_addr <= i_wb_addr;`
425			`spif_data <= i_wb_data;`
426			`spif_ctrl <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);`
427			`spif_req <= (i_wb_ctrl_stb)\|\|(i_wb_data_stb);`
428			`spi_hold <= 1'b0;`
429			`spi_spd<= 1'b1;`
430			`spi_dir <= 1'b0; // Write (for now)`
431			`if ((i_wb_cyc)&&(i_wb_data_stb)&&(~i_wb_we))`
432			`begin // Continue our read ... send the new address / mode`
433			`o_wb_stall <= 1'b1;`
434			`spi_wr <= 1'b1;`
435	4	dgisselq	`spi_len <= 2'b10; // Write address, but not mode byte`
436	7	dgisselq	`spi_in <= { {(24-ADDRESS_WIDTH){1'b0}},`
437			`i_wb_addr[(ADDRESS_WIDTH-3):0], 2'b00, 8'ha0 };`
438	2	dgisselq	state <= `WBQSPI_QRD_DUMMY;
439			`end else if((i_wb_cyc)&&(i_wb_ctrl_stb)&&(~i_wb_we)&&(i_wb_addr[1:0] == 2'b00))`
440			`begin`
441			`// A local read that doesn't touch the device, so leave`
442			`// the device in its current state`
443			`o_wb_stall <= 1'b0;`
444			`o_wb_ack <= 1'b1;`
445			`o_wb_data <= { write_in_progress,`
446			`dirty_sector, spi_busy,`
447			`~write_protect,`
448			`quad_mode_enabled,`
449	7	dgisselq	`{(29-ADDRESS_WIDTH){1'b0}},`
450	2	dgisselq	`erased_sector, 14'h000 };`
451			`end else if((i_wb_cyc)&&((i_wb_ctrl_stb)\|\|(i_wb_data_stb)))`
452			`begin // Need to release the device from quad mode for all else`
453			`o_wb_ack <= 1'b0;`
454			`o_wb_stall <= 1'b1;`
455			`spi_wr <= 1'b1;`
456			`spi_len <= 2'b11;`
457			`spi_in <= 32'h00;`
458			state <= `WBQSPI_WBDECODE;
459			`end`
460			end else if (state == `WBQSPI_WBDECODE)
461			`begin`
462			`// We were in quad SPI read mode, and had to get out.`
463			`// Now we've got a command (not data read) to read and`
464			`// execute. Accomplish what we would've done while in the`
465			`// IDLE state here, save only that we don't have to worry`
466			`// about data reads, and we need to operate on a stored`
467			`// version of the bus command`
468			`o_wb_stall <= 1'b1;`
469			`o_wb_ack <= 1'b0;`
470			`spi_wr <= 1'b0; // Keep the port idle, unless told otherwise`
471			`spi_hold <= 1'b0;`
472			`spi_spd <= 1'b0;`
473			`spi_dir <= 1'b0;`
474			`spif_req<= (spif_req) && (i_wb_cyc);`
475			`if ((~spi_busy)&&(o_qspi_cs_n)&&(~spi_wr)) // only in full idle ...`
476			`begin`
477			`// Data register access`
478			`if (~spif_ctrl)`
479			`begin`
480			`if (spif_cmd) // Request to write a page`
481			`begin`
482	7	dgisselq	`ifdef READ_ONLY
483			`o_wb_ack <= spif_req;`
484			`o_wb_stall <= 1'b0;`
485			state <= `WBQSPI_IDLE;
486			`else
487	2	dgisselq	`if((~write_protect)&&(~write_in_progress))`
488			`begin // 00`
489			`spi_wr <= 1'b1;`
490			`spi_len <= 2'b00; // 8 bits`
491			`// Send a write enable command`
492			`spi_in <= { 8'h06, 24'h00 };`
493			state <= `WBQSPI_WEN;
494
495			`o_wb_ack <= 1'b0;`
496			`o_wb_stall <= 1'b1;`
497			`end else if (write_protect)`
498			`begin // whether or not write-in_progress ...`
499			`// Do nothing on a write protect`
500			`// violation`

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