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franksdeve |
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_SIGNED.ALL;
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-- c2003 Franks Development, LLC
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-- http://www.franks-development.com
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-- !This source is distributed under the terms & conditions specified at opencores.org
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--resource or companion to this code:
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-- Xilinx Application note 12 - "Quadrature Phase Decoder" - xapp012.pdf
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-- no longer appears on xilinx website (to best of my knowledge), perhaps it has been superceeded?
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--this code was origonally intended for use on Xilinx XPLA3 'coolrunner' CPLD devices
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--origonally compiled/synthesized with Xilinx 'Webpack' 5.2 software
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--How we 'talk' to the outside world:
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entity QuadratureCounterPorts is
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Port ( clock : in std_logic; --system clock, i.e. 10MHz oscillator
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QuadA : in std_logic; --first input from quadrature device (i.e. optical disk encoder)
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QuadB : in std_logic; --second input from quadrature device (i.e. optical disk encoder)
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CounterValue : out std_logic_vector(15 downto 0) --just an example debuggin output
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);
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end QuadratureCounterPorts;
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--What we 'do':
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architecture QuadratureCounter of QuadratureCounterPorts is
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-- local 'variables' or 'registers'
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--This is the counter for how many quadrature ticks have gone past.
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--the size of this counter is dependant on how far you need to count
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--it was origonally used with a circular disk encoder having 2048 ticks/revolution
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--thus this 16-bit count could hold 2^15 ticks in either direction, or a total
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--of 32768/2048 = 16 revolutions in either direction. if the disk
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--was turned more than 16 times in a given direction, the counter overflows
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--and the origonal location is lost. If you had a linear instead of
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--circular encoder that physically could not move more than 2048 ticks,
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--then Count would only need to be 11 downto 0, and you could count
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--2048 ticks in either direction, regardless of the position of the
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--encoder at system bootup.
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signal Count : std_logic_vector(15 downto 0);
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--this is the signal from the quadrature logic that it is time to change
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--the value of the counter on this clock signal (either + or -)
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signal CountEnable : std_logic;
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--should we increment or decrement count?
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signal CountDirection : std_logic;
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--where all the 'work' is done: quadraturedecoder.vhd
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component QuadratureDecoderPorts
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Port (
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clock : in std_logic;
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QuadA : in std_logic;
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QuadB : in std_logic;
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franksdeve |
Direction : out std_logic;
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2 |
franksdeve |
CountEnable : out std_logic
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);
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end component;
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begin --architecture QuadratureCounter
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--instanciate the decoder
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iQuadratureDecoder: QuadratureDecoderPorts
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port map (
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clock => clock,
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QuadA => QuadA,
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QuadB => QuadB,
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franksdeve |
Direction => CountDirection,
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franksdeve |
CountEnable => CountEnable
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);
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-- do our actual work every clock cycle
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process(clock)
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begin
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--keep track of the counter
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if ( (clock'event) and (clock = '1') ) then
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if (CountEnable = '1') then
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if (CountDirection = '1') then Count <= Count + "0000000000000001"; end if;
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if (CountDirection = '0') then Count <= Count - "0000000000000001"; end if;
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end if;
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end if; --clock'event
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--!!!!!!!!!!!INSERT SOMETHING USEFULL HERE!!!!!!!!!!!
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--This is where you do actual work based on the value of the counter
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--for instance, I will just output the value of the counter
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--led's on an output like this are very useful - you can see the top
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--bits light when moved backwards from initial position (count goes negative)
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CounterValue <= Count;
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end process; --(clock)
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end QuadratureCounter;
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