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[/] [quark/] [trunk/] [05_HDLConstruction/] [01_OldArchitecture_ReferenceOnly/] [Alu/] [Alu.v] - Blame information for rev 9

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////////////////////////////////////////////////
// @file  ALU.v
// @brief ALU design for Quantum processor
// @date  9/6/2014
////////////////////////////////////////////////
 
`include "Alu.vh"
 
module ModAlu (
  input             Clock,
  input             Reset,
  input      [0:7]  AluInstruction,
  input      [0:7]  AluInput1,
  input      [0:7]  AluInput2,
  output reg [0:15] AluResult
  );
 
  always@(posedge Clock, negedge Reset) begin
    if (Reset == 1'b0) begin
      AluResult <= 16'h00;
    end else begin
      case (AluInstruction)
        `Idle: begin
          AluResult <= AluResult;
        end
        `And: begin
          AluResult <= AluInput2 & AluInput1;
        end
        `Or: begin
          AluResult <= AluInput2 | AluInput1;
        end
        `XNOr: begin
          AluResult <= AluInput2 ^~ AluInput1;
        end
        `XOr: begin
          AluResult <= AluInput2 ^ AluInput1;
        end
        `Not: begin
          AluResult <= {AluInput2, AluInput1};
        end
        `Add: begin
          AluResult <= AluInput2 + AluInput1;
        end
        `Sub: begin
          AluResult <= AluInput2 - AluInput1;
        end
        default: begin
          AluResult <= AluResult;
        end
      endcase
    end
  end
endmodule
 
////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////

Line No.	Rev	Author	Line
1	3	progman32	`////////////////////////////////////////////////`
2			`// @file ALU.v`
3			`// @brief ALU design for Quantum processor`
4			`// @date 9/6/2014`
5			`////////////////////////////////////////////////`
6
7			`include "Alu.vh"
8
9			`module ModAlu (`
10			`input Clock,`
11			`input Reset,`
12			`input [0:7] AluInstruction,`
13			`input [0:7] AluInput1,`
14			`input [0:7] AluInput2,`
15			`output reg [0:15] AluResult`
16			`);`
17
18			`always@(posedge Clock, negedge Reset) begin`
19			`if (Reset == 1'b0) begin`
20			`AluResult <= 16'h00;`
21			`end else begin`
22			`case (AluInstruction)`
23			`Idle: begin
24			`AluResult <= AluResult;`
25			`end`
26			`And: begin
27			`AluResult <= AluInput2 & AluInput1;`
28			`end`
29			`Or: begin
30			`AluResult <= AluInput2 \| AluInput1;`
31			`end`
32			`XNOr: begin
33			`AluResult <= AluInput2 ^~ AluInput1;`
34			`end`
35			`XOr: begin
36			`AluResult <= AluInput2 ^ AluInput1;`
37			`end`
38			`Not: begin
39			`AluResult <= {AluInput2, AluInput1};`
40			`end`
41			`Add: begin
42			`AluResult <= AluInput2 + AluInput1;`
43			`end`
44			`Sub: begin
45			`AluResult <= AluInput2 - AluInput1;`
46			`end`
47			`default: begin`
48			`AluResult <= AluResult;`
49			`end`
50			`endcase`
51			`end`
52			`end`
53			`endmodule`
54
55			`////////////////////////////////////////////////`
56			`// EOF`
57			`////////////////////////////////////////////////`

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[/] [quark/] [trunk/] [05_HDLConstruction/] [01_OldArchitecture_ReferenceOnly/] [Alu/] [Alu.v] - Blame information for rev 9