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`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////

// Company: 

// Engineer:

//

// Create Date:   22:11:23 09/06/2014

// Design Name:   ModAlu

// Module Name:   C:/Quantum/ALU/ALU_TB.v

// Project Name:  Quantum

// Target Device:  

// Tool versions:  

// Description: 

//

// Verilog Test Fixture created by ISE for module: ModAlu

//

// Dependencies:

// 

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

// 

////////////////////////////////////////////////////////////////////////////////

module ALU_TB;

        // Inputs

        reg Clock;

        reg Reset;

        reg [0:7] Mnemonic;

        reg [0:7] Data0;

        reg [0:7] Data1;

        // Outputs

        wire [0:15] Result;

        // Instantiate the Unit Under Test (UUT)

        ModAlu uut (

                .Clock(Clock),

                .Reset(Reset),

                .Mnemonic(Mnemonic),

                .Data0(Data0),

                .Data1(Data1),

                .Result(Result)

        );

   always@(*) begin

          #10;

          Clock = ~Clock;

        end

        initial begin

                // Initialize Inputs

                Reset = 0;

                Mnemonic = 0;

                Data0 = 0;

                Data1 = 0;

                // Wait 100 ns for global reset to finish

                #100;

                // Add stimulus here

        end

endmodule