OpenCores
URL https://opencores.org/ocsvn/quark/quark/trunk

Subversion Repositories quark

[/] [quark/] [trunk/] [05_HDLConstruction/] [01_OldArchitecture_ReferenceOnly/] [ControlUnit/] [ControlUnit.v] - Blame information for rev 10

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 progman32
////////////////////////////////////////////////
2
// @file  ControlUnit.v
3
// @brief Control Unit of Quantum Processor
4
// @date  9/28/2014
5
////////////////////////////////////////////////
6
 
7
module ControlUnit (
8
  input         Clock,
9
  input         Reset,
10
  input  [0:7]  BusDataIn,
11
  input  [0:15] AluResult,
12
  output        IncrementPC,
13
  output        WritePC,
14
  output        WriteEnable,
15
  output [0:7]  BusDataOut,
16
  output [0:7]  NewPC,
17
  output [0:7]  AluInstruction,
18
  output [0:7]  AluInput1,
19
  output [0:7]  AluInput2,
20
  output [0:7]  REGA,
21
  output [0:7]  REGB,
22
  output [0:7]  REGC,
23
  output [0:7]  REGX,
24
  output [0:7]  REGY,
25
  output [0:7]  REGZ
26
  );
27
 
28
  wire [0:15] ExecuteCode;
29
  wire [0:7]  Opcode;
30
  wire [0:7]  FetchTemporalReg1;
31
  wire [0:7]  FetchTemporalReg2;
32
  wire [0:7]  FetchTemporalReg3;
33
  wire        RequestDecode;
34
  wire        DecodeIsBusy;
35
  wire        LockPC;
36
  wire        PCIsNotLocked;
37
  wire        IncrementPC1;
38
  wire        ExecuteIsBusy;
39
  wire        RequestExecute;
40
  wire        MemoryIsCorrupted;
41
  wire        RequestUnlockPC;
42
 
43
  FetchUnit FetchUnit(
44
    .Clock             (Clock),
45
    .Reset             (Reset),
46
    .DecodeIsBusy      (DecodeIsBusy),
47
    .RequestUnlockPC   (RequestUnlockPC),
48
    .BusDataIn         (BusDataIn),
49
    .Opcode            (Opcode),
50
    .FetchTemporalReg1 (FetchTemporalReg1),
51
    .FetchTemporalReg2 (FetchTemporalReg2),
52
    .FetchTemporalReg3 (FetchTemporalReg3),
53
    .RequestDecode     (RequestDecode),
54
    .LockPC            (LockPC),
55
    .PCIsNotLocked     (PCIsNotLocked),
56
    .IncrementPC       (IncrementPC1)
57
  );
58
 
59
  DecodeUnit DecodeUnit(
60
    .Clock             (Clock),
61
    .Reset             (Reset),
62
    .RequestDecode     (RequestDecode),
63
    .ExecuteIsBusy     (ExecuteIsBusy),
64
    .Opcode            (Opcode),
65
    .FetchTemporalReg1 (FetchTemporalReg1),
66
    .FetchTemporalReg2 (FetchTemporalReg2),
67
    .FetchTemporalReg3 (FetchTemporalReg3),
68
    .ExecuteCode       (ExecuteCode),
69
    .DecodeIsBusy      (DecodeIsBusy),
70
    .RequestExecute    (RequestExecute),
71
    .MemoryIsCorrupted (MemoryIsCorrupted)
72
  );
73
 
74
  ExecuteUnit ExecuteUnit(
75
    .Clock             (Clock),
76
    .Reset             (Reset),
77
    .RequestExecute    (RequestExecute),
78
    .AluResult         (AluResult),
79
    .ExecuteCode       (ExecuteCode),
80
    .FetchTemporalReg1 (FetchTemporalReg1),
81
    .FetchTemporalReg2 (FetchTemporalReg2),
82
    .FetchTemporalReg3 (FetchTemporalReg3),
83
    .REGA              (REGA),
84
    .REGB              (REGB),
85
    .REGC              (REGC),
86
    .REGX              (REGX),
87
    .REGY              (REGY),
88
    .REGZ              (REGZ),
89
    .AluInput1         (AluInput1),
90
    .AluInput2         (AluInput2),
91
    .AluInstruction    (AluInstruction),
92
    .BusDataOut        (BusDataOut),
93
    .NewPC             (NewPC),
94
    .WritePC           (WritePC),
95
    .ExecuteIsBusy     (ExecuteIsBusy),
96
    .RequestUnlockPC   (RequestUnlockPC),
97
    .WriteEnable       (WriteEnable)
98
  );
99
 
100
  assign IncrementPC = PCIsNotLocked & IncrementPC1;
101
endmodule
102
 
103
////////////////////////////////////////////////
104
// EOF
105
////////////////////////////////////////////////

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.