1 |
3 |
progman32 |
////////////////////////////////////////////////
|
2 |
|
|
// @file DecodeUnit.v
|
3 |
|
|
// @brief Decode Unit for Quantum Processor
|
4 |
|
|
// @date 9/28/2014
|
5 |
|
|
////////////////////////////////////////////////
|
6 |
|
|
|
7 |
|
|
`include "DecodeUnit.vh"
|
8 |
|
|
`include "../ExecuteUnit/ExecuteUnit.vh"
|
9 |
|
|
`include "../FetchUnit/FetchUnit.vh"
|
10 |
|
|
|
11 |
|
|
module DecodeUnit (
|
12 |
|
|
input Clock,
|
13 |
|
|
input Reset,
|
14 |
|
|
input RequestDecode,
|
15 |
|
|
input ExecuteIsBusy,
|
16 |
|
|
input [0:7] Opcode,
|
17 |
|
|
input [0:7] FetchTemporalReg1,
|
18 |
|
|
input [0:7] FetchTemporalReg2,
|
19 |
|
|
input [0:7] FetchTemporalReg3,
|
20 |
|
|
output reg [0:15] ExecuteCode,
|
21 |
|
|
output reg DecodeIsBusy,
|
22 |
|
|
output reg RequestExecute,
|
23 |
|
|
output reg MemoryIsCorrupted
|
24 |
|
|
);
|
25 |
|
|
|
26 |
|
|
reg [0:7] DecodeState;
|
27 |
|
|
|
28 |
|
|
always@(posedge Clock, negedge Reset) begin
|
29 |
|
|
if (Reset == 1'b0) begin
|
30 |
|
|
DecodeIsBusy <= 1'b1;
|
31 |
|
|
RequestExecute <= 1'b0;
|
32 |
|
|
MemoryIsCorrupted <= 1'b0;
|
33 |
|
|
ExecuteCode <= `idle;
|
34 |
|
|
DecodeState <= `Decode;
|
35 |
|
|
end else begin
|
36 |
|
|
DecodeIsBusy <= 1'b1;
|
37 |
|
|
|
38 |
|
|
case(DecodeState)
|
39 |
|
|
`Decode: begin
|
40 |
|
|
if (RequestDecode == 1'b1) begin
|
41 |
|
|
DecodeState <= `RequestExecute;
|
42 |
|
|
|
43 |
|
|
//////////////////////////////////////////////////
|
44 |
|
|
///// Load Instructions
|
45 |
|
|
//////////////////////////////////////////////////
|
46 |
|
|
if ((Opcode == `ldr) && (FetchTemporalReg1 == `rega)) begin
|
47 |
|
|
ExecuteCode <= `ldr_rega_data;
|
48 |
|
|
end else if ((Opcode == `ldr) && (FetchTemporalReg1 == `regb)) begin
|
49 |
|
|
ExecuteCode <= `ldr_regb_data;
|
50 |
|
|
end else if ((Opcode == `ldr) && (FetchTemporalReg1 == `regc)) begin
|
51 |
|
|
ExecuteCode <= `ldr_regc_data;
|
52 |
|
|
end else if ((Opcode == `ldr) && (FetchTemporalReg1 == `regx)) begin
|
53 |
|
|
ExecuteCode <= `ldr_regx_data;
|
54 |
|
|
end else if ((Opcode == `ldr) && (FetchTemporalReg1 == `regy)) begin
|
55 |
|
|
ExecuteCode <= `ldr_regy_data;
|
56 |
|
|
end else if ((Opcode == `ldr) && (FetchTemporalReg1 == `regz)) begin
|
57 |
|
|
ExecuteCode <= `ldr_regz_data;
|
58 |
|
|
end else if (Opcode == `ldm) begin
|
59 |
|
|
ExecuteCode <= `ldm_addr_data;
|
60 |
|
|
|
61 |
|
|
//////////////////////////////////////////////////
|
62 |
|
|
///// Addition operations
|
63 |
|
|
//////////////////////////////////////////////////
|
64 |
|
|
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `rega) && (FetchTemporalReg2 == `rega)) begin
|
65 |
|
|
ExecuteCode <= `addrr_rega_rega;
|
66 |
|
|
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `rega) && (FetchTemporalReg2 == `regb)) begin
|
67 |
|
|
ExecuteCode <= `addrr_rega_regb;
|
68 |
|
|
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `rega) && (FetchTemporalReg2 == `regc)) begin
|
69 |
|
|
ExecuteCode <= `addrr_rega_regc;
|
70 |
|
|
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `rega) && (FetchTemporalReg2 == `regx)) begin
|
71 |
|
|
ExecuteCode <= `addrr_rega_regx;
|
72 |
|
|
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `rega) && (FetchTemporalReg2 == `regy)) begin
|
73 |
|
|
ExecuteCode <= `addrr_rega_regy;
|
74 |
|
|
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `rega) && (FetchTemporalReg2 == `regz)) begin
|
75 |
|
|
ExecuteCode <= `addrr_rega_regz;
|
76 |
|
|
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regb) && (FetchTemporalReg2 == `rega)) begin
|
77 |
|
|
ExecuteCode <= `addrr_regb_rega;
|
78 |
|
|
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regb) && (FetchTemporalReg2 == `regb)) begin
|
79 |
|
|
ExecuteCode <= `addrr_regb_regb;
|
80 |
|
|
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regb) && (FetchTemporalReg2 == `regc)) begin
|
81 |
|
|
ExecuteCode <= `addrr_regb_regc;
|
82 |
|
|
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regb) && (FetchTemporalReg2 == `regx)) begin
|
83 |
|
|
ExecuteCode <= `addrr_regb_regx;
|
84 |
|
|
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regb) && (FetchTemporalReg2 == `regy)) begin
|
85 |
|
|
ExecuteCode <= `addrr_regb_regy;
|
86 |
|
|
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regb) && (FetchTemporalReg2 == `regz)) begin
|
87 |
|
|
ExecuteCode <= `addrr_regb_regz;
|
88 |
|
|
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regc) && (FetchTemporalReg2 == `rega)) begin
|
89 |
|
|
ExecuteCode <= `addrr_regc_rega;
|
90 |
|
|
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regc) && (FetchTemporalReg2 == `regb)) begin
|
91 |
|
|
ExecuteCode <= `addrr_regc_regb;
|
92 |
|
|
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regc) && (FetchTemporalReg2 == `regc)) begin
|
93 |
|
|
ExecuteCode <= `addrr_regc_regc;
|
94 |
|
|
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regc) && (FetchTemporalReg2 == `regx)) begin
|
95 |
|
|
ExecuteCode <= `addrr_regc_regx;
|
96 |
|
|
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regc) && (FetchTemporalReg2 == `regy)) begin
|
97 |
|
|
ExecuteCode <= `addrr_regc_regy;
|
98 |
|
|
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regc) && (FetchTemporalReg2 == `regz)) begin
|
99 |
|
|
ExecuteCode <= `addrr_regc_regz;
|
100 |
|
|
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regx) && (FetchTemporalReg2 == `rega)) begin
|
101 |
|
|
ExecuteCode <= `addrr_regx_rega;
|
102 |
|
|
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regx) && (FetchTemporalReg2 == `regb)) begin
|
103 |
|
|
ExecuteCode <= `addrr_regx_regb;
|
104 |
|
|
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regx) && (FetchTemporalReg2 == `regc)) begin
|
105 |
|
|
ExecuteCode <= `addrr_regx_regc;
|
106 |
|
|
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regx) && (FetchTemporalReg2 == `regx)) begin
|
107 |
|
|
ExecuteCode <= `addrr_regx_regx;
|
108 |
|
|
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regx) && (FetchTemporalReg2 == `regy)) begin
|
109 |
|
|
ExecuteCode <= `addrr_regx_regy;
|
110 |
|
|
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regx) && (FetchTemporalReg2 == `regz)) begin
|
111 |
|
|
ExecuteCode <= `addrr_regx_regz;
|
112 |
|
|
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regy) && (FetchTemporalReg2 == `rega)) begin
|
113 |
|
|
ExecuteCode <= `addrr_regy_rega;
|
114 |
|
|
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regy) && (FetchTemporalReg2 == `regb)) begin
|
115 |
|
|
ExecuteCode <= `addrr_regy_regb;
|
116 |
|
|
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regy) && (FetchTemporalReg2 == `regc)) begin
|
117 |
|
|
ExecuteCode <= `addrr_regy_regc;
|
118 |
|
|
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regy) && (FetchTemporalReg2 == `regx)) begin
|
119 |
|
|
ExecuteCode <= `addrr_regy_regx;
|
120 |
|
|
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regy) && (FetchTemporalReg2 == `regy)) begin
|
121 |
|
|
ExecuteCode <= `addrr_regy_regy;
|
122 |
|
|
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regy) && (FetchTemporalReg2 == `regz)) begin
|
123 |
|
|
ExecuteCode <= `addrr_regy_regz;
|
124 |
|
|
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regz) && (FetchTemporalReg2 == `rega)) begin
|
125 |
|
|
ExecuteCode <= `addrr_regz_rega;
|
126 |
|
|
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regz) && (FetchTemporalReg2 == `regb)) begin
|
127 |
|
|
ExecuteCode <= `addrr_regz_regb;
|
128 |
|
|
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regz) && (FetchTemporalReg2 == `regc)) begin
|
129 |
|
|
ExecuteCode <= `addrr_regz_regc;
|
130 |
|
|
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regz) && (FetchTemporalReg2 == `regx)) begin
|
131 |
|
|
ExecuteCode <= `addrr_regz_regx;
|
132 |
|
|
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regz) && (FetchTemporalReg2 == `regy)) begin
|
133 |
|
|
ExecuteCode <= `addrr_regz_regy;
|
134 |
|
|
end else if ((Opcode == `addrr) && (FetchTemporalReg1 == `regz) && (FetchTemporalReg2 == `regz)) begin
|
135 |
|
|
ExecuteCode <= `addrr_regz_regz;
|
136 |
|
|
end else if ((Opcode == `addrm) && (FetchTemporalReg1 == `rega)) begin
|
137 |
|
|
ExecuteCode <= `addrm_rega_addr;
|
138 |
|
|
end else if ((Opcode == `addrm) && (FetchTemporalReg1 == `regb)) begin
|
139 |
|
|
ExecuteCode <= `addrm_regb_addr;
|
140 |
|
|
end else if ((Opcode == `addrm) && (FetchTemporalReg1 == `regc)) begin
|
141 |
|
|
ExecuteCode <= `addrm_regc_addr;
|
142 |
|
|
end else if ((Opcode == `addrm) && (FetchTemporalReg1 == `regx)) begin
|
143 |
|
|
ExecuteCode <= `addrm_regx_addr;
|
144 |
|
|
end else if ((Opcode == `addrm) && (FetchTemporalReg1 == `regy)) begin
|
145 |
|
|
ExecuteCode <= `addrm_regy_addr;
|
146 |
|
|
end else if ((Opcode == `addrm) && (FetchTemporalReg1 == `regz)) begin
|
147 |
|
|
ExecuteCode <= `addrm_regz_addr;
|
148 |
|
|
end else if ((Opcode == `addmr) && (FetchTemporalReg2 == `rega)) begin
|
149 |
|
|
ExecuteCode <= `addmr_addr_rega;
|
150 |
|
|
end else if ((Opcode == `addmr) && (FetchTemporalReg2 == `regb)) begin
|
151 |
|
|
ExecuteCode <= `addmr_addr_regb;
|
152 |
|
|
end else if ((Opcode == `addmr) && (FetchTemporalReg2 == `regc)) begin
|
153 |
|
|
ExecuteCode <= `addmr_addr_regc;
|
154 |
|
|
end else if ((Opcode == `addmr) && (FetchTemporalReg2 == `regx)) begin
|
155 |
|
|
ExecuteCode <= `addmr_addr_regx;
|
156 |
|
|
end else if ((Opcode == `addmr) && (FetchTemporalReg2 == `regy)) begin
|
157 |
|
|
ExecuteCode <= `addmr_addr_regy;
|
158 |
|
|
end else if ((Opcode == `addmr) && (FetchTemporalReg2 == `regz)) begin
|
159 |
|
|
ExecuteCode <= `addmr_addr_regz;
|
160 |
|
|
end else if (Opcode == `addmm) begin
|
161 |
|
|
ExecuteCode <= `addmm_addr_addr;
|
162 |
|
|
|
163 |
|
|
//////////////////////////////////////////////////
|
164 |
|
|
///// Branch Instructions
|
165 |
|
|
//////////////////////////////////////////////////
|
166 |
|
|
end else if ((Opcode == `breqrr) && (FetchTemporalReg1 == `rega) && (FetchTemporalReg2 == `regb)) begin
|
167 |
|
|
ExecuteCode <= `breqrr_rega_regb;
|
168 |
|
|
end else if ((Opcode == `breqrr) && (FetchTemporalReg1 == `rega) && (FetchTemporalReg2 == `regc)) begin
|
169 |
|
|
ExecuteCode <= `breqrr_rega_regc;
|
170 |
|
|
end else if ((Opcode == `breqrr) && (FetchTemporalReg1 == `rega) && (FetchTemporalReg2 == `regx)) begin
|
171 |
|
|
ExecuteCode <= `breqrr_rega_regx;
|
172 |
|
|
end else if ((Opcode == `breqrr) && (FetchTemporalReg1 == `rega) && (FetchTemporalReg2 == `regy)) begin
|
173 |
|
|
ExecuteCode <= `breqrr_rega_regy;
|
174 |
|
|
end else if ((Opcode == `breqrr) && (FetchTemporalReg1 == `rega) && (FetchTemporalReg2 == `regz)) begin
|
175 |
|
|
ExecuteCode <= `breqrr_rega_regz;
|
176 |
|
|
end else if ((Opcode == `breqrr) && (FetchTemporalReg1 == `regb) && (FetchTemporalReg2 == `rega)) begin
|
177 |
|
|
ExecuteCode <= `breqrr_regb_rega;
|
178 |
|
|
end else if ((Opcode == `breqrr) && (FetchTemporalReg1 == `regb) && (FetchTemporalReg2 == `regc)) begin
|
179 |
|
|
ExecuteCode <= `breqrr_regb_regc;
|
180 |
|
|
end else if ((Opcode == `breqrr) && (FetchTemporalReg1 == `regb) && (FetchTemporalReg2 == `regx)) begin
|
181 |
|
|
ExecuteCode <= `breqrr_regb_regx;
|
182 |
|
|
end else if ((Opcode == `breqrr) && (FetchTemporalReg1 == `regb) && (FetchTemporalReg2 == `regy)) begin
|
183 |
|
|
ExecuteCode <= `breqrr_regb_regy;
|
184 |
|
|
end else if ((Opcode == `breqrr) && (FetchTemporalReg1 == `regb) && (FetchTemporalReg2 == `regz)) begin
|
185 |
|
|
ExecuteCode <= `breqrr_regb_regz;
|
186 |
|
|
end else if ((Opcode == `breqrr) && (FetchTemporalReg1 == `regc) && (FetchTemporalReg2 == `rega)) begin
|
187 |
|
|
ExecuteCode <= `breqrr_regc_rega;
|
188 |
|
|
end else if ((Opcode == `breqrr) && (FetchTemporalReg1 == `regc) && (FetchTemporalReg2 == `regb)) begin
|
189 |
|
|
ExecuteCode <= `breqrr_regc_regb;
|
190 |
|
|
end else if ((Opcode == `breqrr) && (FetchTemporalReg1 == `regc) && (FetchTemporalReg2 == `regx)) begin
|
191 |
|
|
ExecuteCode <= `breqrr_regc_regx;
|
192 |
|
|
end else if ((Opcode == `breqrr) && (FetchTemporalReg1 == `regc) && (FetchTemporalReg2 == `regy)) begin
|
193 |
|
|
ExecuteCode <= `breqrr_regc_regy;
|
194 |
|
|
end else if ((Opcode == `breqrr) && (FetchTemporalReg1 == `regc) && (FetchTemporalReg2 == `regz)) begin
|
195 |
|
|
ExecuteCode <= `breqrr_regc_regz;
|
196 |
|
|
end else if ((Opcode == `breqrm) && (FetchTemporalReg1 == `rega)) begin
|
197 |
|
|
ExecuteCode <= `breqrm_rega_addr;
|
198 |
|
|
end else if ((Opcode == `breqrm) && (FetchTemporalReg1 == `regb)) begin
|
199 |
|
|
ExecuteCode <= `breqrm_regb_addr;
|
200 |
|
|
end else if ((Opcode == `breqrm) && (FetchTemporalReg1 == `regc)) begin
|
201 |
|
|
ExecuteCode <= `breqrm_regc_addr;
|
202 |
|
|
end else if ((Opcode == `breqrm) && (FetchTemporalReg1 == `regx)) begin
|
203 |
|
|
ExecuteCode <= `breqrm_regx_addr;
|
204 |
|
|
end else if ((Opcode == `breqrm) && (FetchTemporalReg1 == `regy)) begin
|
205 |
|
|
ExecuteCode <= `breqrm_regy_addr;
|
206 |
|
|
end else if ((Opcode == `breqrm) && (FetchTemporalReg1 == `regz)) begin
|
207 |
|
|
ExecuteCode <= `breqrm_regz_addr;
|
208 |
|
|
end else if (Opcode == `breqmm) begin
|
209 |
|
|
ExecuteCode <= `breqmm_addr_addr;
|
210 |
|
|
|
211 |
|
|
//////////////////////////////////////////////////
|
212 |
|
|
///// Jump Instructions
|
213 |
|
|
//////////////////////////////////////////////////
|
214 |
|
|
end else if ((Opcode == `jmpr) && (FetchTemporalReg1 == `rega)) begin
|
215 |
|
|
ExecuteCode <= `jmpr_rega;
|
216 |
|
|
end else if ((Opcode == `jmpr) && (FetchTemporalReg1 == `regb)) begin
|
217 |
|
|
ExecuteCode <= `jmpr_regb;
|
218 |
|
|
end else if ((Opcode == `jmpr) && (FetchTemporalReg1 == `regc)) begin
|
219 |
|
|
ExecuteCode <= `jmpr_regc;
|
220 |
|
|
end else if ((Opcode == `jmpr) && (FetchTemporalReg1 == `regx)) begin
|
221 |
|
|
ExecuteCode <= `jmpr_regx;
|
222 |
|
|
end else if ((Opcode == `jmpr) && (FetchTemporalReg1 == `regy)) begin
|
223 |
|
|
ExecuteCode <= `jmpr_regy;
|
224 |
|
|
end else if ((Opcode == `jmpr) && (FetchTemporalReg1 == `regz)) begin
|
225 |
|
|
ExecuteCode <= `jmpr_regz;
|
226 |
|
|
end else if (Opcode == `jmpm) begin
|
227 |
|
|
ExecuteCode <= `jmpm_addr;
|
228 |
|
|
end else begin
|
229 |
|
|
ExecuteCode <= `idle;
|
230 |
|
|
MemoryIsCorrupted <= 1'b0;
|
231 |
|
|
DecodeState <= `Decode;
|
232 |
|
|
end
|
233 |
|
|
end
|
234 |
|
|
end
|
235 |
|
|
|
236 |
|
|
`RequestExecute: begin
|
237 |
|
|
RequestExecute <= 1'b1;
|
238 |
|
|
DecodeState <= `WaitRequest;
|
239 |
|
|
end
|
240 |
|
|
|
241 |
|
|
`WaitRequest: begin
|
242 |
|
|
DecodeState <= `WaitExecute;
|
243 |
|
|
end
|
244 |
|
|
|
245 |
|
|
`WaitExecute: begin
|
246 |
|
|
if (ExecuteIsBusy == 1'b0) begin
|
247 |
|
|
DecodeState <= `ResetDecodeSM;
|
248 |
|
|
RequestExecute <= 1'b0;
|
249 |
|
|
DecodeIsBusy <= 1'b0;
|
250 |
|
|
ExecuteCode <= `idle;
|
251 |
|
|
end
|
252 |
|
|
end
|
253 |
|
|
|
254 |
|
|
`ResetDecodeSM: begin
|
255 |
|
|
if (RequestDecode == 1'b0) begin
|
256 |
|
|
DecodeState <= `Decode;
|
257 |
|
|
end
|
258 |
|
|
end
|
259 |
|
|
endcase
|
260 |
|
|
end
|
261 |
|
|
end
|
262 |
|
|
endmodule
|
263 |
|
|
|
264 |
|
|
////////////////////////////////////////////////
|
265 |
|
|
// EOF
|
266 |
|
|
////////////////////////////////////////////////
|