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[/] [quark/] [trunk/] [05_HDLConstruction/] [01_OldArchitecture_ReferenceOnly/] [Memory/] [RomMemory.vhd] - Blame information for rev 12

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Line No. Rev Author Line
1 3 progman32 
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity ROM is port(
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  Clock:       in  std_logic;
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  Reset:       in  std_logic;
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  WriteEnable: in  std_logic;
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  DataOut:     out std_logic_vector(7 downto 0);
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  DataIn:      in  std_logic_vector(7 downto 0);
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  Address:     in  std_logic_vector(7 downto 0)
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  );
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end ROM;
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architecture ArchRom of ROM is
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  --****************************
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  --* Define Opcodes
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  --****************************
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  constant nop:    std_logic_vector(7 downto 0) := x"00";
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  constant ldr:    std_logic_vector(7 downto 0) := x"01";
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  constant ldm:    std_logic_vector(7 downto 0) := x"02";
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  constant addrr:  std_logic_vector(7 downto 0) := x"03";
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  constant addrm:  std_logic_vector(7 downto 0) := x"04";
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  constant addmr:  std_logic_vector(7 downto 0) := x"05";
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  constant addmm:  std_logic_vector(7 downto 0) := x"06";
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  constant breqrr: std_logic_vector(7 downto 0) := x"07";
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  constant breqrm: std_logic_vector(7 downto 0) := x"08";
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  constant breqmm: std_logic_vector(7 downto 0) := x"09";
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  constant jmpr:   std_logic_vector(7 downto 0) := x"0A";
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  constant jmpm:   std_logic_vector(7 downto 0) := x"0B";
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  --****************************
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  --* Define Registers
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  --****************************
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  constant rega: std_logic_vector(7 downto 0) := x"00";
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  constant regb: std_logic_vector(7 downto 0) := x"01";
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  constant regc: std_logic_vector(7 downto 0) := x"02";
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  constant regx: std_logic_vector(7 downto 0) := x"03";
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  constant regy: std_logic_vector(7 downto 0) := x"04";
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  constant regz: std_logic_vector(7 downto 0) := x"05";
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  --****************************
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  --* Define Asm Labels
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  --****************************
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  constant LoopLabel: std_logic_vector(7 downto 0) := x"12";
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  type ROMA is array(0 to 255) of std_logic_vector(7 downto 0);
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  signal ROM1: ROMA:=(
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    --##################################
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    --## PROGRAM 1
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    --##################################
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    ldr, rega, x"00",
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    ldr, regb, x"00",
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    ldr, regc, x"00",
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    ldr, regx, x"01",
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    ldr, regy, x"ff",
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    ldr, regz, LoopLabel,
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--LoopLabel:
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    addrr,  rega, regx,
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    breqrr, rega, regy, LoopLabel,
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    ldr,    rega, x"00",
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    addrr,  regb, regx,
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    breqrr, regb, regy, LoopLabel,
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    ldr,    regb, x"00",
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    addrr,  regc, regx,
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    jmpr,   regz,
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    --adda,  x"01",
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    --brnea, x"FF", x"00",
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    --lda,   x"00",
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    --addb,  x"01",
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    --brneb, x"FF", x"00",
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    --addc,  x"01",
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    --ldgpc,
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    --ldb,   x"00",
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    --jmp,   x"00",
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00"),
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    (x"00")
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  );
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  attribute ramstyle : string;
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  --attribute ramstyle of ROM1 : signal is "M512";
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begin
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  process(Clock, Reset) begin
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    if (Reset = '0') then
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      DataOut <= x"00";
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    elsif rising_edge(Clock) then
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      if (WriteEnable = '1') then
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        ROM1 (conv_integer(Address)) <= DataIn;
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      else
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        DataOut <= ROM1(conv_integer(Address));
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      end if;
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    end if;
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  end process;
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end ArchRom;

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