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[/] [quark/] [trunk/] [05_HDLConstruction/] [01_OldArchitecture_ReferenceOnly/] [contador0-999.vhd] - Blame information for rev 10

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
entity contador is port(
   clk, rst: in std_logic;
   DECO: out std_logic_vector(6 downto 0);
        AP: out std_logic;
        barrido: out std_logic_vector(2 downto 0));
end contador;
 
architecture cont of contador is
   type states is (state0, state1, state2);
        signal state: states;
        signal cnt1, cnt2: std_logic_vector(31 downto 0);
        signal contU, contD, contC: std_logic_vector(3 downto 0);
   signal temp1, temp2: std_logic;
        signal p1, p2, p3: std_logic;
        signal MUX: std_logic_vector(3 downto 0);
        signal barr: std_logic_vector(2 downto 0);
begin
 
divisor1: process(clk,rst)
   begin
      if (rst='1') then
         temp1 <= '0';
         cnt1 <= conv_std_logic_vector(0,32);
      elsif(clk'event and clk='1') then
         if (cnt1=conv_std_logic_vector(25000000,32)) then
            temp1 <= not temp1;
            cnt1 <= conv_std_logic_vector(0,32);
         else
            cnt1 <= cnt1 + 1;
         end if;
      end if;
   end process;
 
divisor2: process(clk,rst)
   begin
      if (rst='1') then
         temp2 <= '0';
         cnt2 <= conv_std_logic_vector(0,32);
      elsif(clk'event and clk='1') then
         if (cnt2=conv_std_logic_vector(125000,32)) then
            temp2 <= not temp2;
            cnt2 <= conv_std_logic_vector(0,32);
         else
            cnt2 <= cnt2 + 1;
         end if;
      end if;
   end process;
 
contador1: process(temp1,rst)
   begin
           if (rst='1') then
                   contU <= conv_std_logic_vector(0,4);
                elsif(temp1'event and temp1='1') then
                   if contU < 9 then
                           contU <= contU + 1;
                                p1 <= '0';
                        elsif contU = 9 then
                           contU <= conv_std_logic_vector(0,4);
                                p1 <= '1';
                        end if;
                end if;
        end process;
 
contador2: process(p1,rst)
   begin
           if (rst='1') then
                   contD <= conv_std_logic_vector(0,4);
                elsif(p1'event and p1='1') then
                   if contD < 9 then
                           contD <= contD + 1;
                                p2 <= '0';
                        elsif contD = 9 then
                           contD <= conv_std_logic_vector(0,4);
                                p2 <= '1';
                        end if;
                end if;
        end process;
 
contador3: process(p2,rst)
   begin
           if (rst='1') then
                   contC <= conv_std_logic_vector(0,4);
                elsif(p2'event and p2='1') then
                   if contC < 9 then
                           contC <= contC + 1;
                                p3 <= '0';
                        elsif contC = 9 then
                           contC <= conv_std_logic_vector(0,4);
                                p3 <= '1';
                        end if;
                end if;
        end process;
 
BD: process(temp2,rst)
   begin
           if (rst='1') then
                   barrido <= conv_std_logic_vector(0,3);
                        barr <= conv_std_logic_vector(0,3);
                        state <= state0;
                elsif(temp2'event and temp2='1') then
                   case state is
                           when state0 =>
                                   barrido <= "110";
                                        barr <= "110";
                                   state <= state1;
                                when state1 =>
                                   barrido <= "101";
                                        barr <= "101";
                                        state <= state2;
                                when state2 =>
                                   barrido <= "011";
                                        barr <= "011";
                                        state <= state0;
                        end case;
                end if;
        end process;
 
--MUX
 
   MUX <= contU when barr = "110" else
               contD when barr = "101" else
                         contC when barr = "011";
 
--DECO
 
        DECO <= "1000000" when mux = "0000" else
                "1111001" when mux = "0001" else
                          "0100100" when mux = "0010" else
                          "0110000" when mux = "0011" else
                          "0011001" when mux = "0100" else
                          "0010010" when mux = "0101" else
                          "0000010" when mux = "0110" else
                          "1111000" when mux = "0111" else
                          "0000000" when mux = "1000" else
                          "0011000" when mux = "1001" else
                          "0000110";
 
--AP
   AP <= '1';
end cont;

Line No.	Rev	Author	Line
1	3	progman32	`library ieee;`
2			`use ieee.std_logic_1164.all;`
3			`use ieee.std_logic_arith.all;`
4			`use ieee.std_logic_unsigned.all;`
5
6			`entity contador is port(`
7			`clk, rst: in std_logic;`
8			`DECO: out std_logic_vector(6 downto 0);`
9			`AP: out std_logic;`
10			`barrido: out std_logic_vector(2 downto 0));`
11			`end contador;`
12
13			`architecture cont of contador is`
14			`type states is (state0, state1, state2);`
15			`signal state: states;`
16			`signal cnt1, cnt2: std_logic_vector(31 downto 0);`
17			`signal contU, contD, contC: std_logic_vector(3 downto 0);`
18			`signal temp1, temp2: std_logic;`
19			`signal p1, p2, p3: std_logic;`
20			`signal MUX: std_logic_vector(3 downto 0);`
21			`signal barr: std_logic_vector(2 downto 0);`
22			`begin`
23
24			`divisor1: process(clk,rst)`
25			`begin`
26			`if (rst='1') then`
27			`temp1 <= '0';`
28			`cnt1 <= conv_std_logic_vector(0,32);`
29			`elsif(clk'event and clk='1') then`
30			`if (cnt1=conv_std_logic_vector(25000000,32)) then`
31			`temp1 <= not temp1;`
32			`cnt1 <= conv_std_logic_vector(0,32);`
33			`else`
34			`cnt1 <= cnt1 + 1;`
35			`end if;`
36			`end if;`
37			`end process;`
38
39			`divisor2: process(clk,rst)`
40			`begin`
41			`if (rst='1') then`
42			`temp2 <= '0';`
43			`cnt2 <= conv_std_logic_vector(0,32);`
44			`elsif(clk'event and clk='1') then`
45			`if (cnt2=conv_std_logic_vector(125000,32)) then`
46			`temp2 <= not temp2;`
47			`cnt2 <= conv_std_logic_vector(0,32);`
48			`else`
49			`cnt2 <= cnt2 + 1;`
50			`end if;`
51			`end if;`
52			`end process;`
53
54			`contador1: process(temp1,rst)`
55			`begin`
56			`if (rst='1') then`
57			`contU <= conv_std_logic_vector(0,4);`
58			`elsif(temp1'event and temp1='1') then`
59			`if contU < 9 then`
60			`contU <= contU + 1;`
61			`p1 <= '0';`
62			`elsif contU = 9 then`
63			`contU <= conv_std_logic_vector(0,4);`
64			`p1 <= '1';`
65			`end if;`
66			`end if;`
67			`end process;`
68
69			`contador2: process(p1,rst)`
70			`begin`
71			`if (rst='1') then`
72			`contD <= conv_std_logic_vector(0,4);`
73			`elsif(p1'event and p1='1') then`
74			`if contD < 9 then`
75			`contD <= contD + 1;`
76			`p2 <= '0';`
77			`elsif contD = 9 then`
78			`contD <= conv_std_logic_vector(0,4);`
79			`p2 <= '1';`
80			`end if;`
81			`end if;`
82			`end process;`
83
84			`contador3: process(p2,rst)`
85			`begin`
86			`if (rst='1') then`
87			`contC <= conv_std_logic_vector(0,4);`
88			`elsif(p2'event and p2='1') then`
89			`if contC < 9 then`
90			`contC <= contC + 1;`
91			`p3 <= '0';`
92			`elsif contC = 9 then`
93			`contC <= conv_std_logic_vector(0,4);`
94			`p3 <= '1';`
95			`end if;`
96			`end if;`
97			`end process;`
98
99			`BD: process(temp2,rst)`
100			`begin`
101			`if (rst='1') then`
102			`barrido <= conv_std_logic_vector(0,3);`
103			`barr <= conv_std_logic_vector(0,3);`
104			`state <= state0;`
105			`elsif(temp2'event and temp2='1') then`
106			`case state is`
107			`when state0 =>`
108			`barrido <= "110";`
109			`barr <= "110";`
110			`state <= state1;`
111			`when state1 =>`
112			`barrido <= "101";`
113			`barr <= "101";`
114			`state <= state2;`
115			`when state2 =>`
116			`barrido <= "011";`
117			`barr <= "011";`
118			`state <= state0;`
119			`end case;`
120			`end if;`
121			`end process;`
122
123			`--MUX`
124
125			`MUX <= contU when barr = "110" else`
126			`contD when barr = "101" else`
127			`contC when barr = "011";`
128
129			`--DECO`
130
131			`DECO <= "1000000" when mux = "0000" else`
132			`"1111001" when mux = "0001" else`
133			`"0100100" when mux = "0010" else`
134			`"0110000" when mux = "0011" else`
135			`"0011001" when mux = "0100" else`
136			`"0010010" when mux = "0101" else`
137			`"0000010" when mux = "0110" else`
138			`"1111000" when mux = "0111" else`
139			`"0000000" when mux = "1000" else`
140			`"0011000" when mux = "1001" else`
141			`"0000110";`
142
143			`--AP`
144			`AP <= '1';`
145			`end cont;`

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[/] [quark/] [trunk/] [05_HDLConstruction/] [01_OldArchitecture_ReferenceOnly/] [contador0-999.vhd] - Blame information for rev 10