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#!/usr/bin/env python3
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###############################################################################
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#
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# Copyright (C) 2015
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# ASTRON (Netherlands Institute for Radio Astronomy)
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# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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#
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# This program is free software: you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation, either version 3 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program. If not, see .
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#
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###############################################################################
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"""
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Purpose:
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. Generate an Altera QSYS file from a base QSYS file and user supplied list of regs.
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Usage:
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. python generate_qsys.py
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"""
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from common import *
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def _to_element_str(reg_name, reg_base_addr):
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"""
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Returns a template XML 'element' filled in with reg_name and reg_base_addr.
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"""
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ELEMENT_TEMPLATE = """
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element HDL_REG_NAME.mem
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{
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datum baseAddress
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{
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value = HDL_REG_BASE_ADDR;
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type = "long";
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}
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datum _sortIndex
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{
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value = "8";
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type = "int";
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}
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datum sopceditor_expanded
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{
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value = "0";
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type = "boolean";
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}
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}
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"""
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return ELEMENT_TEMPLATE.replace('HDL_REG_NAME', reg_name).replace('HDL_REG_BASE_ADDR', str(reg_base_addr))
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def _to_interface_str(reg_name):
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"""
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Returns a template XML 'interface' filled in with reg_name.
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"""
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INTERFACE_TEMPLATE = """
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name="HDL_REG_NAME_reset"
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internal="HDL_REG_NAME.reset"
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type="conduit"
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dir="end" />
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name="HDL_REG_NAME_clk"
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internal="HDL_REG_NAME.clk"
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type="conduit"
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dir="end" />
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name="HDL_REG_NAME_address"
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internal="HDL_REG_NAME.address"
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type="conduit"
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dir="end" />
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name="HDL_REG_NAME_write"
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internal="HDL_REG_NAME.write"
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type="conduit"
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dir="end" />
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name="HDL_REG_NAME_writedata"
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internal="HDL_REG_NAME.writedata"
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type="conduit"
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dir="end" />
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name="HDL_REG_NAME_read"
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internal="HDL_REG_NAME.read"
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type="conduit"
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dir="end" />
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name="HDL_REG_NAME_readdata"
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internal="HDL_REG_NAME.readdata"
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type="conduit"
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dir="end" />
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"""
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return INTERFACE_TEMPLATE.replace('HDL_REG_NAME', reg_name)
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def _append_to_modules_mid_str(modules_mid_str, reg_name, reg_base_addr, reg_end_addr):
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"""
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The modules_mid section contains one line (dataSlaveMapParam) for all start- and end addresses.
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Append the start and end address of our register to this line.
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"""
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DATASLAVEMAPPARAM_TEMPLATE = ""
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return modules_mid_str + DATASLAVEMAPPARAM_TEMPLATE.replace('HDL_REG_NAME', reg_name).replace('HDL_REG_BASE_ADDR', str(reg_base_addr)).replace('HDL_REG_END_ADDR', str(reg_end_addr))
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def _to_module_str(reg_name, reg_addr_w):
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"""
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Returns a template XML 'module' filled in with reg_name and reg_addr_w.
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"""
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MODULE_TEMPLATE = """
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"""
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return MODULE_TEMPLATE.replace('HDL_REG_NAME', reg_name).replace('HDL_REG_ADDR_W', str(reg_addr_w))
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def _to_connection_str(reg_name, reg_base_addr):
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"""
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Returns a template XML 'connection' filled in with reg_name and reg_base_addr.
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"""
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CONNECTION_TEMPLATE = """
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kind="reset"
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version="11.1"
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start="cpu_0.jtag_debug_module_reset"
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end="HDL_REG_NAME.system_reset" />
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kind="avalon"
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version="11.1"
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start="cpu_0.data_master"
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end="HDL_REG_NAME.mem">
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kind="reset"
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version="11.1"
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start="clk_input.clk_reset"
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end="HDL_REG_NAME.system_reset" />
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kind="clock"
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version="11.1"
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start="clk_input.clk"
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end="HDL_REG_NAME.system" />
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"""
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return CONNECTION_TEMPLATE.replace('HDL_REG_NAME', reg_name).replace('HDL_REG_BASE_ADDR', str(reg_base_addr))
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def generate_qsys(input_qsys, regs, output_filename):
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"""
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Creates an XML QSYS file (output_filename) from a base QSYS and a user-supplied list of registers to add (regs).
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. regs = [ (reg_name, reg_base_addr, reg_span), .. ]
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"""
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# Read the base QSYS contents into a string
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with open (input_qsys, "r") as base_qsys_file:
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data=base_qsys_file.read()
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# We'll split the base QSYS string up in 5 sections.
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# . Note that string.split() throws away the delimiter so we'll restore those later.
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elements = data.split(']]>', 1)[0]
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parameters = data.split(']]>', 1)[1].split('', 1)[0]
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interfaces = data.split(']]>', 1)[1].split('', 1)[1].split('
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modules_head = data.split(']]>', 1)[1].split('', 1)[1].split('')[0]
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modules_mid = data.split(']]>', 1)[1].split('', 1)[1].split('')[1].split(']]>',1)[0]
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modules_tail = data.split(']]>', 1)[1].split('', 1)[1].split('')[1].split(']]>',1)[1]
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connections = data.split(']]>', 1)[1].split('', 1)[1].split('
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# Now we'll append our own XML strings to each section.
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for reg_name, reg_base_addr, reg_addr_w in regs:
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# Determine the end address of this register
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reg_span = ceil_log2(reg_addr_w)
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reg_end_addr = reg_base_addr + reg_span
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# Add strings to the sections
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elements += _to_element_str(reg_name, reg_base_addr)
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parameters = parameters
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interfaces += _to_interface_str(reg_name)
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modules_head = modules_head
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modules_mid = _append_to_modules_mid_str(modules_mid, reg_name, reg_base_addr, reg_end_addr)
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modules_tail += _to_module_str(reg_name, reg_addr_w)
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connections += _to_connection_str(reg_name, reg_base_addr)
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# Re-assemble the sections into one string (add the delimiters that were thrown away by split())
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qsys_str = elements + \
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']]>\n' + \
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parameters + \
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'\n' + \
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interfaces + \
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'
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modules_head + \
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'"dataSlaveMapParam">' + \
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modules_mid + \
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']]>\n' + \
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modules_tail + \
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'
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connections + \
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'\n'
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# Write the QSYS string to the output_file.
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output_file = open(output_filename, "w")
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output_file.write(qsys_str)
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output_file.close()
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################################################################################
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# Example main on execution of this file
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################################################################################
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if __name__ == '__main__':
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base_qsys_path = 'qsys_input.qsys'
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regs = [('reg_my_peripheral', 16384, 3), ('reg_another_peripheral', 17152, 6)]
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generate_qsys(base_qsys_path, regs, 'qsys_generated.qsys')
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