URL https://opencores.org/ocsvn/ram_wb/ram_wb/trunk

Subversion Repositories ram_wb

[/] [ram_wb/] [trunk/] [rtl/] [verilog/] [ram_wb_defines.v] - Blame information for rev 6

Line No.	Rev	Author	Line
1	2	unneback	`define RAM_WB_ADR_WIDTH 12
2			`define RAM_WB_MEM_SIZE 4096
3			`define RAM_WB_DAT_SIZE 32