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1 3 robfinch 
// ============================================================================
2 
// (C) 2012 Robert Finch
3 
// All Rights Reserved.
4 
// robfinch<remove>@opencores.org
5 
//
6 
// Raptor64.v
7 
//  - 64 bit CPU
8 
//
9 
// This source file is free software: you can redistribute it and/or modify
10 
// it under the terms of the GNU Lesser General Public License as published
11 
// by the Free Software Foundation, either version 3 of the License, or
12 
// (at your option) any later version.
13 
//
14 
// This source file is distributed in the hope that it will be useful,
15 
// but WITHOUT ANY WARRANTY; without even the implied warranty of
16 
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17 
// GNU General Public License for more details.
18 
//
19 
// You should have received a copy of the GNU General Public License
20 
// along with this program.  If not, see <http://www.gnu.org/licenses/>.
21 
//
22 
// ============================================================================
23 
//
24 
`define RESET_VECTOR    64'hFFFF_FFFF_FFFF_FFF0
25 
`define NMI_VECTOR              64'hFFFF_FFFF_FFFF_FFE0
26 
`define IRQ_VECTOR              64'hFFFF_FFFF_FFFF_FFD0
27 
`define TRAP_VECTOR             64'h0000_0000_0000_0000
28 
 
29 
`define TLBMissPage             52'hFFFF_FFFF_FFFF_F
30 
`define ITLB_MissHandler        64'hFFFF_FFFF_FFFF_FFC0
31 
 
32 
`define EX_NON          8'd0
33 
`define EX_RST          8'd1
34 
`define EX_NMI          8'd2
35 
`define EX_IRQ          8'd3
36 
`define EX_OFL          8'd16   // overflow
37 
`define EX_DBZ          8'd17   // divide by zero
38 
`define EX_TLBI         8'd19   // TLB exception - ifetch
39 
 
40 
`define EXCEPT_Int              5'd00
41 
`define EXCEPT_Mod              5'd01   // TLB modification
42 
`define EXCEPT_TLBL             5'd02   // TLB exception - load or ifetch
43 
`define EXCEPT_TLBS             5'd03   // TLB exception - store
44 
`define EXCEPT_AdEL             5'd04   // Address error - load or ifetch
45 
`define EXCEPT_AdES             5'd05   // Address error - store
46 
`define EXCEPT_IBE              5'd06   // Bus Error - instruction fetch
47 
`define EXCEPT_DBE              5'd07   // Bus Error - load or store
48 
`define EXCEPT_Sys              5'd08
49 
`define EXCEPT_Bp               5'd09
50 
`define EXCEPT_RI               5'd10   // reserved instruction
51 
`define EXCEPT_CpU              5'd11   // Coprocessor unusable
52 
`define EXCEPT_Ov               5'd12   // Integer Overflow
53 
`define EXCEPT_Tr               5'd13   // Trap exception
54 
// 14-22 Reserved
55 
`define EXCEPT_WATCH    5'd23
56 
`define EXCEPT_MCheck   5'd24   // Machine check
57 
// 25-31 Reserved
58 
 
59 
 
60 
`define MISC    7'd0
61 
`define         BRK             7'd0
62 
`define         IRQ             7'd1
63 
`define         IRET    7'd32
64 
`define         WAIT    7'd40
65 
`define     TLBR        7'd50
66 
`define     TLBWI       7'd51
67 
`define     TLBWR       7'd52
68 
`define         CLI             7'd64
69 
`define         SEI             7'd65
70 
`define R               7'd1
71 
`define         COM             7'd4
72 
`define         NOT             7'd5
73 
`define         NEG             7'd6
74 
`define         ABS             7'd7
75 
`define         SWAP    7'd13
76 
`define         CTLZ    7'd16
77 
`define         CTLO    7'd17
78 
`define         CTPOP   7'd18
79 
`define         SEXT8   7'd19
80 
`define         SEXT16  7'd20
81 
`define         SEXT32  7'd21
82 
`define         SQRT    7'd24
83 
`define         REDOR   7'd30
84 
`define         REDAND  7'd31
85 
`define     MFSPR       7'd40
86 
`define     MTSPR       7'd41
87 
`define         TLBIndex        5'd01
88 
`define         TLBRandom               5'd02
89 
`define         PageTableAddr   5'd04
90 
`define         BadVAddr        5'd08
91 
`define         TLBPhysPage             5'd10
92 
`define         TLBVirtPage             5'd11
93 
`define                 TLBPageMask             5'd12
94 
`define                 TLBASID                 5'd13
95 
`define         ASID                    5'd14
96 
`define                 Wired                   5'd15
97 
`define         EP0             5'd16
98 
`define         EP1             5'd17
99 
`define         EP2             5'd18
100 
`define         EP3             5'd19
101 5 robfinch 
`define         AXC             5'd20
102 3 robfinch 
`define         MFTICK  7'd56
103 
`define         MFEPC   7'd57
104 
`define         MFTBA   7'd58
105 
`define         MTTBA   7'd59
106 
`define         MTREGSET        7'd60
107 
`define         MFREGSET        7'd61
108 
`define RR      7'd2
109 
`define         ADD             7'd4
110 
`define         SUB             7'd5
111 
`define         CMP             7'd6
112 
`define         CMPU    7'd7
113 
`define         AND             7'd8
114 
`define         OR              7'd9
115 
`define         XOR             7'd10
116 
`define         ANDC    7'd11
117 
`define         NAND    7'd12
118 
`define         NOR             7'd13
119 5 robfinch 
`define         XNOR    7'd14
120 3 robfinch 
`define         MIN             7'd20
121 
`define         MAX             7'd21
122 
`define         MULU    7'd24
123 
`define         MULS    7'd25
124 
`define         DIVU    7'd26
125 
`define         DIVS    7'd27
126 
`define         MOD             7'd28
127 
`define         MOVZ    7'd30
128 
`define         MOVNZ   7'd31
129 
 
130 
`define         ASL             7'd40
131 
`define         LSR             7'd41
132 
`define         ROL             7'd42
133 
`define         ROR             7'd43
134 
`define         ASR             7'd44
135 
`define         ROLAM   7'd45
136 
 
137 
`define         NOP             7'd60
138 
 
139 
`define         BLT             7'd80
140 
`define         BGE             7'd81
141 
`define         BLE             7'd82
142 
`define         BGT             7'd83
143 
`define         BLTU    7'd84
144 
`define         BGEU    7'd85
145 
`define         BLEU    7'd86
146 
`define         BGTU    7'd87
147 
`define         BEQ             7'd88
148 
`define         BNE             7'd89
149 
`define         BRA             7'd90
150 
`define         BRN             7'd91
151 
`define         BAND    7'd92
152 
`define         BOR             7'd93
153 
 
154 
`define         SLT             7'd96
155 
`define         SLE             7'd97
156 
`define         SGT             7'd98
157 
`define         SGE             7'd99
158 5 robfinch 
`define         SLTU    7'd100
159 
`define         SLEU    7'd101
160 
`define         SGTU    7'd102
161 
`define         SGEU    7'd103
162 3 robfinch 
`define         SEQ             7'd104
163 
`define         SNE             7'd105
164 
 
165 
`define     BCD_ADD     7'd110
166 
`define     BCD_SUB 7'd111
167 
 
168 
`define SHFTI   7'd3
169 
`define ASLI            7'd0
170 
`define LSRI            7'd1
171 
`define ROLI            7'd2
172 
`define ASRI            7'd3
173 
`define RORI            7'd4
174 
`define ROLAMI          7'd5
175 
`define BFINS           7'd8
176 
`define BFSET           7'd9
177 
`define BFCLR           7'd10
178 
`define BFCHG           7'd11
179 
 
180 
`define ADDI    7'd4
181 
`define SUBI    7'd5
182 
`define CMPI    7'd6
183 
`define CMPUI   7'd7
184 
`define ANDI    7'd8
185 
`define ORI             7'd9
186 
`define XORI    7'd10
187 
 
188 
`define MULUI   7'd12
189 
`define MULSI   7'd13
190 
`define DIVUI   7'd14
191 
`define DIVSI   7'd15
192 
 
193 
`define BRr             7'd16
194 
`define         BEQZ    5'd0
195 
`define         BNEZ    5'd1
196 
`define         BLTZ    5'd2
197 
`define         BLEZ    5'd3
198 
`define         BGTZ    5'd4
199 
`define         BGEZ    5'd5
200 
`define         BRAZ    5'd6
201 
`define         BNR             5'd7
202 
`define         BEQZD   5'd8
203 
`define         BNEZD   5'd9
204 
`define         BLTZD   5'd10
205 
`define         BLEZD   5'd11
206 
`define         BGTZD   5'd12
207 
`define         BGEZD   5'd13
208 
`define         BRAD    5'd14
209 
`define         BEQZR   5'd16
210 
`define         BNEZR   5'd17
211 
`define         BLTZR   5'd18
212 
`define         BLEZR   5'd19
213 
`define         BGTZR   5'd20
214 
`define         BGEZR   5'd21
215 
`define         BEQZRD  5'd24
216 
`define         BNEZRD  5'd25
217 
`define         BLTZRD  5'd26
218 
`define         BLEZRD  5'd27
219 
`define         BGTZRD  5'd28
220 
`define         BGEZRD  5'd29
221 
`define TRAPcc  7'd17
222 
`define         TEQ             7'd0
223 
`define         TNE             7'd1
224 
`define         TLT             7'd2
225 
`define         TLE             7'd3
226 
`define         TGT             7'd4
227 
`define         TGE             7'd5
228 
`define         TLO             7'd6
229 
`define         TLS             7'd7
230 
`define         THI             7'd8
231 
`define         THS             7'd9
232 
`define         TRAP    7'd10
233 
`define         TRN             7'd11
234 
`define TRAPcci 7'd18
235 
`define         TEQI    5'd0
236 
`define         TNEI    5'd1
237 
`define         TLTI    5'd2
238 
`define         TLEI    5'd3
239 
`define         TGTI    5'd4
240 
`define         TGEI    5'd5
241 
`define         TLOI    5'd6
242 
`define         TLSI    5'd7
243 
`define         THII    5'd8
244 
`define         THSI    5'd9
245 
`define         TRAI    5'd10
246 
`define         TRNI    5'd11
247 
`define CALL    7'd24
248 
`define JMP             7'd25
249 
`define JAL             7'd26
250 
`define RET             7'd27
251 
 
252 
`define LB              7'd32
253 
`define LC              7'd33
254 
`define LH              7'd34
255 
`define LW              7'd35
256 
`define LP              7'd36
257 
`define LBU             7'd37
258 
`define LCU             7'd38
259 
`define LHU             7'd39
260 
`define LSH             7'd40
261 
`define LSW             7'd41
262 
`define LF              7'd42
263 
`define LFD             7'd43
264 
`define LFP             7'd44
265 
`define LFDP    7'd45
266 
`define LWR             7'd46
267 
`define LDONE   7'd47
268 
 
269 
`define SB              7'd48
270 
`define SC              7'd49
271 
`define SH              7'd50
272 
`define SW              7'd51
273 
`define SP              7'd52
274 
`define SSH             7'd56
275 
`define SSW             7'd57
276 
`define SF              7'd58
277 
`define SFD             7'd59
278 
`define SFP             7'd60
279 
`define SFDP    7'd61
280 
`define SWC             7'd62
281 
 
282 
`define INB             7'd64
283 
`define INCH    7'd65
284 
`define INH             7'd66
285 
`define INW             7'd67
286 
`define OUTB    7'd72
287 
`define OUTC    7'd73
288 
`define OUTH    7'd74
289 
`define OUTW    7'd75
290 
 
291 
`define BEQI    7'd80
292 
`define BNEI    7'd81
293 
`define BLTI    7'd82
294 
`define BLEI    7'd83
295 
`define BGTI    7'd84
296 
`define BGEI    7'd85
297 
`define BLTUI   7'd86
298 
`define BLEUI   7'd87
299 
`define BGTUI   7'd88
300 
`define BGEUI   7'd89
301 
`define BRAI    7'd90
302 
`define BRNI    7'd91
303 
 
304 
 
305 
`define SLTI    7'd96
306 
`define SLEI    7'd97
307 
`define SGTI    7'd98
308 
`define SGEI    7'd99
309 
`define SLTUI   7'd100
310 
`define SLEUI   7'd101
311 
`define SGTUI   7'd102
312 
`define SGEUI   7'd103
313 
`define SEQI    7'd104
314 
`define SNEI    7'd105
315 
 
316 
`define FPLOO   7'd109
317 
`define FPZL    7'd110
318 
`define NOPI    7'd111
319 
 
320 
`define IMM             3'd7
321 
 
322 
`define NOP_INSN        42'b1101111_000_00000000_00000000_00000000_00000000
323 
 
324 
module Raptor64(rst_i, clk_i, nmi_i, irq_i,
325 
        bte_o, cti_o, cyc_o, stb_o, ack_i, we_o, sel_o, rsv_o, adr_o, dat_i, dat_o, sys_adv, sys_adr,
326 
        cmd_en, cmd_instr, cmd_bl, cmd_byte_addr, cmd_full,
327 
        wr_en, wr_data, wr_mask, wr_full, wr_empty,
328 
        rd_en, rd_data, rd_empty
329 
);
330 
parameter IDLE = 5'd1;
331 
parameter ICACT = 5'd2;
332 
parameter ICACT0 = 5'd3;
333 
parameter ICACT1 = 5'd4;
334 
parameter ICACT2 = 5'd5;
335 
parameter ICACT3 = 5'd6;
336 
parameter ICACT4 = 5'd7;
337 
parameter ICACT5 = 5'd8;
338 
parameter ICACT6 = 5'd9;
339 
parameter ICACT7 = 5'd10;
340 
parameter ICDLY = 5'd11;
341 
parameter DCIDLE = 5'd20;
342 
parameter DCACT = 5'd21;
343 
parameter DCACT0 = 5'd22;
344 
parameter DCACT1 = 5'd23;
345 
parameter DCACT2 = 5'd24;
346 
parameter DCACT3 = 5'd25;
347 
parameter DCACT4 = 5'd26;
348 
parameter DCACT5 = 5'd27;
349 
parameter DCACT6 = 5'd28;
350 
parameter DCACT7 = 5'd29;
351 
parameter DCDLY = 5'd30;
352 
 
353 
input rst_i;
354 
input clk_i;
355 
input nmi_i;
356 
input irq_i;
357 
output [1:0] bte_o;
358 
reg [1:0] bte_o;
359 
output [2:0] cti_o;
360 
reg [2:0] cti_o;
361 
output cyc_o;
362 
reg cyc_o;
363 
output stb_o;
364 
reg stb_o;
365 
input ack_i;
366 
output we_o;
367 
reg we_o;
368 
output [7:0] sel_o;
369 
reg [7:0] sel_o;
370 
output rsv_o;
371 
reg rsv_o;
372 
output [63:0] adr_o;
373 
reg [63:0] adr_o;
374 
input [31:0] dat_i;
375 
output [31:0] dat_o;
376 
reg [31:0] dat_o;
377 
input sys_adv;
378 
input [63:5] sys_adr;
379 
 
380 
output cmd_en;
381 
reg cmd_en;
382 
output [2:0] cmd_instr;
383 
reg [2:0] cmd_instr;
384 
output [5:0] cmd_bl;
385 
reg [5:0] cmd_bl;
386 
output [29:0] cmd_byte_addr;
387 
reg [29:0] cmd_byte_addr;
388 
input cmd_full;
389 
output wr_en;
390 
reg wr_en;
391 
output [31:0] wr_data;
392 
reg [31:0] wr_data;
393 
output [3:0] wr_mask;
394 
reg [3:0] wr_mask;
395 
input wr_full;
396 
input wr_empty;
397 
output rd_en;
398 
reg rd_en;
399 
input [31:0] rd_data;
400 
input rd_empty;
401 
 
402 5 robfinch 
reg resetA;
403 3 robfinch 
reg im;                         // interrupt mask
404 
reg [1:0] rm;            // fp rounding mode
405 
reg [41:0] dIR;
406 
reg [41:0] xIR;
407 
reg [4:0] epcnt;
408 
reg [3:0] dAXC,AXC,xAXC;
409 
reg [31:0] EP [3:0];
410 
reg [63:0] pc [15:0];
411 
wire [63:0] pc_axc = pc[AXC];
412 
reg [63:0] dpc,m1pc,m2pc,m3pc,m4pc,wpc;
413 
reg [63:0] xpc;
414 
reg [63:0] tlbra;                // return address for a TLB exception
415 
reg [8:0] dRa,dRb;
416 
reg [8:0] wRt,mRt,m1Rt,m2Rt,m3Rt,m4Rt,tRt,dRt;
417 
reg [8:0] xRt;
418 
reg [63:0] dImm;
419 
reg [63:0] ea;
420 
reg [63:0] iadr_o;
421 
reg [31:0] idat;
422 
reg [4:0] cstate;
423 5 robfinch 
//reg wr_icache;
424 3 robfinch 
reg dccyc;
425 
wire [63:0] cdat;
426 
reg [63:0] wr_addr;
427 
wire [41:0] insn;
428 
reg [3:0] regset;
429 
wire [63:0] rfoa,rfob;
430 
reg clk_en;
431 
reg cpu_clk_en;
432 
reg StatusEXL;          // 1= in exception processing
433 
reg StatusTLB;          // 1= in TLB miss handling
434 
reg [7:0] ASID;          // address space identifier (process ID)
435 
integer n;
436 
reg [63:13] BadVAddr;
437 
reg [63:13] PageTableAddr;
438 
reg [24:13] TLBPageMask;
439 
reg [63:13] TLBVirtPage;
440 
reg [63:13] TLBPhysPage;
441 
reg [7:0] TLBASID;
442 
reg [3:0] Index;
443 
reg [3:0] Random;
444 
reg [3:0] Wired;
445 
reg [15:0] IMatch,DMatch;
446 
 
447 
//-----------------------------------------------------------------------------
448 
// Instruction TLB
449 
//-----------------------------------------------------------------------------
450 
 
451 
reg [4:0] m;
452 
reg [3:0] i;
453 
reg [24:13] ITLBPageMask [15:0];
454 
reg [63:13] ITLBVirtPage [15:0];
455 
reg [63:13] ITLBPhysPage [15:0];
456 
reg [15:0] ITLBG;
457 
reg [7:0] ITLBASID [15:0];
458 
reg [15:0] ITLBValid;
459 
always @*
460 
for (n = 0; n < 16; n = n + 1)
461 
        IMatch[n] = ((pc_axc[63:13]|ITLBPageMask[n])==(ITLBVirtPage[n]|ITLBPageMask[n])) &&
462 
                                ((ITLBASID[n]==ASID) || ITLBG[n]) &&
463 
                                ITLBValid[n];
464 
always @(IMatch)
465 
if (IMatch[0]) m <= 5'd0;
466 
else if (IMatch[1]) m <= 5'd1;
467 
else if (IMatch[2]) m <= 5'd2;
468 
else if (IMatch[3]) m <= 5'd3;
469 
else if (IMatch[4]) m <= 5'd4;
470 
else if (IMatch[5]) m <= 5'd5;
471 
else if (IMatch[6]) m <= 5'd6;
472 
else if (IMatch[7]) m <= 5'd7;
473 
else if (IMatch[8]) m <= 5'd8;
474 
else if (IMatch[9]) m <= 5'd9;
475 
else if (IMatch[10]) m <= 5'd10;
476 
else if (IMatch[11]) m <= 5'd11;
477 
else if (IMatch[12]) m <= 5'd12;
478 
else if (IMatch[13]) m <= 5'd13;
479 
else if (IMatch[14]) m <= 5'd14;
480 
else if (IMatch[15]) m <= 5'd15;
481 
else m <= 5'd31;
482 
 
483 
wire unmappedArea = pc_axc[63:52]==12'hFFD || pc_axc[63:52]==12'hFFE || pc_axc[63:52]==12'hFFF;
484 
wire [63:0] ppc;
485 
wire ITLBMiss = !unmappedArea & m[4];
486 
 
487 
assign ppc[63:13] = unmappedArea ? pc_axc[63:13] : m[4] ? `TLBMissPage: ITLBPhysPage[m];
488 
assign ppc[12:0] = pc_axc[12:0];
489 
 
490 
//-----------------------------------------------------------------------------
491 
// Data TLB
492 
//-----------------------------------------------------------------------------
493 
 
494 
reg [4:0] q;
495 
reg [24:13] DTLBPageMask [15:0];
496 
reg [63:13] DTLBVirtPage [15:0];
497 
reg [63:13] DTLBPhysPage [15:0];
498 
reg [15:0] DTLBG;
499 
reg [7:0] DTLBASID [15:0];
500 
reg [15:0] DTLBValid;
501 
always @(ea)
502 
for (n = 0; n < 16; n = n + 1)
503 
        DMatch[n] = ((ea[63:13]|DTLBPageMask[n])==(DTLBVirtPage[n]|DTLBPageMask[n])) &&
504 
                                ((DTLBASID[n]==ASID) || DTLBG[n]) &&
505 
                                DTLBValid[n];
506 
always @(DMatch)
507 
if (DMatch[0]) q <= 5'd0;
508 
else if (DMatch[1]) q <= 5'd1;
509 
else if (DMatch[2]) q <= 5'd2;
510 
else if (DMatch[3]) q <= 5'd3;
511 
else if (DMatch[4]) q <= 5'd4;
512 
else if (DMatch[5]) q <= 5'd5;
513 
else if (DMatch[6]) q <= 5'd6;
514 
else if (DMatch[7]) q <= 5'd7;
515 
else if (DMatch[8]) q <= 5'd8;
516 
else if (DMatch[9]) q <= 5'd9;
517 
else if (DMatch[10]) q <= 5'd10;
518 
else if (DMatch[11]) q <= 5'd11;
519 
else if (DMatch[12]) q <= 5'd12;
520 
else if (DMatch[13]) q <= 5'd13;
521 
else if (DMatch[14]) q <= 5'd14;
522 
else if (DMatch[15]) q <= 5'd15;
523 
else q <= 5'd31;
524 
 
525 
wire unmappedDataArea = ea[63:52]==12'hFFD || ea[63:52]==12'hFFE || ea[63:52]==12'hFFF;
526 
wire DTLBMiss = !unmappedDataArea & q[4];
527 
 
528 
wire [63:0] pea;
529 
assign pea[63:13] = unmappedDataArea ? ea[63:13] : q[4] ? `TLBMissPage: DTLBPhysPage[q];
530 
assign pea[12:0] = ea[12:0];
531 
 
532 
//-----------------------------------------------------------------------------
533 
// Clock control
534 
// - reset or NMI reenables the clock
535 
// - this circuit must be under the clk_i domain
536 
//-----------------------------------------------------------------------------
537 
//
538 
BUFGCE u20 (.CE(cpu_clk_en), .I(clk_i), .O(clk) );
539 
 
540 
always @(posedge clk_i)
541 
if (rst_i) begin
542 
        cpu_clk_en <= 1'b1;
543 
end
544 
else begin
545 
        if (nmi_i)
546 
                cpu_clk_en <= 1'b1;
547 
        else
548 
                cpu_clk_en <= clk_en;
549 
end
550 
 
551 
//-----------------------------------------------------------------------------
552 
// Instruction Cache
553 
// 8kB
554 5 robfinch 
//
555 3 robfinch 
//-----------------------------------------------------------------------------
556 
reg icaccess;
557 5 robfinch 
wire wr_icache = !rd_empty & icaccess;
558 3 robfinch 
 
559 
Raptor64_icache_ram_x32 u1
560 
(
561 
        .clk(clk),
562 5 robfinch 
        .wr(wr_icache),
563 
        .adr_i(iadr_o[12:0]),
564 
        .dat_i(rd_data),
565 
        .pc(pc_axc),
566 3 robfinch 
        .insn(insn)
567 
);
568 
 
569 
reg [63:13] tmem [127:0];
570 
reg [127:0] tvalid;
571 
 
572 
initial begin
573 
        for (n=0; n < 128; n = n + 1)
574 
                tmem[n] = 0;
575 
        for (n=0; n < 128; n = n + 1)
576 
                tvalid[n] = 0;
577 
end
578 
 
579 
wire [64:13] tgout;
580 5 robfinch 
assign tgout = {tvalid[pc_axc[12:6]],tmem[pc_axc[12:6]]};
581 3 robfinch 
assign ihit = (tgout=={1'b1,ppc[63:13]});
582 
 
583 
 
584 
//-----------------------------------------------------------------------------
585 
// Data Cache
586 5 robfinch 
// No-allocate on write
587 3 robfinch 
//-----------------------------------------------------------------------------
588 
reg dcaccess;
589 
wire dhit;
590 5 robfinch 
wire [13:0] dtign;
591 3 robfinch 
wire [64:14] dtgout;
592 
reg wrhit;
593 
reg [7:0] dsel_o;
594 
reg [63:0] dadr_o;
595 
reg [31:0] ddat;
596 
reg wr_dcache;
597 
 
598 
// cache RAM 16Kb
599 
Raptor64_dcache_ram u10
600 
(
601 
        .clk(clk),
602 
        .wr(dcaccess ? wr_dcache : wrhit ? wr_en : 1'b0),
603 
        .sel(dcaccess ? 4'b1111 : wrhit ? ~wr_mask : 4'b0000),
604 
        .wadr(dcaccess ? dadr_o[13:2] : wr_addr[13:2]),
605 
        .i(dcaccess ? ddat : wr_data),
606 
        .radr(pea[13:3]),
607 
        .o(cdat)
608 
);
609 
 
610 
// tag ram
611 
syncRam512x64_1rw1r u11
612 
(
613 
        .wrst(1'b0),
614 
        .wclk(clk),
615 5 robfinch 
        .wce(dadr_o[4:2]==3'b111),
616 3 robfinch 
        .we(wr_dcache),
617 
        .wadr(dadr_o[13:5]),
618 
        .i({14'h3FFF,dadr_o[63:14]}),
619 
        .wo(),
620 
 
621 
        .rrst(1'b0),
622 
        .rclk(~clk),
623 
        .rce(1'b1),
624 
        .radr(pea[13:5]),
625 
        .ro({dtign,dtgout})
626 
);
627 
 
628 
assign dhit = (dtgout=={1'b1,pea[63:14]});
629 
 
630 
//-----------------------------------------------------------------------------
631 
//-----------------------------------------------------------------------------
632 
 
633 
reg [64:0] xData;
634 
wire xisCacheElement = xData[63:52] != 12'hFFD;
635 
reg m1IsCacheElement;
636 
 
637 
reg nopI;
638 
wire [6:0] dFunc = dIR[6:0];
639 
wire [6:0] xFunc = xIR[6:0];
640 
wire [6:0] xOpcode = xIR[41:35];
641 
wire [6:0] dOpcode = dIR[41:35];
642 
reg [6:0] m1Opcode,m2Opcode,m3Opcode,m4Opcode;
643 
reg [6:0] m1Func,m2Func,m3Func,m4Func;
644 
reg [63:0] m1Data,m2Data,m3Data,m4Data,wData,tData;
645 
reg [63:0] m2Addr,m3Addr,m4Addr;
646 
reg [63:0] tick;
647 
reg [63:0] tba;
648 
reg [63:0] exception_address,ipc;
649 
reg [63:0] a,b,imm;
650 
reg prev_ihit;
651 
reg rsf;
652 
reg [63:5] resv_address;
653 
reg dirqf,rirqf,m1irqf,m2irqf,m3irqf,m4irqf,wirqf,tirqf;
654 
reg xirqf;
655 
reg [7:0] dextype,m1extype,m2extype,m3extype,m4extype,wextype,textype,exception_type;
656 
reg [7:0] xextype;
657 
wire advanceX_edge;
658 
reg takb;
659 
 
660 
wire [127:0] mult_out;
661 
wire [63:0] sqrt_out;
662 
wire [63:0] div_q;
663 
wire [63:0] div_r;
664 
wire sqrt_done,mult_done,div_done;
665 
wire isSqrt = xOpcode==`R && xFunc==`SQRT;
666 
wire [7:0] bcdaddo,bcdsubo;
667 
 
668 
BCDAdd u40(.ci(1'b0),.a(a[7:0]),.b(b[7:0]),.o(bcdaddo),.c());
669 
BCDSub u41(.ci(1'b0),.a(a[7:0]),.b(b[7:0]),.o(bcdsubo),.c());
670 
 
671 
isqrt #(64) u14
672 
(
673 
        .rst(rst_i),
674 
        .clk(clk),
675 
        .ce(1'b1),
676 
        .ld(isSqrt),
677 
        .a(a),
678 
        .o(sqrt_out),
679 
        .done(sqrt_done)
680 
);
681 
 
682 
wire isMulu = xOpcode==`RR && xFunc==`MULU;
683 
wire isMuls = (xOpcode==`RR && xFunc==`MULS) || xOpcode==`MULSI;
684 
wire isMuli = xOpcode==`MULSI || xOpcode==`MULUI;
685 
wire isMult = xOpcode==`MULSI || xOpcode==`MULUI || (xOpcode==`RR && (xFunc==`MULS || xFunc==`MULU));
686 
wire isDivu = xOpcode==`RR && xFunc==`DIVU;
687 
wire isDivs = (xOpcode==`RR && xFunc==`DIVS) || xOpcode==`DIVSI;
688 
wire isDivi = xOpcode==`DIVSI || xOpcode==`DIVUI;
689 
wire isDiv = xOpcode==`DIVSI || xOpcode==`DIVUI || (xOpcode==`RR && (xFunc==`DIVS || xFunc==`DIVU));
690 
 
691 
wire disRRShift = dOpcode==`RR && (
692 
        dFunc==`ASL || dFunc==`ROL || dFunc==`ASR ||
693 
        dFunc==`LSR || dFunc==`ROR || dFunc==`ROLAM
694 
        );
695 
wire disRightShift = dOpcode==`RR && (
696 
        dFunc==`ASR || dFunc==`LSR || dFunc==`ROR
697 
        );
698 
 
699 
Raptor64Mult u18
700 
(
701 
        .rst(rst_i),
702 
        .clk(clk),
703 
        .ld(isMult),
704 
        .sgn(isMuls),
705 
        .isMuli(isMuli),
706 
        .a(a),
707 
        .b(b),
708 
        .imm(imm),
709 
        .o(mult_out),
710 
        .done(mult_done)
711 
);
712 
 
713 
Raptor64Div u19
714 
(
715 
        .rst(rst_i),
716 
        .clk(clk),
717 
        .ld(isDiv),
718 
        .sgn(isDivs),
719 
        .isDivi(isDivi),
720 
        .a(a),
721 
        .b(b),
722 
        .imm(imm),
723 
        .qo(div_q),
724 
        .ro(div_r),
725 
        .dvByZr(),
726 
        .done(div_done)
727 
);
728 
 
729 
wire [63:0] fpZLOut;
730 
wire [63:0] fpLooOut;
731 
wire fpLooDone;
732 
 
733 
fpZLUnit #(64) u30
734 
(
735 
        .op(xFunc[5:0]),
736 
        .a(a),
737 
        .b(b),  // for fcmp
738 
        .o(fpZLOut),
739 
        .nanx()
740 
);
741 
 
742 
fpLOOUnit #(64) u31
743 
(
744 
        .clk(clk),
745 
        .ce(1'b1),
746 
        .rm(rm),
747 
        .op(xFunc[5:0]),
748 
        .a(a),
749 
        .o(fpLooOut),
750 
        .done(fpLooDone)
751 
);
752 
 
753 
function [2:0] popcnt6;
754 
input [5:0] a;
755 
begin
756 
case(a)
757 
6'b000000:      popcnt6 = 3'd0;
758 
6'b000001:      popcnt6 = 3'd1;
759 
6'b000010:      popcnt6 = 3'd1;
760 
6'b000011:      popcnt6 = 3'd2;
761 
6'b000100:      popcnt6 = 3'd1;
762 
6'b000101:      popcnt6 = 3'd2;
763 
6'b000110:      popcnt6 = 3'd2;
764 
6'b000111:      popcnt6 = 3'd3;
765 
6'b001000:      popcnt6 = 3'd1;
766 
6'b001001:      popcnt6 = 3'd2;
767 
6'b001010:      popcnt6 = 3'd2;
768 
6'b001011:      popcnt6 = 3'd3;
769 
6'b001100:      popcnt6 = 3'd2;
770 
6'b001101:      popcnt6 = 3'd3;
771 
6'b001110:      popcnt6 = 3'd3;
772 
6'b001111:  popcnt6 = 3'd4;
773 
6'b010000:      popcnt6 = 3'd1;
774 
6'b010001:      popcnt6 = 3'd2;
775 
6'b010010:  popcnt6 = 3'd2;
776 
6'b010011:      popcnt6 = 3'd3;
777 
6'b010100:  popcnt6 = 3'd2;
778 
6'b010101:  popcnt6 = 3'd3;
779 
6'b010110:  popcnt6 = 3'd3;
780 
6'b010111:      popcnt6 = 3'd4;
781 
6'b011000:      popcnt6 = 3'd2;
782 
6'b011001:      popcnt6 = 3'd3;
783 
6'b011010:      popcnt6 = 3'd3;
784 
6'b011011:      popcnt6 = 3'd4;
785 
6'b011100:      popcnt6 = 3'd3;
786 
6'b011101:      popcnt6 = 3'd4;
787 
6'b011110:      popcnt6 = 3'd4;
788 
6'b011111:      popcnt6 = 3'd5;
789 
6'b100000:      popcnt6 = 3'd1;
790 
6'b100001:      popcnt6 = 3'd2;
791 
6'b100010:      popcnt6 = 3'd2;
792 
6'b100011:      popcnt6 = 3'd3;
793 
6'b100100:      popcnt6 = 3'd2;
794 
6'b100101:      popcnt6 = 3'd3;
795 
6'b100110:      popcnt6 = 3'd3;
796 
6'b100111:      popcnt6 = 3'd4;
797 
6'b101000:      popcnt6 = 3'd2;
798 
6'b101001:      popcnt6 = 3'd3;
799 
6'b101010:      popcnt6 = 3'd3;
800 
6'b101011:      popcnt6 = 3'd4;
801 
6'b101100:      popcnt6 = 3'd3;
802 
6'b101101:      popcnt6 = 3'd4;
803 
6'b101110:      popcnt6 = 3'd4;
804 
6'b101111:      popcnt6 = 3'd5;
805 
6'b110000:      popcnt6 = 3'd2;
806 
6'b110001:      popcnt6 = 3'd3;
807 
6'b110010:      popcnt6 = 3'd3;
808 
6'b110011:      popcnt6 = 3'd4;
809 
6'b110100:      popcnt6 = 3'd3;
810 
6'b110101:      popcnt6 = 3'd4;
811 
6'b110110:      popcnt6 = 3'd4;
812 
6'b110111:      popcnt6 = 3'd5;
813 
6'b111000:      popcnt6 = 3'd3;
814 
6'b111001:      popcnt6 = 3'd4;
815 
6'b111010:      popcnt6 = 3'd4;
816 
6'b111011:      popcnt6 = 3'd5;
817 
6'b111100:      popcnt6 = 3'd4;
818 
6'b111101:      popcnt6 = 3'd5;
819 
6'b111110:      popcnt6 = 3'd5;
820 
6'b111111:      popcnt6 = 3'd6;
821 
endcase
822 
end
823 
endfunction
824 
 
825 
//---------------------------------------------------------
826 
// Evaluate branch conditions.
827 
//---------------------------------------------------------
828 
wire signed [63:0] as = a;
829 
wire signed [63:0] bs = b;
830 
wire signed [63:0] imms = imm;
831 
wire aeqz = a==64'd0;
832 
wire beqz = b==64'd0;
833 
wire immeqz = imm==64'd0;
834 
wire eq = a==b;
835 
wire eqi = a==imm;
836 
wire lt = as < bs;
837 
wire lti = as < imms;
838 
wire ltu = a < b;
839 
wire ltui = a < imm;
840 
 
841 
always @(xOpcode or xFunc or a or eq or eqi or lt or lti or ltu or ltui or aeqz or beqz or rsf or xIR)
842 
case (xOpcode)
843 
`RR:
844 
        case(xFunc)
845 
        `BRA:   takb = 1'b1;
846 
        `BRN:   takb = 1'b0;
847 
        `BEQ:   takb = eq;
848 
        `BNE:   takb = !eq;
849 
        `BLT:   takb = lt;
850 
        `BLE:   takb = lt|eq;
851 
        `BGT:   takb = !(lt|eq);
852 
        `BGE:   takb = !lt;
853 
        `BLTU:  takb = ltu;
854 
        `BLEU:  takb = ltu|eq;
855 
        `BGTU:  takb = !(ltu|eq);
856 
        `BGEU:  takb = !ltu;
857 
        `BOR:   takb = !aeqz || !beqz;
858 
        `BAND:  takb = !aeqz && !beqz;
859 
        default:        takb = 1'b0;
860 
        endcase
861 
`BRAI:  takb = 1'b1;
862 
`BRNI:  takb = 1'b0;
863 
`BEQI:  takb = eqi;
864 
`BNEI:  takb = !eqi;
865 
`BLTI:  takb = lti;
866 
`BLEI:  takb = lti|eqi;
867 
`BGTI:  takb = !(lti|eqi);
868 
`BGEI:  takb = !lti;
869 
`BLTUI: takb = ltui;
870 
`BLEUI: takb = ltui|eqi;
871 
`BGTUI: takb = !(ltui|eqi);
872 
`BGEUI: takb = !ltui;
873 
`TRAPcc:
874 
        case(xFunc)
875 
        `TEQ:   takb = eq;
876 
        `TNE:   takb = !eq;
877 
        `TLT:   takb = lt;
878 
        `TLE:   takb = lt|eq;
879 
        `TGT:   takb = !(lt|eq);
880 
        `TGE:   takb = !lt;
881 
        `TLO:   takb = ltu;
882 
        `TLS:   takb = ltu|eq;
883 
        `THI:   takb = !(ltu|eq);
884 
        `THS:   takb = !ltu;
885 
        default:        takb = 1'b0;
886 
        endcase
887 
`TRAPcci:
888 
        case(xIR[29:25])
889 
        `TEQI:  takb = eqi;
890 
        `TNEI:  takb = !eqi;
891 
        `TLTI:  takb = lti;
892 
        `TLEI:  takb = lti|eqi;
893 
        `TGTI:  takb = !(lti|eqi);
894 
        `TGEI:  takb = !lti;
895 
        `TLOI:  takb = ltui;
896 
        `TLSI:  takb = ltui|eqi;
897 
        `THII:  takb = !(ltui|eqi);
898 
        `THSI:  takb = !ltui;
899 
        default:        takb = 1'b0;
900 
        endcase
901 
`BRr:
902 
        case(xIR[29:25])
903 
        `BRAZ:  takb = 1'b1;
904 
        `BEQZ:  takb = aeqz;
905 
        `BNEZ:  takb = !aeqz;
906 
        `BLTZ:  takb = a[63];
907 
        `BLEZ:  takb = a[63] || aeqz;
908 
        `BGTZ:  takb = !a[63] && !aeqz;
909 
        `BGEZ:  takb = !a[63];
910 
        `BRAD:  takb = 1;
911 
        `BNR:   takb = !rsf;
912 
        `BEQZD: takb = a==64'd0;
913 
        `BNEZD: takb = a!=64'd0;
914 
        `BLTZD: takb = a[63];
915 
        `BLEZD: takb = a[63] || aeqz;
916 
        `BGTZD: takb = !a[63] && !aeqz;
917 
        `BGEZD: takb = !a[63];
918 
        `BEQZR: takb = a==64'd0;
919 
        `BNEZR: takb = a!=64'd0;
920 
        `BLTZR: takb = a[63];
921 
        `BLEZR: takb = a[63] || aeqz;
922 
        `BGTZR: takb = !a[63] && !aeqz;
923 
        `BGEZR: takb = !a[63];
924 
        `BEQZRD:        takb = a==64'd0;
925 
        `BNEZRD:        takb = a!=64'd0;
926 
        `BLTZRD:        takb = a[63];
927 
        `BLEZRD:        takb = a[63] || aeqz;
928 
        `BGTZRD:        takb = !a[63] && !aeqz;
929 
        `BGEZRD:        takb = !a[63];
930 
        default:        takb = 1'b0;
931 
        endcase
932 
default:
933 
        takb = 1'b0;
934 
endcase
935 
 
936 
 
937 
//---------------------------------------------------------
938 
// Datapath (ALU) operations.
939 
//---------------------------------------------------------
940 
wire [6:0] cntlzo,cntloo;
941 
cntlz64 u12 ( .i(a),  .o(cntlzo) );
942 
cntlo64 u13 ( .i(a),  .o(cntloo) );
943 
 
944 
reg [1:0] shftop;
945 
wire [63:0] shfto;
946 
always @(xFunc)
947 
        if (xFunc==`ASL)
948 
                shftop = 2'b00;
949 
        else if (xFunc==`ROL || xFunc==`ROR)
950 
                shftop = 2'b01;
951 
        else if (xFunc==`LSR)
952 
                shftop = 2'b10;
953 
        else if (xFunc==`ASR)
954 
                shftop = 2'b11;
955 
        else
956 
                shftop = 2'b01;
957 
 
958 
wire [63:0] masko;
959 
shiftAndMask u15
960 
(
961 
        .op(shftop),
962 
        .oz(1'b0),              // zero the output
963 
        .a(a),
964 
        .b(b[5:0]),
965 
        .mb(xIR[12:7]),
966 
        .me(xIR[18:13]),
967 
        .o(shfto),
968 
        .mo(masko)
969 
);
970 
 
971 
function [63:0] fnIncPC;
972 
input [63:0] fpc;
973 
begin
974 
case(fpc[3:2])
975 
2'd0:   fnIncPC = {fpc[63:4],4'b0100};
976 
2'd1:   fnIncPC = {fpc[63:4],4'b1000};
977 
2'd2:   fnIncPC = {fpc[63:4]+60'd1,4'b0000};
978 
2'd3:   fnIncPC = {fpc[63:4]+60'd1,4'b0000};
979 
endcase
980 
end
981 
endfunction
982 
 
983 
always @(xOpcode or xFunc or a or b or imm or as or bs or imms or xpc or
984 
        sqrt_out or cntlzo or cntloo or tick or ipc or tba or regset or
985 
        lt or eq or ltu or mult_out or lti or eqi or ltui or xIR or div_q or div_r or
986 
        shfto or masko or bcdaddo or bcdsubo or fpLooOut or fpZLOut or
987 
        Wired or Index or Random or TLBPhysPage or TLBVirtPage or TLBASID or
988 
        PageTableAddr or BadVAddr or ASID or TLBPageMask
989 
)
990 
case(xOpcode)
991 
`R:
992 
        case(xFunc)
993 
        `COM:   xData = ~a;
994 
        `NOT:   xData = ~|a;
995 
        `NEG:   xData = -a;
996 
        `ABS:   xData = a[63] ? -a : a;
997 
        `SQRT:  xData = sqrt_out;
998 
        `SWAP:  xData = {a[31:0],a[63:32]};
999 
 
1000 
        `REDOR:         xData = |a;
1001 
        `REDAND:        xData = &a;
1002 
 
1003 
        `CTLZ:  xData = cntlzo;
1004 
        `CTLO:  xData = cntloo;
1005 
        `CTPOP: xData = {4'd0,popcnt6(a[5:0])} +
1006 
                                        {4'd0,popcnt6(a[11:6])} +
1007 
                                        {4'd0,popcnt6(a[17:12])} +
1008 
                                        {4'd0,popcnt6(a[23:18])} +
1009 
                                        {4'd0,popcnt6(a[29:24])} +
1010 
                                        {4'd0,popcnt6(a[35:30])} +
1011 
                                        {4'd0,popcnt6(a[41:36])} +
1012 
                                        {4'd0,popcnt6(a[47:42])} +
1013 
                                        {4'd0,popcnt6(a[53:48])} +
1014 
                                        {4'd0,popcnt6(a[59:54])} +
1015 
                                        {4'd0,popcnt6(a[63:60])}
1016 
                                        ;
1017 
        `SEXT8:         xData = {{56{a[7]}},a[7:0]};
1018 
        `SEXT16:        xData = {{48{a[15]}},a[15:0]};
1019 
        `SEXT32:        xData = {{32{a[31]}},a[31:0]};
1020 
 
1021 
        `MFSPR:
1022 
                case(xIR[34:30])
1023 
                `Wired:                 xData = Wired;
1024 
                `TLBIndex:              xData = Index;
1025 
                `TLBRandom:             xData = Random;
1026 
                `TLBPhysPage:   xData = {TLBPhysPage,13'd0};
1027 
                `TLBVirtPage:   xData = {TLBVirtPage,13'd0};
1028 
                `TLBPageMask:   xData = {TLBPageMask,13'd0};
1029 
                `TLBASID:               xData = TLBASID;
1030 
                `PageTableAddr: xData = {PageTableAddr,13'd0};
1031 
                `BadVAddr:              xData = {BadVAddr,13'd0};
1032 
                `ASID:                  xData = ASID;
1033 
                `EP0:                   xData = EP[0];
1034 
                `EP1:                   xData = EP[1];
1035 
                `EP2:                   xData = EP[2];
1036 
                `EP3:                   xData = EP[3];
1037 5 robfinch 
                `AXC:                   xData = xAXC;
1038 3 robfinch 
                default:        xData = 65'd0;
1039 
                endcase
1040 
        `MFTICK:        xData = tick;
1041 
        `MFEPC:         xData = ipc;
1042 
        `MFTBA:         xData = tba;
1043 
        `MTTBA:         xData = a;
1044 
        `MTREGSET:      xData = a;
1045 
        `MFREGSET:      xData = regset;
1046 
        default:        xData = 65'd0;
1047 
        endcase
1048 
`RR:
1049 
        case(xFunc)
1050 
        `ADD:   xData = a + b;
1051 
        `SUB:   xData = a - b;
1052 
        `CMP:   xData = lt ? 64'hFFFFFFFFFFFFF : eq ? 64'd0 : 64'd1;
1053 
        `CMPU:  xData = ltu ? 64'hFFFFFFFFFFFFF : eq ? 64'd0 : 64'd1;
1054 
        `SEQ:   xData = eq;
1055 
        `SNE:   xData = !eq;
1056 
        `SLT:   xData = lt;
1057 
        `SLE:   xData = lt|eq;
1058 
        `SGT:   xData = !(lt|eq);
1059 
        `SGE:   xData = !lt;
1060 5 robfinch 
        `SLTU:  xData = ltu;
1061 
        `SLEU:  xData = ltu|eq;
1062 
        `SGTU:  xData = !(ltu|eq);
1063 
        `SGEU:  xData = !ltu;
1064 3 robfinch 
        `AND:   xData = a & b;
1065 
        `OR:    xData = a | b;
1066 
        `XOR:   xData = a ^ b;
1067 
        `ANDC:  xData = a & ~b;
1068 
        `NAND:  xData = ~(a & b);
1069 
        `NOR:   xData = ~(a | b);
1070 5 robfinch 
        `XNOR:  xData = ~(a ^ b);
1071 3 robfinch 
        `MIN:   xData = lt ? a : b;
1072 
        `MAX:   xData = lt ? b : a;
1073 
        `MOVZ:  xData = b;
1074 
        `MOVNZ: xData = b;
1075 
        `MULS:  xData = mult_out[63:0];
1076 
        `MULU:  xData = mult_out[63:0];
1077 
        `DIVS:  xData = div_q;
1078 
        `DIVU:  xData = div_q;
1079 
        `MOD:   xData = div_r;
1080 
 
1081 
        `ASL:   xData = shfto;
1082 
        `LSR:   xData = shfto;
1083 
        `ROL:   xData = shfto;
1084 
        `ROR:   xData = {a[0],a[63:1]};
1085 
        `ASR:   xData = shfto;
1086 
        `ROLAM: xData = shfto & masko;
1087 
 
1088 
        `BCD_ADD:       xData = bcdaddo;
1089 
        `BCD_SUB:       xData = bcdsubo;
1090 
 
1091 
        default:        xData = 65'd0;
1092 
        endcase
1093 
`SHFTI:
1094 
        case(xFunc)
1095 
        `ASLI:  xData = shfto;
1096 
        `LSRI:  xData = shfto;
1097 
        `ROLI:  xData = shfto;
1098 
        `RORI:  xData = {a[0],a[63:1]};
1099 
        `ASRI:  xData = shfto;
1100 
        `ROLAMI:        xData = shfto & masko;
1101 
        `BFINS:         for (n = 0; n < 64; n = n + 1) xData[n] = masko[n] ? shfto[n] : b[n];
1102 
        `BFSET:         for (n = 0; n < 64; n = n + 1) xData[n] = masko[n] ? 1'b1 : b[n];
1103 
        `BFCLR:         for (n = 0; n < 64; n = n + 1) xData[n] = masko[n] ? 1'b0 : b[n];
1104 
        `BFCHG:         for (n = 0; n < 64; n = n + 1) xData[n] = masko[n] ? ~b[n] : b[n];
1105 
        default:        xData = 65'd0;
1106 
        endcase
1107 
`ADDI:  xData = a + imm;
1108 
`SUBI:  xData = a - imm;
1109 
`CMPI:  xData = lti ? 64'hFFFFFFFFFFFFF : eqi ? 64'd0 : 64'd1;
1110 
`CMPUI: xData = ltui ? 64'hFFFFFFFFFFFFF : eqi ? 64'd0 : 64'd1;
1111 
`MULSI: xData = mult_out[63:0];
1112 
`MULUI: xData = mult_out[63:0];
1113 
`DIVSI: xData = div_q;
1114 
`DIVUI: xData = div_q;
1115 
`ANDI:  xData = a & imm;
1116 
`ORI:   xData = a | imm;
1117 
`XORI:  xData = a ^ imm;
1118 
`SEQI:  xData = eqi;
1119 
`SNEI:  xData = !eqi;
1120 
`SLTI:  xData = lti;
1121 
`SLEI:  xData = lti|eqi;
1122 
`SGTI:  xData = !(lti|eqi);
1123 
`SGEI:  xData = !lti;
1124 
`SLTUI: xData = ltui;
1125 
`SLEUI: xData = ltui|eqi;
1126 
`SGTUI: xData = !(ltui|eqi);
1127 
`SGEUI: xData = !ltui;
1128 
`INB,`INCH,`INH,`INW:
1129 
                xData = a + imm;
1130 
`OUTB,`OUTC,`OUTH,`OUTW:
1131 
                xData = a + imm;
1132 
`LW,`LH,`LC,`LB,`LHU,`LCU,`LBU,`LWR:
1133 
                xData = a + imm;
1134 
`SW,`SH,`SC,`SB,`SWC:
1135 
                xData = a + imm;
1136 
`BEQ,`BNE,`BLT,`BLE,`BGT,`BGE,`BLTU,`BLEU,`BGTU,`BGEU,`BOR,`BAND:
1137 
                xData = 64'd0;
1138 
`TRAPcc:        xData = fnIncPC(xpc);
1139 
`TRAPcci:       xData = fnIncPC(xpc);
1140 
`CALL:          xData = fnIncPC(xpc);
1141 
`JAL:           xData = xpc + {xIR[29:25],2'b00};
1142 
`RET:   xData = a + {imm,2'b00};
1143 
`FPLOO: xData = fpLooOut;
1144 
`FPZL:  xData = fpZLOut;
1145 
default:        xData = 65'd0;
1146 
endcase
1147 
 
1148 
wire xIsSqrt = xOpcode==`R && xFunc==`SQRT;
1149 
wire xIsMult = (xOpcode==`RR && (xFunc==`MULU || xFunc==`MULS)) ||
1150 
        xOpcode==`MULSI || xOpcode==`MULUI;
1151 
wire xIsDiv = (xOpcode==`RR && (xFunc==`DIVU || xFunc==`DIVS)) ||
1152 
        xOpcode==`DIVSI || xOpcode==`DIVUI;
1153 
 
1154 
wire xIsLoad =
1155 
        xOpcode==`LW || xOpcode==`LH || xOpcode==`LB || xOpcode==`LWR ||
1156 
        xOpcode==`LHU || xOpcode==`LBU ||
1157 
        xOpcode==`LC || xOpcode==`LCU ||
1158 
        xOpcode==`INW || xOpcode==`INB || xOpcode==`INH || xOpcode==`INCH
1159 
        ;
1160 
wire xIsStore =
1161 
        xOpcode==`SW || xOpcode==`SH || xOpcode==`SB || xOpcode==`SC || xOpcode==`SWC ||
1162 
        xOpcode==`OUTW || xOpcode==`OUTH || xOpcode==`OUTB || xOpcode==`OUTC
1163 
        ;
1164 
wire xIsSWC = xOpcode==`SWC;
1165 
wire xIsIn =
1166 
        xOpcode==`INW || xOpcode==`INH || xOpcode==`INCH || xOpcode==`INB
1167 
        ;
1168 
//wire mIsSWC = mOpcode==`SWC;
1169 
 
1170 
//wire mIsLoad =
1171 
//      mOpcode==`LW || mOpcode==`LH || mOpcode==`LB || mOpcode==`LC || mOpcode==`LWR ||
1172 
//      mOpcode==`LHU || mOpcode==`LBU || mOpcode==`LCU ||
1173 
//      mOpcode==`INW || mOpcode==`INB || mOpcode==`INH
1174 
//      ;
1175 
wire m1IsLoad =
1176 
        m1Opcode==`LW || m1Opcode==`LH || m1Opcode==`LB || m1Opcode==`LC || m1Opcode==`LWR ||
1177 
        m1Opcode==`LHU || m1Opcode==`LBU || m1Opcode==`LCU
1178 
        ;
1179 
wire m1IsIn =
1180 
        m1Opcode==`INW || m1Opcode==`INH || m1Opcode==`INCH || m1Opcode==`INB
1181 
        ;
1182 
wire m1IsStore =
1183 
        m1Opcode==`SW || m1Opcode==`SH || m1Opcode==`SB || m1Opcode==`SC || m1Opcode==`SWC
1184 
        ;
1185 
wire m1IsIO =
1186 
        m1IsIn ||
1187 
        m1Opcode==`OUTW || m1Opcode==`OUTH || m1Opcode==`OUTC || m1Opcode==`OUTB
1188 
        ;
1189 
wire m3IsIO =
1190 
        m3Opcode==`INW || m3Opcode==`INH || m3Opcode==`INCH || m3Opcode==`INB ||
1191 
        m3Opcode==`OUTW || m3Opcode==`OUTH || m3Opcode==`OUTC || m3Opcode==`OUTB
1192 
        ;
1193 
 
1194 
wire m2IsLoad =
1195 
        m2Opcode==`LW || m2Opcode==`LH || m2Opcode==`LB || m2Opcode==`LC || m2Opcode==`LWR ||
1196 
        m2Opcode==`LHU || m2Opcode==`LBU || m2Opcode==`LCU
1197 
        ;
1198 
wire m3IsLoad =
1199 
        m3Opcode==`LW || m3Opcode==`LH || m3Opcode==`LB || m3Opcode==`LC || m3Opcode==`LWR ||
1200 
        m3Opcode==`LHU || m3Opcode==`LBU || m3Opcode==`LCU
1201 
        ;
1202 
wire m4IsLoad = m4Opcode==`LW || m4Opcode==`LWR
1203 
        ;
1204 
 
1205 
wire xIsFPLoo = xOpcode==`FPLOO;
1206 
 
1207 
// Stall on SWC allows rsf flag to be loaded for the next instruction
1208 
// Currently stalls on load of R0, but doesn't need to.
1209 
wire xStall = ((xIsLoad||xIsIn) && ((xRt==dRa)||(xRt==dRb)||(xRt==dRt))) || xIsSWC;
1210 
wire m1Stall = ((m1IsLoad||m1IsIn) && ((m1Rt==dRa)||(m1Rt==dRb)||(m1Rt==dRt)));// || mIsSWC;
1211 
wire m2Stall = ((m2IsLoad) && ((m2Rt==dRa)||(m2Rt==dRb)||(m2Rt==dRt)));// || mIsSWC;
1212 
wire m3Stall = ((m3IsLoad) && ((m3Rt==dRa)||(m3Rt==dRb)||(m3Rt==dRt)));// || mIsSWC;
1213 
wire m4Stall = ((m4IsLoad) && ((m4Rt==dRa)||(m4Rt==dRb)||(m4Rt==dRt)));// || mIsSWC;
1214 
wire eomc = dccyc ? dhit : cyc_o & !icaccess & !dcaccess ? ack_i : 1'b1;        // end of memory cycle
1215 
 
1216 
wire m1needWritePort = m1Opcode==`SW || m1Opcode==`SWC || m1Opcode==`SH || m1Opcode==`SC || m1Opcode==`SB;
1217 
wire m2needWritePort = m2Opcode==`SW||m2Opcode==`SWC;
1218 
wire m1needCmdPort = m1IsLoad && !m1IsCacheElement;
1219 
wire m2needCmdPort = m2Opcode==`SH||m2Opcode==`SC||m2Opcode==`SB;
1220 
wire m3needCmdPort = m3Opcode==`SW || m3Opcode==`SWC;
1221 5 robfinch 
wire m2needReadPort = m2IsLoad;
1222 
wire m3needReadPort = m3Opcode==`LW || m3Opcode==`LWR;
1223 
//wire m4needReadPort = m4Opcode==`LW || m4Opcode==`LWR;
1224 3 robfinch 
 
1225 
// Stall for the write port
1226 
wire StallM1 = (m1needWritePort && m2needWritePort) ||  // Write port collision
1227 
// Stall on the command port
1228 
        (m1needCmdPort && (m2needCmdPort||m3needCmdPort)) ||    // SW,SWC are still using the wr port in M2
1229 
// cache access is taking place
1230 
        icaccess || dcaccess
1231 
        ;
1232 
// M3 is using the command port
1233 5 robfinch 
wire StallM2 = (m2needCmdPort & m3needCmdPort) | (m3needReadPort|icaccess|dcaccess);
1234 
wire StallM3 = m3needReadPort & (icaccess|dcaccess);
1235 
wire advanceT = !resetA;
1236 3 robfinch 
wire advanceW = advanceT;
1237 5 robfinch 
wire advanceM4 = advanceW & (m4IsLoad ? !rd_empty : 1'b1);
1238 3 robfinch 
wire advanceM3 = advanceM4 &
1239 
                                        (m3IsIO ? ack_i : 1'b1) &
1240 5 robfinch 
                                        (m3IsLoad ? !rd_empty : 1'b1) &
1241 3 robfinch 
                                        !StallM3
1242 
                                        ;
1243 
wire advanceM2 = advanceM3 & !StallM2;
1244 
wire advanceM1 = advanceM2
1245 
                                        &
1246 
                                        (m1IsIO ? ack_i : 1'b1) &
1247 
                                        ((m1IsLoad & !m1IsCacheElement) ? !cmd_full : 1'b1) &
1248 
                                        ((m1IsLoad & m1IsCacheElement) ? dhit : 1'b1) &
1249 
                                        (m1IsStore ? !wr_full : 1'b1) &
1250 
                                        !StallM1
1251 
                                        ;
1252 
wire advanceX = advanceM1 & !cyc_o & (
1253 
                                        xIsSqrt ? sqrt_done :
1254 
                                        xIsMult ? mult_done :
1255 
                                        xIsDiv ? div_done :
1256 
                                        xIsFPLoo ? fpLooDone :
1257 
                                        1'b1);
1258 
wire advanceR = advanceX & !xStall & !m1Stall && !m2Stall && !m3Stall && !m4Stall;
1259 
wire advanceI = advanceR & ihit;
1260 
 
1261 
wire triggerDCacheLoad = (m1IsLoad & m1IsCacheElement & !dhit) &&       // there is a miss
1262 5 robfinch 
                                                !(icaccess | dcaccess) &&       // caches are not active
1263 3 robfinch 
                                                m2Opcode==`NOPI &&                      // and the pipeline is free of memory-ops
1264 
                                                m3Opcode==`NOPI &&
1265 
                                                m4Opcode==`NOPI &&
1266 
                                                wr_empty                                        // and the write buffer is empty
1267 
                                                ;
1268 
wire triggerICacheLoad = !ihit & !triggerDCacheLoad;                                            ;
1269 
 
1270 
wire xWillLoadStore = (xIsLoad||xIsStore) & advanceX;
1271 
wire stallCacheLoad = xWillLoadStore;
1272 
 
1273 
reg prev_nmi,nmi_edge;
1274 
 
1275 
 
1276 
//---------------------------------------------------------
1277 
// Register file.
1278 
//---------------------------------------------------------
1279 
 
1280 
syncRam512x64_1rw2r u5
1281 
(
1282 
        .wrst(1'b0),
1283 
        .wclk(clk),
1284 
        .wce(advanceW),
1285 
        .we(1'b1),
1286 
        .wadr(wRt),
1287 
        .i(wData),
1288 
        .wo(),
1289 
 
1290 
        .rrsta(1'b0),
1291 
        .rclka(~clk),
1292 
        .rcea(advanceR),
1293 
        .radra(dRa),
1294 
        .roa(rfoa),
1295 
 
1296 
        .rrstb(1'b0),
1297 
        .rclkb(~clk),
1298 
        .rceb(advanceR),
1299 
        .radrb(dRb),
1300 
        .rob(rfob)
1301 
);
1302 
 
1303 
 
1304 
reg m1clkoff,m2clkoff,m3clkoff,m4clkoff,wclkoff;
1305 
 
1306 
always @(posedge clk)
1307 
if (rst_i) begin
1308 
        bte_o <= 2'b00;
1309 
        cti_o <= 3'b000;
1310 
        cyc_o <= 1'b0;
1311 
        stb_o <= 1'b0;
1312 
        we_o <= 1'b0;
1313 
        sel_o <= 8'h00;
1314 
        adr_o <= 64'd0;
1315 
        dat_o <= 64'd0;
1316 
        dccyc <= 1'b0;
1317 5 robfinch 
 
1318 
        cmd_en <= 1'b0;
1319 
        cmd_instr <= 3'b001;
1320 
        cmd_bl <= 6'd1;
1321 
        cmd_byte_addr <= 30'd0;
1322 
 
1323 3 robfinch 
//      pc[0] <= 64'hFFFF_FFFF_FFFF_FFE0;
1324 
        m1Opcode <= `NOPI;
1325 
        m2Opcode <= `NOPI;
1326 
        m3Opcode <= `NOPI;
1327 
        m4Opcode <= `NOPI;
1328 
        dIR <= `NOP_INSN;
1329 
        dRt <= 9'd0;
1330 
        tRt <= 9'd0;
1331 
        wRt <= 9'd0;
1332 
        m1Rt <= 9'd0;
1333 
        m2Rt <= 9'd0;
1334 
        m3Rt <= 9'd0;
1335 
        m4Rt <= 9'd0;
1336 
        tData <= 64'd0;
1337 
        wData <= 64'd0;
1338 
        m1Data <= 64'd0;
1339 
        m2Data <= 64'd0;
1340 
        m3Data <= 64'd0;
1341 
        m4Data <= 64'd0;
1342 
        icaccess <= 1'b0;
1343 
        dcaccess <= 1'b0;
1344 
        nopI <= 1'b0;
1345 
        prev_ihit <= 1'b0;
1346 
        wirqf <= 1'b0;
1347 
        m1irqf <= 1'b0;
1348 
        m2irqf <= 1'b0;
1349 
        m3irqf <= 1'b0;
1350 
        m4irqf <= 1'b0;
1351 
        dirqf <= 1'b0;
1352 
        tick <= 32'd0;
1353 
        cstate <= IDLE;
1354 
        dImm <= 64'd0;
1355 
        regset <= 4'd0;
1356 
        xirqf <= 1'b0;
1357 
        xextype <= 8'h00;
1358 
        xIR <= `NOP_INSN;
1359 
        xpc <= 64'd0;
1360 
        a <= 64'd0;
1361 
        b <= 64'd0;
1362 
        imm <= 64'd0;
1363 
        xRt <= 9'd0;
1364 
        clk_en <= 1'b1;
1365 
        Random <= 4'hF;
1366 
        Wired <= 4'd0;
1367 
        StatusTLB <= 1'b0;
1368 
        StatusEXL <= 1'b0;
1369 
        epcnt <= 5'd0;
1370 
        EP[0] <= 32'd0;
1371 
        EP[1] <= 32'd0;
1372 
        EP[2] <= 32'd0;
1373 
        EP[3] <= 32'd0;
1374 5 robfinch 
        AXC <= 4'd0;
1375 
        dAXC <= 4'd0;
1376 
        xAXC <= 4'd0;
1377 
        resetA <= 1'b1;
1378 3 robfinch 
end
1379 
else begin
1380 
 
1381 
if (Random==Wired)
1382 
        Random <= 4'hF;
1383 
else
1384 
        Random <= Random - 4'd1;
1385 
 
1386 
tick <= tick + 64'd1;
1387 
 
1388 
prev_nmi <= nmi_i;
1389 
if (!prev_nmi & nmi_i)
1390 
        nmi_edge <= 1'b1;
1391 
 
1392 
 
1393 
// A store by any device in the system to a reserved address blcok
1394 
// clears the reservation.
1395 
 
1396 
if (sys_adv && sys_adr[63:5]==resv_address)
1397 
        resv_address <= 59'd0;
1398 
 
1399 
//---------------------------------------------------------
1400 
// TRAILER:
1401 
// - placeholder to allow the use of synchronous register
1402 
//   memory
1403 
//---------------------------------------------------------
1404 
if (advanceT) begin
1405 
        tRt <= 9'd0;
1406 
        tData <= 64'd0;
1407 
end
1408 
 
1409 
//---------------------------------------------------------
1410 
// WRITEBACK:
1411 
// - update the register file with results
1412 
// - record exception address and type
1413 
// - jump to exception handler routine (below)
1414 
//---------------------------------------------------------
1415 
if (advanceW) begin
1416 
        textype <= wextype;
1417 
        tRt <= wRt;
1418 
        tData <= wData;
1419 
//      regfile[wRt] <= wData;  <- regfile.v
1420 
        $display("Writing regfile[%d:%d] with %h", wRt[8:5],wRt[4:0], wData);
1421 
        wRt <= 9'd0;
1422 
        wData <= 64'd0;
1423 
        if (wirqf) begin
1424 
                wirqf <= 1'b0;
1425 
                m1irqf <= 1'b0;
1426 
                m2irqf <= 1'b0;
1427 
                m3irqf <= 1'b0;
1428 
                m4irqf <= 1'b0;
1429 
                xirqf <= 1'b0;
1430 
                dirqf <= 1'b0;
1431 
                ipc <= wpc;
1432 
                exception_type <= wextype;
1433 
        end
1434 
        clk_en <= 1'b1;
1435 
        if (wclkoff)
1436 
                clk_en <= 1'b0;
1437 
        wclkoff <= 1'b0;
1438 
        m1clkoff <= 1'b0;
1439 
        m2clkoff <= 1'b0;
1440 
        m3clkoff <= 1'b0;
1441 
        m4clkoff <= 1'b0;
1442 
end
1443 
 
1444 
//---------------------------------------------------------
1445 
// MEMORY:
1446 
// - merge word load data into pipeline.
1447 
//---------------------------------------------------------
1448 
if (advanceM4) begin
1449 
        wirqf <= m4irqf;
1450 
        wextype <= m4extype;
1451 
        wRt <= m4Rt;
1452 
        wpc <= m4pc;
1453 
        wclkoff <= m4clkoff;
1454 
        wData <= m4Data;
1455 
        m4Rt <= 9'd0;
1456 
        m4Opcode <= `NOPI;
1457 
        m4Data <= 64'd0;
1458 
        m4clkoff <= 1'b0;
1459 
        m4Opcode <= `NOPI;
1460 
        case(m4Opcode)
1461 5 robfinch 
        `LW,`LWR:       begin
1462 
                                        wData <= {rd_data,m4Data[31:0]};
1463 
                                        rd_en <= 1'b0;  // only if LW/LWR
1464 
                                end
1465 3 robfinch 
        default:        wData <= m4Data;
1466 
        endcase
1467 
end
1468 
 
1469 
 
1470 
//---------------------------------------------------------
1471 
// MEMORY:
1472 
//---------------------------------------------------------
1473 
if (advanceM3) begin
1474 
        m4Opcode <= m3Opcode;
1475 
        m4Func <= m3Func;
1476 
        m4irqf <= m3irqf;
1477 
        m4extype <= m3extype;
1478 
        m4Rt <= m3Rt;
1479 
        m4pc <= m3pc;
1480 
        m4clkoff <= m3clkoff;
1481 
        m3Rt <= 9'd0;
1482 
        m3Opcode <= `NOPI;
1483 
        m3Func <= 7'd0;
1484 
        m3clkoff <= 1'b0;
1485 
        m3pc <= 64'd0;
1486 
        m4Data <= m3Data;
1487 
        m3Addr <= 64'd0;
1488 
        m3Data <= 64'd0;
1489 
        case(m3Opcode)
1490 
        `INW:
1491 
                begin
1492 
                        cyc_o <= 1'b0;
1493 
                        stb_o <= 1'b0;
1494 
                        sel_o <= 4'h0;
1495 
                        m4Data <= {dat_i,m3Data[31:0]};
1496 
                end
1497 
        `OUTW:
1498 
                begin
1499 
                        cyc_o <= 1'b0;
1500 
                        stb_o <= 1'b0;
1501 
                        we_o <= 1'b0;
1502 
                        sel_o <= 4'h0;
1503 
                end
1504 
        `LW,`LWR:
1505 
                begin
1506 
                        rd_en <= 1'b1;
1507 
                        m4Data <= {32'd0,rd_data};
1508 
                end
1509 
        `LH:
1510 5 robfinch 
                begin
1511 
                rd_en <= 1'b0;
1512 3 robfinch 
                m4Data <= {{32{rd_data[31]}},rd_data};
1513 5 robfinch 
                end
1514 3 robfinch 
        `LHU:
1515 5 robfinch 
                begin
1516 
                rd_en <= 1'b0;
1517 3 robfinch 
                m4Data <= rd_data;
1518 5 robfinch 
                end
1519 3 robfinch 
        `LC:
1520 5 robfinch 
                begin
1521 
                rd_en <= 1'b0;
1522 3 robfinch 
                case(m3Addr[1])
1523 
                1'b0:   m4Data <= {{48{rd_data[15]}},rd_data[15:0]};
1524 
                1'b1:   m4Data <= {{48{rd_data[31]}},rd_data[31:16]};
1525 
                endcase
1526 5 robfinch 
                end
1527 3 robfinch 
        `LCU:
1528 5 robfinch 
                begin
1529 
                rd_en <= 1'b0;
1530 3 robfinch 
                case(m3Addr[1])
1531 
                1'b0:   m4Data <= {48'd0,rd_data[15:0]};
1532 
                1'b1:   m4Data <= {48'd0,rd_data[31:16]};
1533 
                endcase
1534 5 robfinch 
                end
1535 3 robfinch 
        `LB:
1536 5 robfinch 
                begin
1537 
                rd_en <= 1'b0;
1538 3 robfinch 
                case(m3Addr[1:0])
1539 
                2'd0:   m4Data <= {{56{rd_data[7]}},rd_data[7:0]};
1540 
                2'd1:   m4Data <= {{56{rd_data[15]}},rd_data[15:8]};
1541 
                2'd2:   m4Data <= {{56{rd_data[23]}},rd_data[23:16]};
1542 
                2'd3:   m4Data <= {{56{rd_data[31]}},rd_data[31:24]};
1543 
                endcase
1544 5 robfinch 
                end
1545 3 robfinch 
        `LBU:
1546 5 robfinch 
                begin
1547 3 robfinch 
                case(m3Addr[1:0])
1548 
                2'd0:   m4Data <= {{56{rd_data[7]}},rd_data[7:0]};
1549 
                2'd1:   m4Data <= {{56{rd_data[15]}},rd_data[15:8]};
1550 
                2'd2:   m4Data <= {{56{rd_data[23]}},rd_data[23:16]};
1551 
                2'd3:   m4Data <= {{56{rd_data[31]}},rd_data[31:24]};
1552 
                endcase
1553 5 robfinch 
                rd_en <= 1'b0;
1554 
                end
1555 3 robfinch 
        `SW,`SWC:
1556 
                begin
1557 
                        cmd_en <= 1'b1;
1558 
                        cmd_instr <= 3'b000;    // WRITE
1559 
                        cmd_bl <= 6'd2;                 // 2-words
1560 
                        cmd_byte_addr <= {m3Addr[29:3],3'b000};
1561 
                end
1562 
        default:        ;
1563 
        endcase
1564 
end
1565 
 
1566 
//---------------------------------------------------------
1567 
// MEMORY:
1568 
//---------------------------------------------------------
1569 
if (advanceM2) begin
1570 
        m3Opcode <= m2Opcode;
1571 
        m3Func <= m2Func;
1572 
        m3Addr <= m2Addr;
1573 
        m3Data <= m2Data;
1574 
        m3irqf <= m2irqf;
1575 
        m3extype <= m2extype;
1576 
        m3Rt <= m2Rt;
1577 
        m3pc <= m2pc;
1578 
        m3clkoff <= m2clkoff;
1579 
        m2Rt <= 9'd0;
1580 
        m2Opcode <= `NOPI;
1581 
        m2Func <= 7'd0;
1582 
        m2Addr <= 64'd0;
1583 
        m2Data <= 64'd0;
1584 
        m2clkoff <= 1'b0;
1585 
        m2pc <= 64'd0;
1586 
        case(m2Opcode)
1587 
        `INW:
1588 
                begin
1589 
                stb_o <= 1'b1;
1590 
                sel_o <= 4'hF;
1591 
                adr_o <= {m2Addr[63:3],3'b100};
1592 
                end
1593 
        `OUTW:
1594 
                begin
1595 
                stb_o <= 1'b1;
1596 
                we_o <= 1'b1;
1597 
                sel_o <= 4'hF;
1598 
                adr_o <= {m2Addr[63:3],3'b100};
1599 
                dat_o <= m2Data[63:32];
1600 
                end
1601 
        // Load fifo with upper half of word
1602 
        `SW,`SWC:
1603 
                begin
1604 
                        wr_en <= 1'b1;
1605 
                        wr_data <= m2Data[63:32];
1606 
                        wr_mask <= 4'h0;
1607 
                        wr_addr <= {m2Addr[63:3],3'b100};
1608 
                end
1609 
        `SH,`SC,`SB:
1610 
                begin
1611 
                        cmd_en <= 1'b1;
1612 
                        cmd_instr <= 3'b000;    // WRITE
1613 
                        cmd_bl <= 6'd1;                 // 1-word
1614 
                        cmd_byte_addr <= {m2Addr[29:2],2'b00};
1615 
                end
1616 
        // Initiate read operation
1617 
        `LW,`LWR,`LH,`LC,`LB,`LHU,`LBU,`LCU:
1618 
                begin
1619 
                        rd_en <= 1'b1;
1620 
                end
1621 
        default:        ;
1622 
        endcase
1623 
end
1624 
 
1625 
wrhit <= 1'b0;
1626 
//---------------------------------------------------------
1627 
// MEMORY:
1628 
// On a data cache hit for a load, the load is essentially
1629 
// finished in this stage. We switch the opcode to 'LDONE'
1630 
// to cause the pipeline to advance as if a NOPs were
1631 
// present.
1632 
//---------------------------------------------------------
1633 
if (advanceM1) begin
1634 
        m2Opcode <= m1Opcode;
1635 
        m2Func <= m1Func;
1636 
        m2Addr <= pea;
1637 
        m2Data <= m1Data;
1638 
        m2irqf <= m1irqf;
1639 
        m2extype <= m1extype;
1640 
        m2Rt <= m1Rt;
1641 
        m2pc <= m1pc;
1642 
        m2clkoff <= m1clkoff;
1643 
        m1Rt <= 9'd0;
1644 
        m1Opcode <= `NOPI;
1645 
        m1Func <= 7'd0;
1646 
        m1Data <= 64'd0;
1647 
        m1clkoff <= 1'b0;
1648 
        m1pc <= 64'd0;
1649 
        m1IsCacheElement <= 1'b0;
1650 
        case(m1Opcode)
1651 
        `MISC:
1652 
                case(m1Func)
1653 
                `TLBR:
1654 
                        begin
1655 
                                TLBVirtPage <= ITLBVirtPage[i];
1656 
                                TLBPhysPage <= ITLBPhysPage[i];
1657 
                        end
1658 
                `TLBWI,`TLBWR:
1659 
                        begin
1660 
                                ITLBValid[i] <= 1'b1;
1661 
                                ITLBVirtPage[i] <= TLBVirtPage;
1662 
                                ITLBPhysPage[i] <= TLBPhysPage;
1663 
                                ITLBPageMask[i] <= TLBPageMask;
1664 
                                ITLBASID[i] <= TLBASID;
1665 
                                DTLBValid[i] <= 1'b1;
1666 
                                DTLBVirtPage[i] <= TLBVirtPage;
1667 
                                DTLBPhysPage[i] <= TLBPhysPage;
1668 
                                DTLBPageMask[i] <= TLBPageMask;
1669 
                                DTLBASID[i] <= TLBASID;
1670 
                        end
1671 
                endcase
1672 
        `INW:
1673 
                begin
1674 
                        stb_o <= 1'b0;
1675 
                        m2Data <= {32'd0,dat_i};
1676 
                end
1677 
        `INH:
1678 
                begin
1679 
                        cyc_o <= 1'b0;
1680 
                        stb_o <= 1'b0;
1681 
                        sel_o <= 4'd0;
1682 
                        m2Data <= {{32{dat_i[31]}},dat_i[31: 0]};
1683 
                end
1684 
        `INCH:
1685 
                begin
1686 
                        cyc_o <= 1'b0;
1687 
                        stb_o <= 1'b0;
1688 
                        sel_o <= 4'd0;
1689 
                        case(sel_o)
1690 
                        4'b0011:        m2Data <= {{48{dat_i[15]}},dat_i[15: 0]};
1691 
                        4'b1100:        m2Data <= {{48{dat_i[31]}},dat_i[31:16]};
1692 
                        default:        m2Data <= 64'hDEADDEADDEADDEAD;
1693 
                        endcase
1694 
                end
1695 
        `INB:
1696 
                begin
1697 
                        cyc_o <= 1'b0;
1698 
                        stb_o <= 1'b0;
1699 
                        sel_o <= 4'd0;
1700 
                        case(sel_o)
1701 
                        4'b0001:        m2Data <= {{56{dat_i[ 7]}},dat_i[ 7: 0]};
1702 
                        4'b0010:        m2Data <= {{56{dat_i[15]}},dat_i[15: 8]};
1703 
                        4'b0100:        m2Data <= {{56{dat_i[23]}},dat_i[23:16]};
1704 
                        4'b1000:        m2Data <= {{56{dat_i[31]}},dat_i[31:24]};
1705 
                        default:        m2Data <= 64'hDEADDEADDEADDEAD;
1706 
                        endcase
1707 
                end
1708 
        `OUTW:
1709 
                begin
1710 
                        stb_o <= 1'b0;
1711 
                        we_o <= 1'b0;
1712 
                        sel_o <= 4'd0;
1713 
                end
1714 
        `OUTH,`OUTC,`OUTB:
1715 
                begin
1716 
                        cyc_o <= 1'b0;
1717 
                        stb_o <= 1'b0;
1718 
                        we_o <= 1'b0;
1719 
                        sel_o <= 4'd0;
1720 
                end
1721 
        `LW:
1722 
                if (!m1IsCacheElement) begin
1723 
                        cmd_en <= 1'b1;
1724 
                        cmd_bl <= 6'd2;                 // 2-words (from 32-bit interface)
1725 
                        cmd_instr <= 3'b001;    // READ
1726 
                        cmd_byte_addr <= {pea[63:3],3'b000};
1727 
                end
1728 
                else if (dhit) begin
1729 
                        m2Opcode <= `LDONE;
1730 
                        m2Data <= cdat;
1731 
                end
1732 
        `LWR:
1733 
                if (!m1IsCacheElement) begin
1734 
                        cmd_en <= 1'b1;
1735 
                        cmd_bl <= 6'd2;                 // 2-words (from 32-bit interface)
1736 
                        cmd_instr <= 3'b001;    // READ
1737 
                        cmd_byte_addr <= {pea[63:3],3'b000};
1738 
                        rsv_o <= 1'b1;
1739 
                        resv_address <= pea[63:5];
1740 
                end
1741 
                else if (dhit) begin
1742 
                        m2Opcode <= `LDONE;
1743 
                        m2Data <= cdat;
1744 
                        rsv_o <= 1'b1;
1745 
                        resv_address <= pea[63:5];
1746 
                end
1747 
        `LH:
1748 
                if (!m1IsCacheElement) begin
1749 
                        cmd_en <= 1'b1;
1750 
                        cmd_bl <= 6'd1;                 // 1-words (from 32-bit interface)
1751 
                        cmd_instr <= 3'b001;    // READ
1752 
                        cmd_byte_addr <= {pea[63:2],2'b00};
1753 
                end
1754 
                else if (dhit) begin
1755 
                        m2Opcode <= `LDONE;
1756 
                        if (pea[1])
1757 
                                m2Data <= {{32{cdat[31]}},cdat[31:0]};
1758 
                        else
1759 
                                m2Data <= {{32{cdat[63]}},cdat[63:32]};
1760 
                end
1761 
        `LHU:
1762 
                if (!m1IsCacheElement) begin
1763 
                        cmd_en <= 1'b1;
1764 
                        cmd_bl <= 6'd1;                 // 1-words (from 32-bit interface)
1765 
                        cmd_instr <= 3'b001;    // READ
1766 
                        cmd_byte_addr <= {pea[63:2],2'b00};
1767 
                end
1768 
                else if (dhit) begin
1769 
                        m2Opcode <= `LDONE;
1770 
                        if (pea[1])
1771 
                                m2Data <= {32'd0,cdat};
1772 
                        else
1773 
                                m2Data <= {32'd0,cdat[63:32]};
1774 
                end
1775 
        `LC:
1776 
                if (!m1IsCacheElement) begin
1777 
                        cmd_en <= 1'b1;
1778 
                        cmd_bl <= 6'd1;                 // 1-words (from 32-bit interface)
1779 
                        cmd_instr <= 3'b001;    // READ
1780 
                        cmd_byte_addr <= {pea[63:2],2'b00};
1781 
                end
1782 
                else if (dhit) begin
1783 
                        m2Opcode <= `LDONE;
1784 
                        case(pea[2:1])
1785 
                        2'd0:   m2Data <= {{48{cdat[15]}},cdat[15:0]};
1786 
                        2'd1:   m2Data <= {{48{cdat[31]}},cdat[31:16]};
1787 
                        2'd2:   m2Data <= {{48{cdat[47]}},cdat[47:32]};
1788 
                        2'd3:   m2Data <= {{48{cdat[63]}},cdat[63:48]};
1789 
                        endcase
1790 
                end
1791 
        `LCU:
1792 
                if (!m1IsCacheElement) begin
1793 
                        cmd_en <= 1'b1;
1794 
                        cmd_bl <= 6'd1;                 // 1-words (from 32-bit interface)
1795 
                        cmd_instr <= 3'b001;    // READ
1796 
                        cmd_byte_addr <= {pea[63:2],2'b00};
1797 
                end
1798 
                else if (dhit) begin
1799 
                        m2Opcode <= `LDONE;
1800 
                        case(pea[2:1])
1801 
                        2'd0:   m2Data <= {48'd0,cdat[15: 0]};
1802 
                        2'd1:   m2Data <= {48'd0,cdat[31:16]};
1803 
                        2'd2:   m2Data <= {48'd0,cdat[47:32]};
1804 
                        2'd3:   m2Data <= {48'd0,cdat[63:48]};
1805 
                        endcase
1806 
                end
1807 
        `LB:
1808 
                if (!m1IsCacheElement) begin
1809 
                        cmd_en <= 1'b1;
1810 
                        cmd_bl <= 6'd1;                 // 1-words (from 32-bit interface)
1811 
                        cmd_instr <= 3'b001;    // READ
1812 
                        cmd_byte_addr <= {pea[63:2],2'b00};
1813 
                end
1814 
                else if (dhit) begin
1815 
                        m2Opcode <= `LDONE;
1816 
                        case(pea[2:0])
1817 
                        3'b000: m2Data <= {{56{cdat[ 7]}},cdat[ 7: 0]};
1818 
                        3'b001: m2Data <= {{56{cdat[15]}},cdat[15: 8]};
1819 
                        3'b010: m2Data <= {{56{cdat[23]}},cdat[23:16]};
1820 
                        3'b011: m2Data <= {{56{cdat[31]}},cdat[31:24]};
1821 
                        3'b100: m2Data <= {{56{cdat[39]}},cdat[39:32]};
1822 
                        3'b101: m2Data <= {{56{cdat[47]}},cdat[47:40]};
1823 
                        3'b110: m2Data <= {{56{cdat[55]}},cdat[55:48]};
1824 
                        3'b111: m2Data <= {{56{cdat[63]}},cdat[63:56]};
1825 
                        endcase
1826 
                end
1827 
        `LBU:
1828 
                if (!m1IsCacheElement) begin
1829 
                        cmd_en <= 1'b1;
1830 
                        cmd_bl <= 6'd1;                 // 1-words (from 32-bit interface)
1831 
                        cmd_instr <= 3'b001;    // READ
1832 
                        cmd_byte_addr <= {pea[63:2],2'b00};
1833 
                end
1834 
                else if (dhit) begin
1835 
                        m2Opcode <= `LDONE;
1836 
                        case(pea[2:0])
1837 
                        3'b000: m2Data <= {56'd0,cdat[ 7: 0]};
1838 
                        3'b001: m2Data <= {56'd0,cdat[15: 8]};
1839 
                        3'b010: m2Data <= {56'd0,cdat[23:16]};
1840 
                        3'b011: m2Data <= {56'd0,cdat[31:23]};
1841 
                        3'b100: m2Data <= {56'd0,cdat[39:32]};
1842 
                        3'b101: m2Data <= {56'd0,cdat[47:40]};
1843 
                        3'b110: m2Data <= {56'd0,cdat[55:48]};
1844 
                        3'b111: m2Data <= {56'd0,cdat[63:56]};
1845 
                        endcase
1846 
                end
1847 
        `SW,`SH:
1848 
                begin
1849 
                        wrhit <= dhit;
1850 
                        wr_en <= 1'b1;
1851 
                        wr_data <= b[31:0];
1852 
                        wr_mask <= 4'h0;
1853 
                        wr_addr <= {pea[63:3],3'b000};
1854 
                        m2Addr <= {pea[63:3],3'b000};
1855 
                        if (resv_address==pea[63:5])
1856 
                                resv_address <= 59'd0;
1857 
                end
1858 
        `SC:
1859 
                begin
1860 
                        wrhit <= dhit;
1861 
                        wr_en <= 1'b1;
1862 
                        wr_data <= {2{b[15:0]}};
1863 
                        wr_mask <= pea[1] ? 4'b0011 : 4'b1100;
1864 
                        wr_addr <= {pea[63:2],2'b00};
1865 
                        m2Addr <= {pea[63:2],2'b00};
1866 
                        if (resv_address==pea[63:5])
1867 
                                resv_address <= 59'd0;
1868 
                end
1869 
        `SB:
1870 
                begin
1871 
                        wrhit <= dhit;
1872 
                        wr_en <= 1'b1;
1873 
                        wr_data <= {4{b[7:0]}};
1874 
                        wr_addr <= {pea[63:2],2'b00};
1875 
                        m2Addr <= {pea[63:2],2'b00};
1876 
                        case(pea[1:0])
1877 
                        2'd0:   wr_mask <= 4'b1110;
1878 
                        2'd1:   wr_mask <= 4'b1101;
1879 
                        2'd2:   wr_mask <= 4'b1011;
1880 
                        2'd3:   wr_mask <= 4'b0111;
1881 
                        endcase
1882 
                        if (resv_address==pea[63:5])
1883 
                                resv_address <= 59'd0;
1884 
                end
1885 
        `SWC:
1886 
                begin
1887 
                        rsf <= 1'b0;
1888 
                        if (resv_address==pea[63:5]) begin
1889 
                                wrhit <= dhit;
1890 
                                wr_en <= 1'b1;
1891 
                                wr_data <= b[31:0];
1892 
                                wr_mask <= 4'h0;
1893 
                                wr_addr <= {pea[63:3],3'b000};
1894 
                                m2Addr <= {pea[63:3],3'b000};
1895 
                                resv_address <= 59'd0;
1896 
                                rsf <= 1'b1;
1897 
                        end
1898 
                        else
1899 
                                m2Opcode <= `NOPI;
1900 
                end
1901 
        endcase
1902 
end
1903 
 
1904 
//---------------------------------------------------------
1905 
// EXECUTE:
1906 
// - perform datapath operation
1907 
// - Stores always initiate a bus cycle
1908 
// - Loads initiate a bus cycle only from non-cacheable
1909 
//   addresses
1910 
//---------------------------------------------------------
1911 
if (advanceX) begin
1912 
        m1irqf <= xirqf;
1913 
        m1extype <= xextype;
1914 
        m1Opcode <= xOpcode;
1915 
        m1Func <= xFunc;
1916 
        m1Rt <= xRt;
1917 
        m1Data <= xData;
1918 
        m1IsCacheElement <= xisCacheElement;
1919 
        if (xOpcode==`MOVZ && !aeqz) begin
1920 
                m1Rt <= 9'd0;
1921 
                m1Data <= 64'd0;
1922 
        end
1923 
        if (xOpcode==`MOVNZ && aeqz) begin
1924 
                m1Rt <= 9'd0;
1925 
                m1Data <= 64'd0;
1926 
        end
1927 
        m1pc <= xpc;
1928 
        xRt <= 9'd0;
1929 
        a <= 64'd0;
1930 
        b <= 64'd0;
1931 
        imm <= 64'd0;
1932 
        if (xOpcode[6:4]!=`IMM) begin
1933 
                xIR <= `NOP_INSN;
1934 
        end
1935 
//      xpc <= 64'd0;
1936 
        case(xOpcode)
1937 
        `MISC:
1938 
                case(xFunc)
1939 
                `WAIT:  m1clkoff <= 1'b1;
1940 
                `TLBR,`TLBWI:
1941 
                        begin
1942 
                                i <= Index;
1943 
                        end
1944 
                `TLBWR:
1945 
                        begin
1946 
                                i <= Random;
1947 
                        end
1948 
                default:        ;
1949 
                endcase
1950 
        `R:
1951 
                case(xFunc)
1952 
                `MTSPR:
1953 
                        case(xIR[29:25])
1954 
                        `Wired:                 Wired <= xData[3:0];
1955 
                        `ASID:                  ASID <= xData[7:0];
1956 
                        `TLBIndex:              Index <= xData[3:0];
1957 
                        `TLBVirtPage:   TLBVirtPage <= xData[63:13];
1958 
                        `TLBPhysPage:   TLBPhysPage <= xData[63:13];
1959 
                        `TLBPageMask:   TLBPageMask <= xData[24:13];
1960 
                        `TLBASID:               TLBASID <= xData[7:0];
1961 
                        `PageTableAddr: PageTableAddr <= xData[63:13];
1962 
                        `BadVAddr:              BadVAddr <= xData[63:13];
1963 
                        `EP0:                   EP[0] <= xData[31:0];
1964 
                        `EP1:                   EP[1] <= xData[31:0];
1965 
                        `EP2:                   EP[2] <= xData[31:0];
1966 
                        `EP3:                   EP[3] <= xData[31:0];
1967 
                        default:        ;
1968 
                        endcase
1969 
                `MTTBA: tba <= {xData[63:2],2'b00};
1970 
                default:        ;
1971 
                endcase
1972 
        `CALL:  m1Data <= fnIncPC(xpc);
1973 
        `INW:
1974 
                        begin
1975 
                        cyc_o <= 1'b1;
1976 
                        stb_o <= 1'b1;
1977 
                        sel_o <= 4'hF;
1978 
                        adr_o <= {xData[63:3],3'b000};
1979 
                        end
1980 
        `INH:
1981 
                        begin
1982 
                        cyc_o <= 1'b1;
1983 
                        stb_o <= 1'b1;
1984 
                        sel_o <= 4'b1111;
1985 
                        adr_o <= {xData[63:2],2'b00};
1986 
                        end
1987 
        `INCH:
1988 
                        begin
1989 
                        cyc_o <= 1'b1;
1990 
                        stb_o <= 1'b1;
1991 
                        case(xData[1])
1992 
                        1'b0:   sel_o <= 4'b0011;
1993 
                        1'b1:   sel_o <= 4'b1100;
1994 
                        endcase
1995 
                        adr_o <= {xData[63:1],1'b0};
1996 
                        end
1997 
        `INB:
1998 
                        begin
1999 
                        cyc_o <= 1'b1;
2000 
                        stb_o <= 1'b1;
2001 
                        case(xData[1:0])
2002 
                        2'b00:  sel_o <= 8'b0001;
2003 
                        2'b01:  sel_o <= 8'b0010;
2004 
                        2'b10:  sel_o <= 8'b0100;
2005 
                        2'b11:  sel_o <= 8'b1000;
2006 
                        endcase
2007 
                        adr_o <= xData;
2008 
                        end
2009 
        `OUTW:
2010 
                        begin
2011 
                        cyc_o <= 1'b1;
2012 
                        stb_o <= 1'b1;
2013 
                        we_o <= 1'b1;
2014 
                        sel_o <= 4'hF;
2015 
                        adr_o <= {xData[63:3],3'b000};
2016 
                        dat_o <= b[31:0];
2017 
                        end
2018 
        `OUTH:
2019 
                        begin
2020 
                        cyc_o <= 1'b1;
2021 
                        stb_o <= 1'b1;
2022 
                        we_o <= 1'b1;
2023 
                        sel_o <= 4'b1111;
2024 
                        adr_o <= {xData[63:2],2'b00};
2025 
                        dat_o <= b[31:0];
2026 
                        end
2027 
        `OUTC:
2028 
                        begin
2029 
                        cyc_o <= 1'b1;
2030 
                        stb_o <= 1'b1;
2031 
                        we_o <= 1'b1;
2032 
                        case(xData[1])
2033 
                        1'b0:   sel_o <= 4'b0011;
2034 
                        1'b1:   sel_o <= 4'b1100;
2035 
                        endcase
2036 
                        adr_o <= {xData[63:1],1'b0};
2037 
                        dat_o <= {2{b[15:0]}};
2038 
                        end
2039 
        `OUTB:
2040 
                        begin
2041 
                        cyc_o <= 1'b1;
2042 
                        stb_o <= 1'b1;
2043 
                        we_o <= 1'b1;
2044 
                        case(xData[1:0])
2045 
                        2'b00:  sel_o <= 4'b0001;
2046 
                        2'b01:  sel_o <= 4'b0010;
2047 
                        2'b10:  sel_o <= 4'b0100;
2048 
                        2'b11:  sel_o <= 4'b1000;
2049 
                        endcase
2050 
                        adr_o <= xData;
2051 
                        dat_o <= {4{b[7:0]}};
2052 
                        end
2053 
        `LB,`LBU,`LC,`LCU,`LH,`LHU,`LW,`LWR,`SW,`SH,`SC,`SB,`SWC:
2054 
                        ea <= xData;
2055 
        `DIVSI,`DIVUI:
2056 
                if (b==64'd0) begin
2057 
                        if (xextype == 8'h00)
2058 
                                xextype <= `EX_DBZ;
2059 
                end
2060 
        default:        ;
2061 
        endcase
2062 
end
2063 
 
2064 
//---------------------------------------------------------
2065 
// RFETCH:
2066 
// Register fetch stage
2067 
//---------------------------------------------------------
2068 
if (advanceR) begin
2069 
        xirqf <= dirqf;
2070 
        xextype <= dextype;
2071 
        xAXC <= dAXC;
2072 
        xIR <= dIR;
2073 
        xpc <= dpc;
2074 
        if (dOpcode[6:4]!=`IMM)
2075 
                dIR <= `NOP_INSN;
2076 
        dRa <= 9'd0;
2077 
        dRb <= 9'd0;
2078 
        casex(dRa)
2079 
        9'bxxxx00000:   a <= 64'd0;
2080 
        xRt:    a <= xData;
2081 
        m1Rt:   a <= m1Data;
2082 
        m2Rt:   a <= m2Data;
2083 
        m3Rt:   a <= m3Data;
2084 
        m4Rt:   a <= m4Data;
2085 
        wRt:    a <= wData;
2086 
        tRt:    a <= tData;
2087 
        default:        a <= rfoa;
2088 
        endcase
2089 
        casex(dRb)
2090 
        9'bxxxx00000:   b <= 64'd0;
2091 
        xRt:    b <= disRightShift ? -xData[5:0] : xData;
2092 
        m1Rt:   b <= disRightShift ? -m1Data[5:0] : m1Data;
2093 
        m2Rt:   b <= disRightShift ? -m2Data[5:0] : m2Data;
2094 
        m3Rt:   b <= disRightShift ? -m3Data[5:0] : m3Data;
2095 
        m4Rt:   b <= disRightShift ? -m4Data[5:0] : m4Data;
2096 
        wRt:    b <= disRightShift ? -wData[5:0] : wData;
2097 
        tRt:    b <= disRightShift ? -tData[5:0] : tData;
2098 
        default:        b <= disRightShift ? -rfob[5:0] : rfob;
2099 
        endcase
2100 
        if (dOpcode==`SHFTI)
2101 
                case(dFunc)
2102 
                `ROLI,`ASLI,`ROLAMI:    b <= {58'd0,dIR[24:19]};
2103 
                `RORI,`ASRI,`LSRI:              b <= {58'd0,~dIR[24:19]+6'd1};
2104 
                endcase
2105 
        case(dOpcode)
2106 
        `RR:
2107 
                case(dFunc)
2108 
                `BEQ,`BNE,`BLT,`BLE,`BGT,`BGE,`BLTU,`BLEU,`BGTU,`BGEU,`BRA,`BRN,`BAND,`BOR:
2109 
                        xRt <= 9'd0;
2110 
                default:        xRt <= {dAXC,dIR[24:20]};
2111 
                endcase
2112 
        `RET:   xRt <= {dAXC,dIR[24:20]};
2113 
        `BRr:   xRt <= 9'd0;
2114 
        `TRAPcc:        xRt <= {dAXC,5'd30};
2115 
        `TRAPcci:       xRt <= {dAXC,5'd30};
2116 
        `JMP:           xRt <= 9'd00;
2117 
        `CALL:          xRt <= {dAXC,5'd31};
2118 
        `SW,`SH,`SC,`SB,`OUTW,`OUTH,`OUTC,`OUTB:
2119 
                                xRt <= 9'd0;
2120 
        `NOPI:          xRt <= 9'd0;
2121 
        `BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
2122 
                                xRt <= 9'd0;
2123 
        default:        xRt <= {dAXC,dIR[29:25]};
2124 
        endcase
2125 
        if (xOpcode[6:4]==`IMM) begin
2126 
                imm <= {xIR[38:0],dIR[24:0]};
2127 
        end
2128 
        else
2129 
                case(dOpcode)
2130 
                `BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
2131 
                        imm <= {{46{dIR[17]}},dIR[17:0]};
2132 
                `SHFTI:
2133 
                        case(dFunc)
2134 
                        `RORI,`ASRI,`LSRI:
2135 
                                imm <= {58'd0,~dIR[24:19]+6'd1};
2136 
                        default:        imm <= {58'd0,dIR[24:19]};
2137 
                        endcase
2138 
                `ANDI:  imm <= {39'h7FFFFFFFFF,dIR[24:0]};
2139 
                `ORI:   imm <= {39'h0000000000,dIR[24:0]};
2140 
                `XORI:  imm <= {39'h0000000000,dIR[24:0]};
2141 
                `JMP:   imm <= {dpc[63:37],dIR[34:0],2'b00};
2142 
                `CALL:  imm <= {dpc[63:37],dIR[34:0],2'b00};
2143 
                `RET:   imm <= {44'h00000000000,dIR[19:0]};
2144 
                default:        imm <= {{39{dIR[24]}},dIR[24:0]};
2145 
                endcase
2146 
        if (dOpcode[6:4]==`IMM)
2147 
                xRt <= 9'd0;
2148 
        case(dOpcode)
2149 
        `MISC:
2150 
                case(dFunc)
2151 
                `SEI:   im <= 1'b1;
2152 
                `CLI:   im <= 1'b0;
2153 
                endcase
2154 
        endcase
2155 
 
2156 
end
2157 
 
2158 
//---------------------------------------------------------
2159 
// IFETCH:
2160 
// - check for external hardware interrupt
2161 
// - fetch instruction
2162 
// - increment PC
2163 
// - set special register defaults for some instructions
2164 
//---------------------------------------------------------
2165 
if (advanceI) begin
2166 5 robfinch 
        if (dOpcode[6:4]!=`IMM) begin
2167 
                epcnt <= epcnt + 5'd1;
2168 
                case(epcnt)
2169 
                5'd0:   AXC <= EP[0][ 3: 0];
2170 
                5'd1:   AXC <= EP[0][ 7: 4];
2171 
                5'd2:   AXC <= EP[0][11: 8];
2172 
                5'd3:   AXC <= EP[0][15:12];
2173 
                5'd4:   AXC <= EP[0][19:16];
2174 
                5'd5:   AXC <= EP[0][23:20];
2175 
                5'd6:   AXC <= EP[0][27:24];
2176 
                5'd7:   AXC <= EP[0][31:28];
2177 
                5'd8:   AXC <= EP[1][ 3: 0];
2178 
                5'd9:   AXC <= EP[1][ 7: 4];
2179 
                5'd10:  AXC <= EP[1][11: 8];
2180 
                5'd11:  AXC <= EP[1][15:12];
2181 
                5'd12:  AXC <= EP[1][19:16];
2182 
                5'd13:  AXC <= EP[1][23:20];
2183 
                5'd14:  AXC <= EP[1][27:24];
2184 
                5'd15:  AXC <= EP[1][31:28];
2185 
                5'd16:  AXC <= EP[2][ 3: 0];
2186 
                5'd17:  AXC <= EP[2][ 7: 4];
2187 
                5'd18:  AXC <= EP[2][11: 8];
2188 
                5'd19:  AXC <= EP[2][15:12];
2189 
                5'd20:  AXC <= EP[2][19:16];
2190 
                5'd21:  AXC <= EP[2][23:20];
2191 
                5'd22:  AXC <= EP[2][27:24];
2192 
                5'd23:  AXC <= EP[2][31:28];
2193 
                5'd24:  AXC <= EP[3][ 3: 0];
2194 
                5'd25:  AXC <= EP[3][ 7: 4];
2195 
                5'd26:  AXC <= EP[3][11: 8];
2196 
                5'd27:  AXC <= EP[3][15:12];
2197 
                5'd28:  AXC <= EP[3][19:16];
2198 
                5'd29:  AXC <= EP[3][23:20];
2199 
                5'd30:  AXC <= EP[3][27:24];
2200 
                5'd31:  AXC <= EP[3][31:28];
2201 
                endcase
2202 
        end
2203 3 robfinch 
//      AXC <= EP[epcnt[4:3]][{epcnt[2:0],2'b11}:{epcnt[2:0],2'b00}];
2204 
        if (nmi_edge) begin
2205 
                nmi_edge <= 1'b0;
2206 
                dirqf <= 1'b1;
2207 
                dIR <= `NOP_INSN;
2208 
                dextype <= `EX_NMI;
2209 
        end
2210 
        else if (irq_i & !im) begin
2211 
                dirqf <= 1'b1;
2212 
                dIR <= `NOP_INSN;
2213 
                dextype <= `EX_IRQ;
2214 
        end
2215 
        else if (dirqf) begin
2216 
                dIR <= `NOP_INSN;
2217 
        end
2218 
        else begin
2219 
                dIR <= insn;
2220 5 robfinch 
`include "insn_dump.v"
2221 3 robfinch 
        end
2222 
        nopI <= 1'b0;
2223 
        if (dOpcode[6:4]!=`IMM) begin
2224 
                dpc <= pc_axc;
2225 
        end
2226 
        dAXC <= AXC;
2227 
        dRa <= {AXC,insn[34:30]};
2228 
        dRb <= {AXC,insn[29:25]};
2229 
        if (ITLBMiss) begin
2230 
                dextype <= `EX_TLBI;
2231 
                StatusTLB <= 1'b1;
2232 
                StatusEXL <= 1'b1;
2233 
                BadVAddr <= pc_axc[63:13];
2234 
                pc[AXC] <= `ITLB_MissHandler;
2235 
                tlbra <= pc_axc;
2236 
        end
2237 
        else
2238 
                pc[AXC] <= fnIncPC(pc_axc);
2239 
end
2240 
 
2241 5 robfinch 
//---------------------------------------------------------
2242 
// Initialize program counters
2243 
//---------------------------------------------------------
2244 
if (resetA) begin
2245 
        pc[xAXC] <= `RESET_VECTOR;
2246 
        xAXC <= xAXC + 4'd1;
2247 
        if (xAXC==4'hF)
2248 
                resetA <= 1'b0;
2249 
end
2250 3 robfinch 
 
2251 
//`include "RPSTAGE.v"
2252 
//---------------------------------------------------------
2253 
// EXECUTE - part two:
2254 
// - override the default program counter increment for
2255 
//   control flow instructions
2256 
// - NOP out the instructions following a branch in the
2257 
//   pipeline
2258 
//---------------------------------------------------------
2259 
if (advanceX) begin
2260 
        case(xOpcode)
2261 
        `MISC:
2262 
                case(xFunc)
2263 
                `IRET:  begin
2264 
                                        if (StatusTLB) begin
2265 
                                                pc[xAXC] <= tlbra;
2266 
                                                if (xAXC==AXC)
2267 
                                                        dpc[63:2] <= tlbra[63:2];
2268 
                                                if (xAXC==dAXC)
2269 
                                                        xpc[63:2] <= tlbra[63:2];
2270 
                                                StatusTLB <= 1'b0;
2271 
                                        end
2272 
                                        else if (StatusEXL) begin
2273 
                                                pc[xAXC] <= ipc;
2274 
                                                if (xAXC==AXC)
2275 
                                                        dpc[63:2] <= ipc[63:2];
2276 
                                                if (xAXC==dAXC)
2277 
                                                        xpc[63:2] <= ipc[63:2];
2278 
                                        end
2279 
                                        StatusEXL <= 1'b0;
2280 
                                        xIR <= `NOP_INSN;
2281 
                                        dIR <= `NOP_INSN;
2282 
                                        xRt <= 9'd0;
2283 
                                end
2284 
                default:        ;
2285 
                endcase
2286 
        `RR:
2287 
                case(xFunc)
2288 
                `BEQ,`BNE,`BLT,`BLE,`BGT,`BGE,`BLTU,`BLEU,`BGTU,`BGEU,`BAND,`BOR:
2289 
                        if (takb) begin
2290 
                                pc[xAXC][63:4] <= xpc[63:4] + {{44{xIR[24]}},xIR[24:9]};
2291 
                                pc[xAXC][3:2] <= xIR[8:7];
2292 
                                if (xAXC==AXC) begin
2293 
                                        dpc[63:4] <= xpc[63:4] + {{44{xIR[24]}},xIR[24:9]};
2294 
                                        dpc[3:2] <= xIR[8:7];
2295 
                                        dIR <= `NOP_INSN;
2296 
                                end
2297 
                                if (xAXC==dAXC) begin
2298 
                                        xpc[63:4] <= xpc[63:4] + {{44{xIR[24]}},xIR[24:9]};
2299 
                                        xpc[3:2] <= xIR[8:7];
2300 
                                        xIR <= `NOP_INSN;
2301 
                                        xRt <= 9'd0;
2302 
                                end
2303 
                        end
2304 
                endcase
2305 
        `JMP:   begin
2306 
                                pc[xAXC] <= imm;
2307 
                                if (xAXC==AXC) begin
2308 
                                        dpc <= imm;
2309 
                                        dIR <= `NOP_INSN;
2310 
                                end
2311 
                                if (xAXC==dAXC) begin
2312 
                                        xpc <= imm;
2313 
                                        xIR <= `NOP_INSN;
2314 
                                        xRt <= 9'd0;
2315 
                                end
2316 
                        end
2317 
        `CALL:  begin
2318 
                                pc[xAXC] <= imm;
2319 
                                if (AXC==xAXC) begin
2320 
                                        dpc <= imm;
2321 
                                        dIR <= `NOP_INSN;
2322 
                                end
2323 
                                if (dAXC==xAXC) begin
2324 
                                        xpc <= imm;
2325 
                                        xIR <= `NOP_INSN;
2326 
                                        xRt <= 9'd0;
2327 
                                end
2328 
                        end
2329 
        `JAL:   begin
2330 
                                pc[xAXC][63:2] <= a[63:2] + imm[63:2];
2331 
                                if (AXC==xAXC) begin
2332 
                                        dIR <= `NOP_INSN;
2333 
                                        dpc[63:2] <= a[63:2] + imm[63:2];
2334 
                                end
2335 
                                if (dAXC==xAXC) begin
2336 
                                        xpc[63:2] <= a[63:2] + imm[63:2];
2337 
                                        xIR <= `NOP_INSN;
2338 
                                        xRt <= 9'd0;
2339 
                                end
2340 
                        end
2341 
        `RET:   begin
2342 
                                pc[xAXC][63:2] <= b[63:2];
2343 5 robfinch 
                                $display("returning to: %h", {b,2'b00});
2344 3 robfinch 
                                if (AXC==xAXC) begin
2345 
                                        dpc[63:2] <= b[63:2];
2346 
                                        dIR <= `NOP_INSN;
2347 
                                end
2348 
                                if (xAXC==dAXC) begin
2349 
                                        xpc[63:2] <= b[63:2];
2350 
                                        xIR <= `NOP_INSN;
2351 
                                        xRt <= 9'd0;
2352 
                                end
2353 
                        end
2354 
        `BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
2355 
                if (takb) begin
2356 
                        pc[xAXC][63:4] <= xpc[63:4] + {{50{xIR[24]}},xIR[29:20]};
2357 
                        pc[xAXC][3:2] <= xIR[19:18];
2358 
                        if (AXC==xAXC) begin
2359 
                                dpc[63:4] <= xpc[63:4] + {{50{xIR[24]}},xIR[29:20]};
2360 
                                dpc[3:2] <= xIR[19:18];
2361 
                                dIR <= `NOP_INSN;
2362 
                        end
2363 
                        if (dAXC==xAXC) begin
2364 
                                xpc[63:4] <= xpc[63:4] + {{50{xIR[24]}},xIR[29:20]};
2365 
                                xpc[3:2] <= xIR[19:18];
2366 
                                xIR <= `NOP_INSN;
2367 
                                xRt <= 9'd0;
2368 
                        end
2369 
                end
2370 
        `BRr:
2371 
                case(xIR[29:25])
2372 
                `BRAZ:
2373 
                        begin
2374 
                                pc[xAXC][63:4] <= xpc[63:4] + imm[63:4];
2375 
                                pc[xAXC][3:2] <= imm[3:2];
2376 
                                if (AXC==xAXC) begin
2377 
                                        dpc[63:4] <= xpc[63:4] + imm[63:4];
2378 
                                        dpc[3:2] <= imm[3:2];
2379 
                                        dIR <= `NOP_INSN;
2380 
                                end
2381 
                                if (dAXC==xAXC) begin
2382 
                                        xpc[63:4] <= xpc[63:4] + imm[63:4];
2383 
                                        xpc[3:2] <= imm[3:2];
2384 
                                        xIR <= `NOP_INSN;
2385 
                                        xRt <= 9'd0;
2386 
                                end
2387 
                        end
2388 
                `BEQZ,`BNEZ,`BLTZ,`BLEZ,`BGTZ,`BGEZ,`BNR:
2389 
                        if (takb) begin
2390 
                                pc[xAXC][63:4] <= xpc[63:4] + imm[63:4];
2391 
                                pc[xAXC][3:2] <= imm[3:2];
2392 
                                if (AXC==xAXC) begin
2393 
                                        dpc[63:4] <= xpc[63:4] + imm[63:4];
2394 
                                        dpc[3:2] <= imm[3:2];
2395 
                                        dIR <= `NOP_INSN;
2396 
                                end
2397 
                                if (dAXC==xAXC) begin
2398 
                                        xpc[63:4] <= xpc[63:4] + imm[63:4];
2399 
                                        xpc[3:2] <= imm[3:2];
2400 
                                        xIR <= `NOP_INSN;
2401 
                                        xRt <= 9'd0;
2402 
                                end
2403 
                        end
2404 
                `BRAD,`BEQZD,`BNEZD,`BLTZD,`BLEZD,`BGTZD,`BGEZD:
2405 
                        if (takb) begin
2406 
                                pc[xAXC][63:4] <= xpc[63:4] + imm[63:4];
2407 
                                pc[xAXC][3:2] <= imm[3:2];
2408 
                                if (AXC==xAXC) begin
2409 
                                        dpc[63:4] <= xpc[63:4] + imm[63:4];
2410 
                                        dpc[3:2] <= imm[3:2];
2411 
                                        dIR <= `NOP_INSN;
2412 
                                end
2413 
                        end
2414 
                `BEQZR,`BNEZR,`BLTZR,`BLEZR,`BGTZR,`BGEZR:
2415 
                        if (takb) begin
2416 
                                pc[xAXC][63:2] <= b[63:2];
2417 
                                if (xAXC==AXC) begin
2418 
                                        dpc[63:2] <= b[63:2];
2419 
                                        dIR <= `NOP_INSN;
2420 
                                end
2421 
                                if (dAXC==xAXC) begin
2422 
                                        xpc[63:2] <= b[63:2];
2423 
                                        xIR <= `NOP_INSN;
2424 
                                        xRt <= 9'd0;
2425 
                                end
2426 
                        end
2427 
                `BEQZRD,`BNEZRD,`BLTZRD,`BLEZRD,`BGTZRD,`BGEZRD:
2428 
                        if (takb) begin
2429 
                                pc[xAXC][63:2] <= b[63:2];
2430 
                                if (xAXC==AXC) begin
2431 
                                        dpc[63:2] <= b[63:2];
2432 
                                        dIR <= `NOP_INSN;
2433 
                                end
2434 
                        end
2435 
                endcase
2436 
        `TRAPcc:
2437 
                case(xFunc)
2438 
                `TRAP:
2439 
                        begin
2440 
                                pc[xAXC] <= `TRAP_VECTOR;
2441 
                                if (AXC==xAXC) begin
2442 
                                        dpc <= `TRAP_VECTOR;
2443 
                                        dIR <= `NOP_INSN;
2444 
                                end
2445 
                                if (xAXC==dAXC) begin
2446 
                                        xpc <= `TRAP_VECTOR;
2447 
                                        xIR <= `NOP_INSN;
2448 
                                        xRt <= 9'd0;
2449 
                                end
2450 
                        end
2451 
                `TEQ,`TNE,`TLT,`TLE,`TGT,`TGE,`TLO,`TLS,`THI,`THS:
2452 
                        if (takb) begin
2453 
                                pc[xAXC] <= `TRAP_VECTOR;
2454 
                                if (xAXC==AXC) begin
2455 
                                        dpc <= `TRAP_VECTOR;
2456 
                                        dIR <= `NOP_INSN;
2457 
                                end
2458 
                                if (xAXC==dAXC) begin
2459 
                                        xpc <= `TRAP_VECTOR;
2460 
                                        xIR <= `NOP_INSN;
2461 
                                        xRt <= 9'd0;
2462 
                                end
2463 
                        end
2464 
                endcase
2465 
        `TRAPcci:
2466 
                case(xIR[29:25])
2467 
                `TEQI,`TNEI,`TLTI,`TLEI,`TGTI,`TGEI,`TLOI,`TLSI,`THII,`THSI:
2468 
                        if (takb) begin
2469 
                                pc[xAXC] <= `TRAP_VECTOR;
2470 
                                if (xAXC==AXC) begin
2471 
                                        dpc <= `TRAP_VECTOR;
2472 
                                        dIR <= `NOP_INSN;
2473 
                                end
2474 
                                if (xAXC==dAXC) begin
2475 
                                        xpc <= `TRAP_VECTOR;
2476 
                                        xIR <= `NOP_INSN;
2477 
                                        xRt <= 9'd0;
2478 
                                end
2479 
                        end
2480 
                endcase
2481 
        default:        ;
2482 
        endcase
2483 
end
2484 
 
2485 
 
2486 
//((xOpcode==`TRAPcci) && takb)
2487 
//
2488 
//if (xOpcode==`TRAPcci || xOpcode==`TRAPcc)
2489 
//      pc_src <= `TRAP_VECTOR;
2490 
//else if (branchI) begin
2491 
//      pc_src[63:4] <= xpc[63:4] + {{50{xIR[24]}},xIR[29:20]};
2492 
//      pc_src[3:2] <= xIR[19:18];
2493 
//      pc_src[1:0] <= 2'b00;
2494 
//end
2495 
//else if (branch) begin
2496 
//      pc_src[63:4] <= xpc[63:4] + imm[63:4];
2497 
//      pc_src[3:2] <= imm[3:2];
2498 
//      pc_src[1:0] <= 2'b00;
2499 
//end
2500 
//else if (branchToReg)
2501 
//      pc_src <= b;
2502 
 
2503 
//---------------------------------------------------------
2504 
// WRITEBACK - part two:
2505 
// - vector to exception handler address
2506 
//---------------------------------------------------------
2507 
if (advanceW) begin
2508 
        if (wirqf) begin
2509 
                case(wextype)
2510 
                `EX_NON:        ;       // Dont' vector without an exception!
2511 
                `EX_RST:        pc[AXC] <= `RESET_VECTOR;
2512 
                `EX_NMI:        pc[AXC] <= `NMI_VECTOR;
2513 
                `EX_IRQ:        pc[AXC] <= `IRQ_VECTOR;
2514 
                default:        ;//pc[63:2] <= exception_address[63:2];
2515 
                endcase
2516 
        end
2517 
end
2518 
 
2519 
//---------------------------------------------------------
2520 
// Cache loader
2521 
//---------------------------------------------------------
2522 
if (rst_i) begin
2523 
        cstate <= IDLE;
2524 5 robfinch 
//      wr_icache <= 1'b0;
2525 3 robfinch 
        wr_dcache <= 1'b0;
2526 
end
2527 
else begin
2528 
cmd_en <= 1'b0;                         // allow this signal only to pulse for a single clock cycle
2529 5 robfinch 
//wr_icache <= 1'b0;
2530 3 robfinch 
wr_dcache <= 1'b0;
2531 
case(cstate)
2532 
IDLE:
2533 5 robfinch 
        // we can't do anything until the command buffer is available
2534 
        // in theory the command fifo should always be available
2535 
        if (!cmd_full) begin
2536 
                if (triggerDCacheLoad) begin
2537 
                        dcaccess <= 1'b1;
2538 
                        cmd_en <= 1'b1;
2539 
                        cmd_instr <= 3'b001;    // READ
2540 
                        cmd_byte_addr <= {pea[29:5],5'b00000};
2541 
                        dadr_o <= {pea[63:5],5'b00000};
2542 
                        cmd_bl <= 6'd8; // Eight words per cache line
2543 
                        cstate <= DCACT;
2544 
                end
2545 
                else if (triggerICacheLoad) begin
2546 
                        icaccess <= 1'b1;
2547 
                        cmd_en <= 1'b1; // the command fifo should always be available
2548 
                        cmd_instr <= 3'b001;    // READ
2549 
                        cmd_byte_addr <= {ppc[29:6],6'h00};
2550 
                        iadr_o <= {ppc[63:6],6'h00};
2551 
                        cmd_bl <= 6'd16;        // Sixteen words per cache line
2552 
                        cstate <= ICACT;
2553 
                end
2554 3 robfinch 
        end
2555 
        // Sometime after the read command is issued, the read fifo will begin to fill
2556 
ICACT:
2557 5 robfinch 
        begin
2558 
                rd_en <= 1'b1;
2559 3 robfinch 
                cstate <= ICACT0;
2560 
        end
2561 5 robfinch 
//ICACT0:       // Read word 0
2562 3 robfinch 
        // At this point it should not be necessary to check rd_empty
2563 5 robfinch 
//      if (!rd_empty) begin
2564 
//              wr_icache <= 1'b1;
2565 
//              idat <= rd_data;
2566 
//              cstate <= ICACT1;
2567 
//      end
2568 
 
2569 
ICACT0: // Read word 1-15
2570 3 robfinch 
        // Might have to wait for subsequent data to be available
2571 
        if (!rd_empty) begin
2572 5 robfinch 
//              wr_icache <= 1'b1;
2573 
//              idat <= rd_data;
2574 
                iadr_o[5:2] <= iadr_o[5:2] + 4'h1;
2575 
                if (iadr_o[5:2]==4'hF) begin
2576 
                        rd_en <= 1'b0;
2577 
                        tmem[iadr_o[12:6]] <= {1'b1,iadr_o[63:13]};     // This will cause ihit to go high
2578 
                        tvalid[iadr_o[12:6]] <= 1'b1;
2579 
                        cstate <= ICDLY;
2580 
                end
2581 3 robfinch 
        end
2582 
ICDLY:
2583 5 robfinch 
        // The fifo should have emptied out, if not we force it to empty
2584 3 robfinch 
        if (!rd_empty) begin
2585 
                rd_en <= 1'b1;
2586 
        end
2587 
        else begin
2588 
                icaccess <= 1'b0;
2589 
                rd_en <= 1'b0;
2590 
                cstate <= IDLE;
2591 
        end
2592 
        // Sometime after the read command is issued, the read fifo will begin to fill
2593 
DCACT:
2594 5 robfinch 
        begin
2595 3 robfinch 
                rd_en <= 1'b1;          // Data should be available on the next clock cycle
2596 
                cstate <= DCACT0;
2597 
        end
2598 
DCACT0: // Read word 0
2599 
        // At this point it should not be necessary to check rd_empty
2600 
        if (!rd_empty) begin
2601 
                wr_dcache <= 1'b1;
2602 
                ddat <= rd_data;
2603 
                dadr_o[4:2] <= 3'b000;
2604 
                cstate <= DCACT1;
2605 
        end
2606 
DCACT1: // Read word 1
2607 
        // Might have to wait for subsequent data to be available
2608 
        if (!rd_empty) begin
2609 
                wr_dcache <= 1'b1;
2610 
                ddat <= rd_data;
2611 5 robfinch 
                dadr_o[4:2] <= dadr_o[4:2]+3'd1;
2612 
                if (dadr_o[4:2]==3'b111) begin
2613 
                        rd_en <= 1'b0;
2614 
                        cstate <= DCDLY;
2615 
                end
2616 3 robfinch 
        end
2617 
DCDLY:
2618 5 robfinch 
        // The fifo should have emptied out, if not, empty it out.
2619 3 robfinch 
        if (!rd_empty) begin
2620 
                rd_en <= 1'b1;
2621 
        end
2622 
        else begin
2623 
                dcaccess <= 1'b0;
2624 
                rd_en <= 1'b0;
2625 
                cstate <= IDLE;
2626 
        end
2627 
endcase
2628 
end
2629 
 
2630 
end
2631 
 
2632 
endmodule

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