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[/] [raptor64/] [trunk/] [rtl/] [verilog/] [Raptor64_SetTargetRegister.v] - Blame information for rev 45

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`include "Raptor64_opcodes.v"
`timescale 1ns / 1ps
//=============================================================================
//        __
//   \\__/ o\    (C) 2011,2012  Robert Finch
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@opencores.org
//       ||
//  
//      Raptor64_SetTargetRegister.v
//  
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
//
//=============================================================================
 
`define EX_IRQ                  9'd449  // interrupt
`define EX_NMI                  9'd510  // non-maskable interrupt
 
module Raptor64_SetTargetRegister(rst,clk,advanceR,advanceX,dIR,dIRvalid,dAXC,xRt);
input rst;
input clk;
input advanceR;
input advanceX;
input [31:0] dIR;
input dIRvalid;
input [3:0] dAXC;
output [8:0] xRt;
reg [8:0] xRt;
 
wire [6:0] dOpcode = dIR[31:25];
wire [6:0] dFunc = dIR[6:0];
 
always @(posedge clk)
if (rst) begin
        xRt <= 9'd0;
end
else begin
if (advanceR) begin
        if (dIRvalid) begin
                casex(dOpcode)
                `MISC:
                        case(dFunc)
                        `SYSCALL:       xRt <= 9'd0;
                        default:        xRt <= 9'd0;
                        endcase
                `R:
                        case(dFunc)
                        `MTSPR,`CMG,`CMGI,`EXEC:
                                                xRt <= 9'd0;
                        default:        xRt <= {dAXC,dIR[19:15]};
                        endcase
                `MYST,`MUX:     xRt <= {dAXC,dIR[ 9: 5]};
                `SETLO:         xRt <= {dAXC,dIR[26:22]};
                `SETMID:        xRt <= {dAXC,dIR[26:22]};
                `SETHI:         xRt <= {dAXC,dIR[26:22]};
                `RR,`FP:        xRt <= {dAXC,dIR[14:10]};
                `BTRI:          xRt <= 9'd0;
                `BTRR:
                        case(dIR[4:0])
                        `LOOP:  xRt <= {dAXC,dIR[19:15]};
                        default: xRt <= 9'd0;
                        endcase
                `TRAPcc:        xRt <= 9'd0;
                `TRAPcci:       xRt <= 9'd0;
                `JMP:           xRt <= 9'd00;
                `CALL:          xRt <= {dAXC,5'd31};
                `RET:           xRt <= {dAXC,5'd30};
                `MEMNDX:
                        case(dFunc[5:0])
                        `SWX,`SHX,`SCX,`SBX,`SFX,`SFDX,`SPX,`SFPX,`SFDPX,`SSHX,`SSWX,
                        `OUTWX,`OUTHX,`OUTCX,`OUTBX:
                                        xRt <= 9'd0;
                        default:        xRt <= {dAXC,dIR[14:10]};
                        endcase
                `LSH,`LSW,
                `SW,`SH,`SC,`SB,`SF,`SFD,`SSH,`SSW,`SP,`SFP,`SFDP,      // but not SWC!
                `OUTW,`OUTH,`OUTC,`OUTB:
                                        xRt <= 9'd0;
                `NOPI:          xRt <= 9'd0;
                `BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
                                        xRt <= 9'd0;
                default:        xRt <= {dAXC,dIR[19:15]};
                endcase
        end
        else
                xRt <= 9'd0;
end
else if (advanceX)
        xRt <= 9'd0;
end
 
endmodule

Line No.	Rev	Author	Line
1	33	robfinch	`include "Raptor64_opcodes.v"
2			`timescale 1ns / 1ps
3			`//=============================================================================`
4			`// __`
5			`// \\__/ o\ (C) 2011,2012 Robert Finch`
6			`// \ __ / All rights reserved.`
7			`// \/_// robfinch<remove>@opencores.org`
8			`// \|\|`
9			`//`
10			`// Raptor64_SetTargetRegister.v`
11			`//`
12			`// This source file is free software: you can redistribute it and/or modify`
13			`// it under the terms of the GNU Lesser General Public License as published`
14			`// by the Free Software Foundation, either version 3 of the License, or`
15			`// (at your option) any later version.`
16			`//`
17			`// This source file is distributed in the hope that it will be useful,`
18			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
19			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
20			`// GNU General Public License for more details.`
21			`//`
22			`// You should have received a copy of the GNU General Public License`
23			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
24			`//`
25			`//`
26			`//=============================================================================`
27
28	41	robfinch	`define EX_IRQ 9'd449 // interrupt
29			`define EX_NMI 9'd510 // non-maskable interrupt
30
31	45	robfinch	`module Raptor64_SetTargetRegister(rst,clk,advanceR,advanceX,dIR,dIRvalid,dAXC,xRt);`
32	33	robfinch	`input rst;`
33			`input clk;`
34			`input advanceR;`
35			`input advanceX;`
36	41	robfinch	`input [31:0] dIR;`
37	45	robfinch	`input dIRvalid;`
38	33	robfinch	`input [3:0] dAXC;`
39			`output [8:0] xRt;`
40			`reg [8:0] xRt;`
41
42	41	robfinch	`wire [6:0] dOpcode = dIR[31:25];`
43	33	robfinch	`wire [6:0] dFunc = dIR[6:0];`
44
45			`always @(posedge clk)`
46			`if (rst) begin`
47			`xRt <= 9'd0;`
48			`end`
49			`else begin`
50			`if (advanceR) begin`
51	45	robfinch	`if (dIRvalid) begin`
52			`casex(dOpcode)`
53			`MISC:
54			`case(dFunc)`
55			`SYSCALL: xRt <= 9'd0;
56			`default: xRt <= 9'd0;`
57			`endcase`
58			`R:
59			`case(dFunc)`
60			`MTSPR,`CMG,`CMGI,`EXEC:
61			`xRt <= 9'd0;`
62			`default: xRt <= {dAXC,dIR[19:15]};`
63			`endcase`
64			`MYST,`MUX: xRt <= {dAXC,dIR[ 9: 5]};
65			`SETLO: xRt <= {dAXC,dIR[26:22]};
66			`SETMID: xRt <= {dAXC,dIR[26:22]};
67			`SETHI: xRt <= {dAXC,dIR[26:22]};
68			`RR,`FP: xRt <= {dAXC,dIR[14:10]};
69			`BTRI: xRt <= 9'd0;
70			`BTRR:
71			`case(dIR[4:0])`
72			`LOOP: xRt <= {dAXC,dIR[19:15]};
73			`default: xRt <= 9'd0;`
74			`endcase`
75			`TRAPcc: xRt <= 9'd0;
76			`TRAPcci: xRt <= 9'd0;
77			`JMP: xRt <= 9'd00;
78			`CALL: xRt <= {dAXC,5'd31};
79			`RET: xRt <= {dAXC,5'd30};
80			`MEMNDX:
81			`case(dFunc[5:0])`
82			`SWX,`SHX,`SCX,`SBX,`SFX,`SFDX,`SPX,`SFPX,`SFDPX,`SSHX,`SSWX,
83			`OUTWX,`OUTHX,`OUTCX,`OUTBX:
84	33	robfinch	`xRt <= 9'd0;`
85	45	robfinch	`default: xRt <= {dAXC,dIR[14:10]};`
86			`endcase`
87			`LSH,`LSW,
88			`SW,`SH,`SC,`SB,`SF,`SFD,`SSH,`SSW,`SP,`SFP,`SFDP, // but not SWC!
89			`OUTW,`OUTH,`OUTC,`OUTB:
90			`xRt <= 9'd0;`
91			`NOPI: xRt <= 9'd0;
92			`BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
93			`xRt <= 9'd0;`
94	41	robfinch	`default: xRt <= {dAXC,dIR[19:15]};`
95	33	robfinch	`endcase`
96	45	robfinch	`end`
97			`else`
98			`xRt <= 9'd0;`
99	33	robfinch	`end`
100			`else if (advanceX)`
101			`xRt <= 9'd0;`
102			`end`
103
104			`endmodule`

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[/] [raptor64/] [trunk/] [rtl/] [verilog/] [Raptor64_SetTargetRegister.v] - Blame information for rev 45