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[/] [raptor64/] [trunk/] [rtl/] [verilog/] [Raptor64_dcache_ram.v] - Blame information for rev 3

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1 3 robfinch 
// ============================================================================
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// (C) 2012 Robert Finch
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// All Rights Reserved.
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// robfinch<remove>@opencores.org
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//
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// Raptor64.v - dcache_ram
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//  - 64 bit CPU data cache ram
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.
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//
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// ============================================================================
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//
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module Raptor64_dcache_ram(clk,wr,sel,wadr,i,radr,o);
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input clk;
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input wr;
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input [3:0] sel;
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input [13:2] wadr;
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input [31:0] i;
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input [13:3] radr;
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output [63:0] o;
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reg [7:0] mem0 [2047:0];
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reg [31:0] memH [2047:0];
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syncRam2kx8_1rw1r u1
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(
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        .wrst(1'b0),
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        .wclk(clk),
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        .wce(sel[0] && !wadr[2]),
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        .we(wr),
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        .wadr(wadr[13:3]),
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        .i(i[7:0]),
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        .wo(),
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        .rrst(1'b0),
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        .rclk(~clk),
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        .rce(1'b1),
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        .radr(radr[13:3]),
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        .o(o[7:0])
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);
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syncRam2kx8_1rw1r u2
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(
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        .wrst(1'b0),
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        .wclk(clk),
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        .wce(sel[1] && !wadr[2]),
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        .we(wr),
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        .wadr(wadr[13:3]),
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        .i(i[15:8]),
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        .wo(),
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        .rrst(1'b0),
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        .rclk(~clk),
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        .rce(1'b1),
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        .radr(radr[13:3]),
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        .o(o[15:8])
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);
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syncRam2kx8_1rw1r u3
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(
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        .wrst(1'b0),
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        .wclk(clk),
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        .wce(sel[2] && !wadr[2]),
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        .we(wr),
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        .wadr(wadr[13:3]),
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        .i(i[23:16]),
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        .wo(),
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        .rrst(1'b0),
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        .rclk(~clk),
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        .rce(1'b1),
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        .radr(radr[13:3]),
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        .o(o[23:16])
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);
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syncRam2kx8_1rw1r u4
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(
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        .wrst(1'b0),
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        .wclk(clk),
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        .wce(sel[3] && !wadr[2]),
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        .we(wr),
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        .wadr(wadr[13:3]),
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        .i(i[31:24]),
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        .wo(),
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        .rrst(1'b0),
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        .rclk(~clk),
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        .rce(1'b1),
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        .radr(radr[13:3]),
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        .o(o[31:24])
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);
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syncRam2kx8_1rw1r u5
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(
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        .wrst(1'b0),
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        .wclk(clk),
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        .wce(sel[0] && wadr[2]),
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        .we(wr),
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        .wadr(wadr[13:3]),
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        .i(i[7:0]),
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        .wo(),
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        .rrst(1'b0),
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        .rclk(~clk),
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        .rce(1'b1),
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        .radr(radr[13:3]),
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        .o(o[39:32])
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);
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syncRam2kx8_1rw1r u6
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(
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        .wrst(1'b0),
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        .wclk(clk),
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        .wce(sel[1] && wadr[2]),
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        .we(wr),
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        .wadr(wadr[13:3]),
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        .i(i[15:8]),
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        .wo(),
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        .rrst(1'b0),
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        .rclk(~clk),
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        .rce(1'b1),
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        .radr(radr[13:3]),
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        .o(o[47:40])
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);
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syncRam2kx8_1rw1r u7
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(
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        .wrst(1'b0),
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        .wclk(clk),
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        .wce(sel[2] && wadr[2]),
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        .we(wr),
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        .wadr(wadr[13:3]),
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        .i(i[23:16]),
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        .wo(),
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        .rrst(1'b0),
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        .rclk(~clk),
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        .rce(1'b1),
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        .radr(radr[13:3]),
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        .o(o[55:48])
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);
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syncRam2kx8_1rw1r u8
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(
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        .wrst(1'b0),
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        .wclk(clk),
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        .wce(sel[3] && wadr[2]),
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        .we(wr),
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        .wadr(wadr[13:3]),
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        .i(i[31:24]),
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        .wo(),
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        .rrst(1'b0),
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        .rclk(~clk),
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        .rce(1'b1),
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        .radr(radr[13:3]),
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        .o(o[63:56])
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);
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endmodule
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