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[/] [raptor64/] [trunk/] [rtl/] [verilog/] [Raptor64_set.v] - Blame information for rev 41

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`include "Raptor64_opcodes.v"
`timescale 1ns / 1ps
//=============================================================================
//        __
//   \\__/ o\    (C) 2012  Robert Finch
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@opencores.org
//       ||
//  
//      Raptor64_set.v
//  - set datapath operations
//
//  
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
//
//=============================================================================
//
module Raptor64_set(xIR, a, b, imm, o);
input [31:0] xIR;
input [63:0] a;
input [63:0] b;
input [63:0] imm;
output [63:0] o;
reg [63:0] o;
 
wire [6:0] xOpcode = xIR[31:25];
wire [5:0] xFunc = xIR[5:0];
 
wire eqi = a==imm;
wire lti = $signed(a) < $signed(imm);
wire ltui = a < imm;
wire eq = a==b;
wire lt = $signed(a) < $signed(b);
wire ltu = a < b;
 
always @(xOpcode,xFunc,eq,lt,ltu,eqi,lti,ltui)
case (xOpcode)
`RR:
        case(xFunc)
        `SEQ:   o = eq;
        `SNE:   o = !eq;
        `SLT:   o = lt;
        `SLE:   o = lt|eq;
        `SGT:   o = !(lt|eq);
        `SGE:   o = !lt;
        `SLTU:  o = ltu;
        `SLEU:  o = ltu|eq;
        `SGTU:  o = !(ltu|eq);
        `SGEU:  o = !ltu;
        default:        o = 64'd0;
        endcase
`SEQI:  o = eqi;
`SNEI:  o = !eqi;
`SLTI:  o = lti;
`SLEI:  o = lti|eqi;
`SGTI:  o = !(lti|eqi);
`SGEI:  o = !lti;
`SLTUI: o = ltui;
`SLEUI: o = ltui|eqi;
`SGTUI: o = !(ltui|eqi);
`SGEUI: o = !ltui;
default:        o = 64'd0;
endcase
 
endmodule

Line No.	Rev	Author	Line
1	31	robfinch	`include "Raptor64_opcodes.v"
2			`timescale 1ns / 1ps
3			`//=============================================================================`
4			`// __`
5			`// \\__/ o\ (C) 2012 Robert Finch`
6			`// \ __ / All rights reserved.`
7			`// \/_// robfinch<remove>@opencores.org`
8			`// \|\|`
9			`//`
10			`// Raptor64_set.v`
11			`// - set datapath operations`
12			`//`
13			`//`
14			`// This source file is free software: you can redistribute it and/or modify`
15			`// it under the terms of the GNU Lesser General Public License as published`
16			`// by the Free Software Foundation, either version 3 of the License, or`
17			`// (at your option) any later version.`
18			`//`
19			`// This source file is distributed in the hope that it will be useful,`
20			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
21			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
22			`// GNU General Public License for more details.`
23			`//`
24			`// You should have received a copy of the GNU General Public License`
25			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
26			`//`
27			`//`
28			`//=============================================================================`
29			`//`
30			`module Raptor64_set(xIR, a, b, imm, o);`
31	41	robfinch	`input [31:0] xIR;`
32	31	robfinch	`input [63:0] a;`
33			`input [63:0] b;`
34			`input [63:0] imm;`
35			`output [63:0] o;`
36			`reg [63:0] o;`
37
38	41	robfinch	`wire [6:0] xOpcode = xIR[31:25];`
39			`wire [5:0] xFunc = xIR[5:0];`
40	31	robfinch
41			`wire eqi = a==imm;`
42			`wire lti = $signed(a) < $signed(imm);`
43			`wire ltui = a < imm;`
44			`wire eq = a==b;`
45			`wire lt = $signed(a) < $signed(b);`
46			`wire ltu = a < b;`
47
48			`always @(xOpcode,xFunc,eq,lt,ltu,eqi,lti,ltui)`
49			`case (xOpcode)`
50			`RR:
51			`case(xFunc)`
52			`SEQ: o = eq;
53			`SNE: o = !eq;
54			`SLT: o = lt;
55			`SLE: o = lt\|eq;
56			`SGT: o = !(lt\|eq);
57			`SGE: o = !lt;
58			`SLTU: o = ltu;
59			`SLEU: o = ltu\|eq;
60			`SGTU: o = !(ltu\|eq);
61			`SGEU: o = !ltu;
62			`default: o = 64'd0;`
63			`endcase`
64			`SEQI: o = eqi;
65			`SNEI: o = !eqi;
66			`SLTI: o = lti;
67			`SLEI: o = lti\|eqi;
68			`SGTI: o = !(lti\|eqi);
69			`SGEI: o = !lti;
70			`SLTUI: o = ltui;
71			`SLEUI: o = ltui\|eqi;
72			`SGTUI: o = !(ltui\|eqi);
73			`SGEUI: o = !ltui;
74			`default: o = 64'd0;`
75			`endcase`
76
77			`endmodule`

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[/] [raptor64/] [trunk/] [rtl/] [verilog/] [Raptor64_set.v] - Blame information for rev 41