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[/] [raptor64/] [trunk/] [rtl/] [verilog/] [Raptor64_shift.v] - Blame information for rev 33

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1 31 robfinch
`include "Raptor64_opcodes.v"
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`timescale 1ns / 1ps
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//=============================================================================
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//        __
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//   \\__/ o\    (C) 2012  Robert Finch
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@opencores.org
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//       ||
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//  
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//      Raptor64_shift.v
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//  - shift operations
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//
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//  
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//                                                                          
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//
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//=============================================================================
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//
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module Raptor64_shift(xIR, a, b, mask, o);
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input [41:0] xIR;
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input [63:0] a;
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input [63:0] b;
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input [63:0] mask;
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output [63:0] o;
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reg [63:0] o;
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wire [6:0] xOpcode = xIR[41:35];
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wire [6:0] xFunc = xIR[6:0];
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wire [4:0] xFunc5 = xIR[4:0];
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wire [127:0] shlxo = {64'd0,a} << b[5:0];
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wire [127:0] shruxo = {a,64'd0} >> b[5:0];
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wire [63:0] shlo = shlxo[63:0];
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wire [63:0] shruo = shruxo[127:64];
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wire [63:0] rolo = {shlxo[127:64]|shlxo[63:0]};
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wire [63:0] roro = {shruxo[127:64]|shruxo[63:0]};
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wire [63:0] shro = ~(~a >> b[5:0]);
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always @(xOpcode,xFunc,xFunc5,shlo,shruo,rolo,roro,shro,mask)
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case(xOpcode)
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`RR:
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        case(xFunc)
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        `SHL:   o = shlo;
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        `SHRU:  o = shruo;
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        `ROL:   o = rolo;
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        `ROR:   o = roro;
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        `SHR:   o = shro;
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        `ROLAM: o = rolo & mask;
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        default:        o = 64'd0;
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        endcase
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`SHFTI:
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        case(xFunc5)
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        `SHLI:  o = shlo;
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        `SHRUI: o = shruo;
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        `ROLI:  o = rolo;
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        `RORI:  o = roro;
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        `SHRI:  o = shro;
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        `ROLAMI:        o = rolo & mask;
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        default:        o = 64'd0;
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        endcase
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default:        o = 64'd0;
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endcase
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endmodule

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