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[/] [raptor64/] [trunk/] [rtl/] [verilog/] [Raptor64_shift.v] - Blame information for rev 48

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`include "Raptor64_opcodes.v"
`timescale 1ns / 1ps
//=============================================================================
//        __
//   \\__/ o\    (C) 2012  Robert Finch
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@opencores.org
//       ||
//  
//      Raptor64_shift.v
//  - shift operations
//
//  
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
//
//=============================================================================
//
module Raptor64_shift(xIR, a, b, mask, o, rolo);
input [31:0] xIR;
input [63:0] a;
input [63:0] b;
input [63:0] mask;
output [63:0] o;
reg [63:0] o;
output [63:0] rolo;
 
wire [6:0] xOpcode = xIR[31:25];
wire [5:0] xFunc = xIR[5:0];
wire [3:0] xFunc4 = xIR[3:0];
 
wire [127:0] shlxo = {64'd0,a} << b[5:0];
wire [127:0] shruxo = {a,64'd0} >> b[5:0];
wire [63:0] shlo = shlxo[63:0];
wire [63:0] shruo = shruxo[127:64];
assign rolo = {shlxo[127:64]|shlxo[63:0]};
wire [63:0] roro = {shruxo[127:64]|shruxo[63:0]};
wire [63:0] shro = ~(~a >> b[5:0]);
 
always @(xOpcode,xFunc,xFunc4,shlo,shruo,rolo,roro,shro,mask)
case(xOpcode)
`RR:
        case(xFunc)
        `SHL:   o = shlo;
        `SHLU:  o = shlo;
        `SHRU:  o = shruo;
        `ROL:   o = rolo;
        `ROR:   o = roro;
        `SHR:   o = shro;
        default:        o = 64'd0;
        endcase
`SHFTI:
        case(xFunc4)
        `SHLI:  o = shlo;
        `SHLUI: o = shlo;
        `SHRUI: o = shruo;
        `ROLI:  o = rolo;
        `RORI:  o = roro;
        `SHRI:  o = shro;
        default:        o = 64'd0;
        endcase
default:        o = 64'd0;
endcase
 
endmodule

Line No.	Rev	Author	Line
1	31	robfinch	`include "Raptor64_opcodes.v"
2			`timescale 1ns / 1ps
3			`//=============================================================================`
4			`// __`
5			`// \\__/ o\ (C) 2012 Robert Finch`
6			`// \ __ / All rights reserved.`
7			`// \/_// robfinch<remove>@opencores.org`
8			`// \|\|`
9			`//`
10			`// Raptor64_shift.v`
11			`// - shift operations`
12			`//`
13			`//`
14			`// This source file is free software: you can redistribute it and/or modify`
15			`// it under the terms of the GNU Lesser General Public License as published`
16			`// by the Free Software Foundation, either version 3 of the License, or`
17			`// (at your option) any later version.`
18			`//`
19			`// This source file is distributed in the hope that it will be useful,`
20			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
21			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
22			`// GNU General Public License for more details.`
23			`//`
24			`// You should have received a copy of the GNU General Public License`
25			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
26			`//`
27			`//`
28			`//=============================================================================`
29			`//`
30	41	robfinch	`module Raptor64_shift(xIR, a, b, mask, o, rolo);`
31			`input [31:0] xIR;`
32	31	robfinch	`input [63:0] a;`
33			`input [63:0] b;`
34			`input [63:0] mask;`
35			`output [63:0] o;`
36			`reg [63:0] o;`
37	41	robfinch	`output [63:0] rolo;`
38	31	robfinch
39	41	robfinch	`wire [6:0] xOpcode = xIR[31:25];`
40			`wire [5:0] xFunc = xIR[5:0];`
41	44	robfinch	`wire [3:0] xFunc4 = xIR[3:0];`
42	31	robfinch
43			`wire [127:0] shlxo = {64'd0,a} << b[5:0];`
44			`wire [127:0] shruxo = {a,64'd0} >> b[5:0];`
45			`wire [63:0] shlo = shlxo[63:0];`
46			`wire [63:0] shruo = shruxo[127:64];`
47	41	robfinch	`assign rolo = {shlxo[127:64]\|shlxo[63:0]};`
48	31	robfinch	`wire [63:0] roro = {shruxo[127:64]\|shruxo[63:0]};`
49			`wire [63:0] shro = ~(~a >> b[5:0]);`
50
51	44	robfinch	`always @(xOpcode,xFunc,xFunc4,shlo,shruo,rolo,roro,shro,mask)`
52	31	robfinch	`case(xOpcode)`
53			`RR:
54			`case(xFunc)`
55			`SHL: o = shlo;
56	41	robfinch	`SHLU: o = shlo;
57	31	robfinch	`SHRU: o = shruo;
58			`ROL: o = rolo;
59			`ROR: o = roro;
60			`SHR: o = shro;
61			`default: o = 64'd0;`
62			`endcase`
63			`SHFTI:
64	44	robfinch	`case(xFunc4)`
65	31	robfinch	`SHLI: o = shlo;
66	41	robfinch	`SHLUI: o = shlo;
67	31	robfinch	`SHRUI: o = shruo;
68			`ROLI: o = rolo;
69			`RORI: o = roro;
70			`SHRI: o = shro;
71			`default: o = 64'd0;`
72			`endcase`
73			`default: o = 64'd0;`
74			`endcase`
75
76			`endmodule`

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[/] [raptor64/] [trunk/] [rtl/] [verilog/] [Raptor64_shift.v] - Blame information for rev 48