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[/] [raptor64/] [trunk/] [rtl/] [verilog/] [Raptor64mc.v] - Blame information for rev 21

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1 14 robfinch
// ============================================================================
2
// (C) 2012 Robert Finch
3
// All Rights Reserved.
4
// robfinch<remove>@opencores.org
5
//
6
// Raptor64.v
7
//  - 64 bit CPU
8
//
9
// This source file is free software: you can redistribute it and/or modify 
10
// it under the terms of the GNU Lesser General Public License as published 
11
// by the Free Software Foundation, either version 3 of the License, or     
12
// (at your option) any later version.                                      
13
//                                                                          
14
// This source file is distributed in the hope that it will be useful,      
15
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
16
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
17
// GNU General Public License for more details.                             
18
//                                                                          
19
// You should have received a copy of the GNU General Public License        
20
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
21 16 robfinch
//                                         
22
// 33MHz / 35000 LUTs                            
23 14 robfinch
// ============================================================================
24
//
25
`define RESET_VECTOR    64'hFFFF_FFFF_FFFF_FFF0
26
`define NMI_VECTOR              64'hFFFF_FFFF_FFFF_FFE0
27
`define IRQ_VECTOR              64'hFFFF_FFFF_FFFF_FFD0
28
`define TRAP_VECTOR             64'h0000_0000_0000_0000
29
 
30
`define TLBMissPage             52'hFFFF_FFFF_FFFF_F
31
`define ITLB_MissHandler        64'hFFFF_FFFF_FFFF_FFC0
32
`define DTLB_MissHandler        64'hFFFF_FFFF_FFFF_FFB0
33
 
34
`define GEN_TRAP_OFFSET         13'h0200
35
`define DBZ_TRAP_OFFSET         13'h0050
36
`define OFL_TRAP_OFFSET         13'h0070
37 16 robfinch
`define PRIV_OFFSET                     13'h0080
38 14 robfinch
 
39
`define EX_NON          8'd0
40
`define EX_RST          8'd1
41
`define EX_NMI          8'd2
42
`define EX_IRQ          8'd3
43
`define EX_TRAP         8'd4
44 16 robfinch
`define EX_PRIV         8'd8
45 14 robfinch
`define EX_OFL          8'd16   // overflow
46
`define EX_DBZ          8'd17   // divide by zero
47
`define EX_TLBI         8'd19   // TLB exception - ifetch
48
`define EX_TLBD         8'd20   // TLB exception - data
49
 
50
`define EXCEPT_Int              5'd00
51
`define EXCEPT_Mod              5'd01   // TLB modification
52
`define EXCEPT_TLBL             5'd02   // TLB exception - load or ifetch
53
`define EXCEPT_TLBS             5'd03   // TLB exception - store
54
`define EXCEPT_AdEL             5'd04   // Address error - load or ifetch
55
`define EXCEPT_AdES             5'd05   // Address error - store
56
`define EXCEPT_IBE              5'd06   // Bus Error - instruction fetch
57
`define EXCEPT_DBE              5'd07   // Bus Error - load or store
58
`define EXCEPT_Sys              5'd08
59
`define EXCEPT_Bp               5'd09
60
`define EXCEPT_RI               5'd10   // reserved instruction
61
`define EXCEPT_CpU              5'd11   // Coprocessor unusable
62
`define EXCEPT_Ov               5'd12   // Integer Overflow
63
`define EXCEPT_Tr               5'd13   // Trap exception
64
// 14-22 Reserved
65
`define EXCEPT_WATCH    5'd23
66
`define EXCEPT_MCheck   5'd24   // Machine check
67
// 25-31 Reserved
68
 
69
 
70
`define MISC    7'd0
71
`define         BRK             7'd0
72
`define         IRQ             7'd1
73
`define     FIP         7'd20
74
`define         IRET    7'd32
75
`define         ERET    7'd33
76
`define         WAIT    7'd40
77
`define         TLBP    7'd49
78
`define     TLBR        7'd50
79
`define     TLBWI       7'd51
80
`define     TLBWR       7'd52
81
`define         CLI             7'd64
82
`define         SEI             7'd65
83
`define R               7'd1
84
`define         COM             7'd4
85
`define         NOT             7'd5
86
`define         NEG             7'd6
87
`define         ABS             7'd7
88
`define         SWAP    7'd13
89
`define         CTLZ    7'd16
90
`define         CTLO    7'd17
91
`define         CTPOP   7'd18
92
`define         SEXT8   7'd19
93
`define         SEXT16  7'd20
94
`define         SEXT32  7'd21
95
`define         SQRT    7'd24
96
`define         REDOR   7'd30
97
`define         REDAND  7'd31
98
`define     MFSPR       7'd40
99
`define     MTSPR       7'd41
100
`define         TLBIndex        6'd01
101
`define         TLBRandom               6'd02
102
`define         PageTableAddr   6'd04
103
`define         BadVAddr        6'd08
104
`define         TLBPhysPage0    6'd10
105
`define         TLBPhysPage1    6'd11
106
`define         TLBVirtPage             6'd12
107
`define                 TLBPageMask             6'd13
108
`define                 TLBASID                 6'd14
109
`define         ASID                    6'd15
110
`define                 Wired                   6'd16
111
`define         EP0             6'd17
112
`define         EP1             6'd18
113
`define         EP2             6'd19
114
`define         EP3             6'd20
115
`define         AXC             6'd21
116
`define                 Tick                    6'd22
117
`define                 EPC                             6'd23
118
`define                 CauseCode               6'd24
119
`define                 TBA                             6'd25
120
`define         OMG             7'd50
121
`define         CMG             7'd51
122
`define         OMGI    7'd52
123
`define         CMGI    7'd53
124
`define         MFTBA   7'd58
125
`define         MTTBA   7'd59
126
`define RR      7'd2
127
`define         ADD             7'd2
128
`define         ADDU    7'd3
129
`define         SUB             7'd4
130
`define         SUBU    7'd5
131
`define         CMP             7'd6
132
`define         CMPU    7'd7
133
`define         AND             7'd8
134
`define         OR              7'd9
135
`define         XOR             7'd10
136
`define         ANDC    7'd11
137
`define         NAND    7'd12
138
`define         NOR             7'd13
139
`define         XNOR    7'd14
140
`define         ORC             7'd15
141
`define         MIN             7'd20
142
`define         MAX             7'd21
143
`define         MULU    7'd24
144
`define         MULS    7'd25
145
`define         DIVU    7'd26
146
`define         DIVS    7'd27
147
`define         MOD             7'd28
148
`define         MOVZ    7'd30
149
`define         MOVNZ   7'd31
150
 
151
`define         SHL             7'd40
152
`define         SHRU    7'd41
153
`define         ROL             7'd42
154
`define         ROR             7'd43
155
`define         SHR             7'd44
156
`define         ROLAM   7'd45
157
 
158
`define         NOP             7'd60
159
 
160
`define         SLT             7'd96
161
`define         SLE             7'd97
162
`define         SGT             7'd98
163
`define         SGE             7'd99
164
`define         SLTU    7'd100
165
`define         SLEU    7'd101
166
`define         SGTU    7'd102
167
`define         SGEU    7'd103
168
`define         SEQ             7'd104
169
`define         SNE             7'd105
170
 
171
`define     BCD_ADD     7'd110
172
`define     BCD_SUB 7'd111
173
 
174
`define SHFTI   7'd3
175
`define SHLI            7'd0
176
`define SHRUI           7'd1
177
`define ROLI            7'd2
178
`define SHRI            7'd3
179
`define RORI            7'd4
180
`define ROLAMI          7'd5
181
`define BFINS           7'd8
182
`define BFSET           7'd9
183
`define BFCLR           7'd10
184
`define BFCHG           7'd11
185
 
186
`define ADDI    7'd4
187
`define ADDUI   7'd5
188
`define SUBI    7'd6
189
`define SUBUI   7'd7
190
`define CMPI    7'd8
191
`define CMPUI   7'd9
192
`define ANDI    7'd10
193
`define ORI             7'd11
194
`define XORI    7'd12
195
 
196
`define MULUI   7'd13
197
`define MULSI   7'd14
198
`define DIVUI   7'd15
199
`define DIVSI   7'd16
200
 
201
`define TRAPcc  7'd17
202
`define         TEQ             7'd0
203
`define         TNE             7'd1
204
`define         TLT             7'd2
205
`define         TLE             7'd3
206
`define         TGT             7'd4
207
`define         TGE             7'd5
208
`define         TLO             7'd6
209
`define         TLS             7'd7
210
`define         THI             7'd8
211
`define         THS             7'd9
212
`define         TRAP    7'd10
213
`define         TRN             7'd11
214
`define TRAPcci 7'd18
215
`define         TEQI    5'd0
216
`define         TNEI    5'd1
217
`define         TLTI    5'd2
218
`define         TLEI    5'd3
219
`define         TGTI    5'd4
220
`define         TGEI    5'd5
221
`define         TLOI    5'd6
222
`define         TLSI    5'd7
223
`define         THII    5'd8
224
`define         THSI    5'd9
225
`define         TRAI    5'd10
226
`define         TRNI    5'd11
227
`define SETLO   7'b00101xx
228
`define CALL    7'd24
229
`define JMP             7'd25
230
`define JAL             7'd26
231
`define RET             7'd27
232
`define SETHI   7'b00111xx
233
 
234
`define LB              7'd32
235
`define LC              7'd33
236
`define LH              7'd34
237
`define LW              7'd35
238
`define LP              7'd36
239
`define LBU             7'd37
240
`define LCU             7'd38
241
`define LHU             7'd39
242
`define LSH             7'd40
243
`define LSW             7'd41
244
`define LF              7'd42
245
`define LFD             7'd43
246
`define LFP             7'd44
247
`define LFDP    7'd45
248
`define LWR             7'd46
249
`define LDONE   7'd47
250
 
251
`define SB              7'd48
252
`define SC              7'd49
253
`define SH              7'd50
254
`define SW              7'd51
255
`define SP              7'd52
256
`define MEMNDX  7'd53
257
`define SSH             7'd56
258
`define SSW             7'd57
259
`define SF              7'd58
260
`define SFD             7'd59
261
`define SFP             7'd60
262
`define SFDP    7'd61
263
`define SWC             7'd62
264
 
265
`define INB             7'd64
266
`define INCH    7'd65
267
`define INH             7'd66
268
`define INW             7'd67
269
`define OUTB    7'd72
270
`define OUTC    7'd73
271
`define OUTH    7'd74
272
`define OUTW    7'd75
273
 
274
`define BLTI    7'd80
275
`define BGEI    7'd81
276
`define BLEI    7'd82
277
`define BGTI    7'd83
278
`define BLTUI   7'd84
279
`define BGEUI   7'd85
280
`define BLEUI   7'd86
281
`define BGTUI   7'd87
282
`define BEQI    7'd88
283
`define BNEI    7'd89
284
`define BRAI    7'd90
285
`define BRNI    7'd91
286
 
287
`define BTRI    7'd94
288
`define         BLTRI   5'd0
289
`define         BGERI   5'd1
290
`define         BLERI   5'd2
291
`define         BGTRI   5'd3
292
`define         BLTURI  5'd4
293
`define         BGEURI  5'd5
294
`define         BLEURI  5'd6
295
`define         BGTURI  5'd7
296
`define         BEQRI   5'd8
297
`define         BNERI   5'd9
298
`define         BRARI   5'd10
299
`define         BRNRI   5'd11
300
`define         BANDRI  5'd12
301
`define         BORRI   5'd13
302
`define BTRR    7'd95
303
`define         BLT             5'd0
304
`define         BGE             5'd1
305
`define         BLE             5'd2
306
`define         BGT             5'd3
307
`define         BLTU    5'd4
308
`define         BGEU    5'd5
309
`define         BLEU    5'd6
310
`define         BGTU    5'd7
311
`define         BEQ             5'd8
312
`define         BNE             5'd9
313
`define         BRA             5'd10
314
`define         BRN             5'd11
315
`define         BAND    5'd12
316
`define         BOR             5'd13
317
`define         BNR             5'd14
318 21 robfinch
`define         LOOP    5'd15
319 14 robfinch
`define         BLTR    5'd16
320
`define         BGER    5'd17
321
`define         BLER    5'd18
322
`define         BGTR    5'd19
323
`define         BLTUR   5'd20
324
`define         BGEUR   5'd21
325
`define         BLEUR   5'd22
326
`define         BGTUR   5'd23
327
`define         BEQR    5'd24
328
`define         BNER    5'd25
329
`define         BRAR    5'd26
330
`define         BRNR    5'd27
331
 
332
 
333
`define SLTI    7'd96
334
`define SLEI    7'd97
335
`define SGTI    7'd98
336
`define SGEI    7'd99
337
`define SLTUI   7'd100
338
`define SLEUI   7'd101
339
`define SGTUI   7'd102
340
`define SGEUI   7'd103
341
`define SEQI    7'd104
342
`define SNEI    7'd105
343
 
344
`define FPLOO   7'd109
345
`define FPZL    7'd110
346
`define NOPI    7'd111
347
 
348
`define IMM             3'd7
349
 
350
`define NOP_INSN        42'b1101111_000_00000000_00000000_00000000_00000000
351
 
352
module Raptor64mc(rst_i, clk_i, nmi_i, irq_i,
353
        bte_o, cti_o, cyc_o, stb_o, ack_i, we_o, sel_o, rsv_o, adr_o, dat_i, dat_o, sys_adv, sys_adr,
354
        cmd_en, cmd_instr, cmd_bl, cmd_byte_addr, cmd_full,
355
        wr_en, wr_data, wr_mask, wr_full, wr_empty,
356
        rd_en, rd_data, rd_empty
357
);
358
parameter IDLE = 5'd1;
359
parameter ICACT = 5'd2;
360
parameter ICACT0 = 5'd3;
361
parameter ICACT1 = 5'd4;
362
parameter ICACT2 = 5'd5;
363
parameter ICACT3 = 5'd6;
364
parameter ICACT4 = 5'd7;
365
parameter ICACT5 = 5'd8;
366
parameter ICACT6 = 5'd9;
367
parameter ICACT7 = 5'd10;
368
parameter ICDLY = 5'd11;
369
parameter DCIDLE = 5'd20;
370
parameter DCACT = 5'd21;
371
parameter DCACT0 = 5'd22;
372
parameter DCACT1 = 5'd23;
373
parameter DCACT2 = 5'd24;
374
parameter DCACT3 = 5'd25;
375
parameter DCACT4 = 5'd26;
376
parameter DCACT5 = 5'd27;
377
parameter DCACT6 = 5'd28;
378
parameter DCACT7 = 5'd29;
379
parameter DCDLY = 5'd30;
380
 
381
input rst_i;
382
input clk_i;
383
input nmi_i;
384
input irq_i;
385
 
386
output [1:0] bte_o;
387
reg [1:0] bte_o;
388
output [2:0] cti_o;
389
reg [2:0] cti_o;
390
output cyc_o;
391
reg cyc_o;
392
output stb_o;
393
reg stb_o;
394
input ack_i;
395
output we_o;
396
reg we_o;
397
output [3:0] sel_o;
398
reg [3:0] sel_o;
399
output rsv_o;
400
reg rsv_o;
401
output [31:0] adr_o;
402
reg [31:0] adr_o;
403
input [31:0] dat_i;
404
output [31:0] dat_o;
405
reg [31:0] dat_o;
406
 
407
input sys_adv;
408
input [63:5] sys_adr;
409
 
410
output cmd_en;
411
reg cmd_en;
412
output [2:0] cmd_instr;
413
reg [2:0] cmd_instr;
414
output [5:0] cmd_bl;
415
reg [5:0] cmd_bl;
416
output [29:0] cmd_byte_addr;
417
reg [29:0] cmd_byte_addr;
418
input cmd_full;
419
output wr_en;
420
reg wr_en;
421
output [31:0] wr_data;
422
reg [31:0] wr_data;
423
output [3:0] wr_mask;
424
reg [3:0] wr_mask;
425
input wr_full;
426
input wr_empty;
427
output rd_en;
428
reg rd_en;
429
input [31:0] rd_data;
430
input rd_empty;
431
 
432
reg resetA;
433
reg im;                         // interrupt mask
434
reg [1:0] rm;            // fp rounding mode
435
reg [41:0] dIR;
436
reg [41:0] xIR;
437
reg [4:0] epcnt;
438
reg [3:0] dAXC,AXC,xAXC,m1AXC,m2AXC,m3AXC,m4AXC,wAXC;
439
reg [31:0] EP [3:0];
440
reg [63:0] pc [15:0];
441
reg [63:0] ErrorEPC,EPC[15:0],IPC[15:0];
442
wire [63:0] pc_axc = pc[AXC];
443
reg [63:0] dpc,m1pc,m2pc,m3pc,m4pc,wpc;
444
reg [63:0] xpc;
445
reg [63:0] tlbra;                // return address for a TLB exception
446
reg [8:0] dRa,dRb,dRc;
447
reg [8:0] wRt,mRt,m1Rt,m2Rt,m3Rt,m4Rt,tRt,dRt;
448
reg [8:0] xRt;
449
reg [63:0] dImm;
450
reg [63:0] ea;
451
reg [63:0] iadr_o;
452
reg [31:0] idat;
453
reg [4:0] cstate;
454
reg dbranch_taken,xbranch_taken;
455
reg [63:0] mutex_gate;
456
reg [63:0] TBA;
457
 
458
//reg wr_icache;
459
reg dccyc;
460
wire [63:0] cdat;
461
reg [63:0] wr_addr;
462
wire [41:0] insn;
463
reg [3:0] regset;
464
wire [63:0] rfoa,rfob;
465
reg clk_en;
466
reg cpu_clk_en;
467
reg [15:0] StatusERL;            // 1= in error processing
468
reg [15:0] StatusEXL;            // 1= in exception processing
469
reg [15:0] StatusHWI;
470
reg [7:0] CauseCode[15:0];
471
reg [7:0] ASID;          // address space identifier (process ID)
472
integer n;
473
reg [63:13] BadVAddr [15:0];
474
reg [63:13] PageTableAddr;
475
 
476
function [63:0] fnIncPC;
477
input [63:0] fpc;
478
begin
479
case(fpc[3:2])
480
2'd0:   fnIncPC = {fpc[63:4],4'b0100};
481
2'd1:   fnIncPC = {fpc[63:4],4'b1000};
482
2'd2:   fnIncPC = {fpc[63:4]+60'd1,4'b0000};
483
2'd3:   fnIncPC = {fpc[63:4]+60'd1,4'b0000};
484
endcase
485
end
486
endfunction
487
 
488 16 robfinch
function [3:0] fnSel4;
489
input [63:0] ad;
490
begin
491
case(ad[1:0])
492
2'd0:   fnSel4 = 4'b0001;
493
2'd1:   fnSel4 = 4'b0010;
494
2'd2:   fnSel4 = 4'b0100;
495
2'd3:   fnSel4 = 4'b1000;
496
endcase
497
end
498
endfunction
499
 
500
function [3:0] fnSel2;
501
input [63:0] ad;
502
begin
503
case(ad[1:0])
504
2'd0:   fnSel2 = 4'b0011;
505
2'd1:   fnSel2 = 4'b0110;
506
2'd2:   fnSel2 = 4'b1100;
507
2'd3:   fnSel2 = 4'b1000;
508
endcase
509
end
510
endfunction
511
 
512
function [3:0] fnSel1;
513
input [63:0] ad;
514
begin
515
case(ad[1:0])
516
2'd0:   fnSel1 = 4'b1111;
517
2'd1:   fnSel1 = 4'b1110;
518
2'd2:   fnSel1 = 4'b1100;
519
2'd3:   fnSel1 = 4'b1000;
520
endcase
521
end
522
endfunction
523
 
524
 
525 14 robfinch
wire xKernelMode = StatusEXL[xAXC];
526
 
527
//-----------------------------------------------------------------------------
528
// TLB stuff
529
//-----------------------------------------------------------------------------
530
 
531
reg [24:13] TLBPageMask;
532
reg [63:13] TLBVirtPage;
533
reg [63:13] TLBPhysPage0;
534
reg [63:13] TLBPhysPage1;
535
reg [7:0] TLBASID;
536
reg TLBG,TLBD,TLBValid;
537 16 robfinch
reg [31:0] Index;
538 14 robfinch
reg [3:0] Random;
539
reg [3:0] Wired;
540
 
541
reg [15:0] IMatch,DMatch;
542
reg [4:0] m,q;
543
reg [3:0] i;
544
reg [31:13] tTLBPageMask [15:0];
545
reg [63:13] tTLBVirtPage [15:0];
546
reg [63:13] tTLBPhysPage0 [15:0];
547
reg [63:13] tTLBPhysPage1 [15:0];
548
reg [15:0] tTLBG;
549
reg [15:0] tTLBD;
550
reg [7:0] tTLBASID [15:0];
551
reg [15:0] tTLBValid;
552
initial begin
553
        for (n = 0; n < 16; n = n + 1)
554
        begin
555
                tTLBPageMask[n] = 0;
556
                tTLBVirtPage[n] = 0;
557
                tTLBPhysPage0[n] = 0;
558
                tTLBPhysPage1[n] = 0;
559
                tTLBG[n] = 0;
560
                tTLBD[n] = 0;
561
                tTLBASID[n] = 0;
562
                tTLBValid[n] = 0;
563
        end
564
end
565
always @*
566
for (n = 0; n < 16; n = n + 1)
567
begin
568
        IMatch[n] = ((pc_axc[63:13]|tTLBPageMask[n])==(tTLBVirtPage[n]|tTLBPageMask[n])) &&
569
                                ((tTLBASID[n]==ASID) || tTLBG[n]) &&
570
                                tTLBValid[n];
571
        DMatch[n] = ((ea[63:13]|tTLBPageMask[n])==(tTLBVirtPage[n]|tTLBPageMask[n])) &&
572
                                ((tTLBASID[n]==ASID) || tTLBG[n]) &&
573
                                tTLBValid[n];
574
end
575
always @(IMatch)
576
if (IMatch[0]) m <= 5'd0;
577
else if (IMatch[1]) m <= 5'd1;
578
else if (IMatch[2]) m <= 5'd2;
579
else if (IMatch[3]) m <= 5'd3;
580
else if (IMatch[4]) m <= 5'd4;
581
else if (IMatch[5]) m <= 5'd5;
582
else if (IMatch[6]) m <= 5'd6;
583
else if (IMatch[7]) m <= 5'd7;
584
else if (IMatch[8]) m <= 5'd8;
585
else if (IMatch[9]) m <= 5'd9;
586
else if (IMatch[10]) m <= 5'd10;
587
else if (IMatch[11]) m <= 5'd11;
588
else if (IMatch[12]) m <= 5'd12;
589
else if (IMatch[13]) m <= 5'd13;
590
else if (IMatch[14]) m <= 5'd14;
591
else if (IMatch[15]) m <= 5'd15;
592
else m <= 5'd31;
593
 
594
wire ioddpage = |({tTLBPageMask[m]+19'd1,13'd0}&pc_axc);
595
wire [63:13] IPFN = ioddpage ? tTLBPhysPage1[m] : tTLBPhysPage0[m];
596
 
597
wire unmappedArea = pc_axc[63:52]==12'hFFD || pc_axc[63:52]==12'hFFE || pc_axc[63:52]==12'hFFF;
598
wire [63:0] ppc;
599
wire ITLBMiss = !unmappedArea & m[4];
600
 
601
assign ppc[63:13] = unmappedArea ? pc_axc[63:13] : m[4] ? `TLBMissPage: IPFN;
602
assign ppc[12:0] = pc_axc[12:0];
603
 
604
always @(DMatch)
605
if (DMatch[0]) q <= 5'd0;
606
else if (DMatch[1]) q <= 5'd1;
607
else if (DMatch[2]) q <= 5'd2;
608
else if (DMatch[3]) q <= 5'd3;
609
else if (DMatch[4]) q <= 5'd4;
610
else if (DMatch[5]) q <= 5'd5;
611
else if (DMatch[6]) q <= 5'd6;
612
else if (DMatch[7]) q <= 5'd7;
613
else if (DMatch[8]) q <= 5'd8;
614
else if (DMatch[9]) q <= 5'd9;
615
else if (DMatch[10]) q <= 5'd10;
616
else if (DMatch[11]) q <= 5'd11;
617
else if (DMatch[12]) q <= 5'd12;
618
else if (DMatch[13]) q <= 5'd13;
619
else if (DMatch[14]) q <= 5'd14;
620
else if (DMatch[15]) q <= 5'd15;
621
else q <= 5'd31;
622
 
623
wire doddpage = |({tTLBPageMask[q]+19'd1,13'd0}&ea);
624
wire [63:13] DPFN = doddpage ? tTLBPhysPage1[q] : tTLBPhysPage0[q];
625
 
626
reg m1UnmappedDataArea;
627
wire unmappedDataArea = ea[63:52]==12'hFFD || ea[63:52]==12'hFFE || ea[63:52]==12'hFFF;
628
wire DTLBMiss = !unmappedDataArea & q[4];
629
 
630
wire [63:0] pea;
631
assign pea[63:13] = unmappedDataArea ? ea[63:13] : q[4] ? `TLBMissPage: DPFN;
632
assign pea[12:0] = ea[12:0];
633
 
634 16 robfinch
wire m1DRAMBus = !pea[63];
635
wire m2DRAMBus = !m2Addr[63];
636
wire m3DRAMBus = !m3Addr[63];
637
wire m4DRAMBus = !m4Addr[63];
638
 
639 14 robfinch
//-----------------------------------------------------------------------------
640
// Clock control
641
// - reset or NMI reenables the clock
642
// - this circuit must be under the clk_i domain
643
//-----------------------------------------------------------------------------
644
//
645
BUFGCE u20 (.CE(cpu_clk_en), .I(clk_i), .O(clk) );
646
 
647
always @(posedge clk_i)
648
if (rst_i) begin
649
        cpu_clk_en <= 1'b1;
650
end
651
else begin
652
        if (nmi_i)
653
                cpu_clk_en <= 1'b1;
654
        else
655
                cpu_clk_en <= clk_en;
656
end
657
 
658
//-----------------------------------------------------------------------------
659
// Instruction Cache
660
// 8kB
661
// 
662
//-----------------------------------------------------------------------------
663
reg icaccess, iciaccess;
664
wire wr_icache = (!rd_empty & icaccess) | (iciaccess & ack_i);
665
 
666
Raptor64_icache_ram_x32 u1
667
(
668
        .clk(clk),
669
        .wr(wr_icache),
670
        .adr_i(iadr_o[12:0]),
671
        .dat_i(icaccess ?rd_data : dat_i),
672
        .pc(pc_axc),
673
        .insn(insn)
674
);
675
 
676
reg [63:13] tmem [127:0];
677
reg [127:0] tvalid;
678
 
679
initial begin
680
        for (n=0; n < 128; n = n + 1)
681
                tmem[n] = 0;
682
        for (n=0; n < 128; n = n + 1)
683
                tvalid[n] = 0;
684
end
685
 
686
wire [64:13] tgout;
687
assign tgout = {tvalid[pc_axc[12:6]],tmem[pc_axc[12:6]]};
688
assign ihit = (tgout=={1'b1,ppc[63:13]});
689
 
690
 
691
//-----------------------------------------------------------------------------
692
// Data Cache
693
// No-allocate on write
694
//-----------------------------------------------------------------------------
695
reg dcaccess;
696
wire dhit;
697
wire [13:0] dtign;
698
wire [64:14] dtgout;
699
reg wrhit;
700
reg [7:0] dsel_o;
701
reg [63:0] dadr_o;
702
reg [31:0] ddat;
703
reg wr_dcache;
704
 
705
// cache RAM 16Kb
706
Raptor64mc_dcache_ram u10
707
(
708
        .clka(~clk),
709
        .wea(8'h00),
710
        .addra(pea[13:3]),
711
        .dina(64'h0000),
712
        .douta(cdat),
713
 
714
        .clkb(clk),
715
        .web(dcaccess ? {4{wr_dcache}} : wrhit & wr_en ? ~wr_mask : 4'b0000),
716
        .addrb(dcaccess ? dadr_o[13:2] : wr_addr[13:2]),
717
        .dinb(dcaccess ? ddat : wr_data),
718
        .doutb()
719
);
720
 
721
// tag ram
722
syncRam512x64_1rw1r u11
723
(
724
        .wrst(1'b0),
725
        .wclk(clk),
726
        .wce(dadr_o[4:2]==3'b111),
727
        .we(wr_dcache),
728
        .wadr(dadr_o[13:5]),
729
        .i({14'h3FFF,dadr_o[63:14]}),
730
        .wo(),
731
 
732
        .rrst(1'b0),
733
        .rclk(~clk),
734
        .rce(1'b1),
735
        .radr(pea[13:5]),
736
        .ro({dtign,dtgout})
737
);
738
 
739
assign dhit = (dtgout=={1'b1,pea[63:14]});
740
 
741
//-----------------------------------------------------------------------------
742
//-----------------------------------------------------------------------------
743
 
744
reg [64:0] xData;
745
wire xisCacheElement = xData[63:52] != 12'hFFD;
746
reg m1IsCacheElement;
747
 
748
reg nopI;
749
wire [6:0] iFunc = insn[6:0];
750
wire [6:0] dFunc = dIR[6:0];
751
wire [6:0] xFunc = xIR[6:0];
752
wire [6:0] iOpcode = insn[41:35];
753
wire [6:0] xOpcode = xIR[41:35];
754
wire [6:0] dOpcode = dIR[41:35];
755
reg [6:0] m1Opcode,m2Opcode,m3Opcode,m4Opcode;
756
reg [6:0] m1Func,m2Func,m3Func,m4Func;
757
reg [63:0] m1Data,m2Data,m3Data,m4Data,wData,tData;
758
reg [63:0] m2Addr,m3Addr,m4Addr;
759
reg [63:0] tick;
760
reg [63:0] tba;
761
reg [63:0] exception_address,ipc;
762 16 robfinch
reg [63:0] a,b,c,imm,m1b,m2b,m3b;
763 14 robfinch
reg prev_ihit;
764
reg rsf;
765
reg [63:5] resv_address;
766
reg [15:0] dirqf;
767
reg rirqf,m1irqf,m2irqf,m3irqf,m4irqf,wirqf,tirqf;
768
reg xirqf;
769
reg [7:0] dextype,m1extype,m2extype,m3extype,m4extype,wextype,textype,exception_type;
770
reg [7:0] xextype;
771
wire advanceX_edge;
772
reg takb;
773
 
774
wire [127:0] mult_out;
775
wire [63:0] sqrt_out;
776
wire [63:0] div_q;
777
wire [63:0] div_r;
778
wire sqrt_done,mult_done,div_done;
779
wire isSqrt = xOpcode==`R && xFunc==`SQRT;
780
wire [7:0] bcdaddo,bcdsubo;
781
 
782
BCDAdd u40(.ci(1'b0),.a(a[7:0]),.b(b[7:0]),.o(bcdaddo),.c());
783
BCDSub u41(.ci(1'b0),.a(a[7:0]),.b(b[7:0]),.o(bcdsubo),.c());
784
 
785
isqrt #(64) u14
786
(
787
        .rst(rst_i),
788
        .clk(clk),
789
        .ce(1'b1),
790
        .ld(isSqrt),
791
        .a(a),
792
        .o(sqrt_out),
793
        .done(sqrt_done)
794
);
795
 
796
wire isMulu = xOpcode==`RR && xFunc==`MULU;
797
wire isMuls = (xOpcode==`RR && xFunc==`MULS) || xOpcode==`MULSI;
798
wire isMuli = xOpcode==`MULSI || xOpcode==`MULUI;
799
wire isMult = xOpcode==`MULSI || xOpcode==`MULUI || (xOpcode==`RR && (xFunc==`MULS || xFunc==`MULU));
800
wire isDivu = xOpcode==`RR && xFunc==`DIVU;
801
wire isDivs = (xOpcode==`RR && xFunc==`DIVS) || xOpcode==`DIVSI;
802
wire isDivi = xOpcode==`DIVSI || xOpcode==`DIVUI;
803
wire isDiv = xOpcode==`DIVSI || xOpcode==`DIVUI || (xOpcode==`RR && (xFunc==`DIVS || xFunc==`DIVU));
804
 
805
wire disRRShift = dOpcode==`RR && (
806
        dFunc==`SHL || dFunc==`ROL || dFunc==`SHR ||
807
        dFunc==`SHRU || dFunc==`ROR || dFunc==`ROLAM
808
        );
809
wire disRightShift = dOpcode==`RR && (
810
        dFunc==`SHR || dFunc==`SHRU || dFunc==`ROR
811
        );
812
 
813
Raptor64Mult u18
814
(
815
        .rst(rst_i),
816
        .clk(clk),
817
        .ld(isMult),
818
        .sgn(isMuls),
819
        .isMuli(isMuli),
820
        .a(a),
821
        .b(b),
822
        .imm(imm),
823
        .o(mult_out),
824
        .done(mult_done)
825
);
826
 
827
Raptor64Div u19
828
(
829
        .rst(rst_i),
830
        .clk(clk),
831
        .ld(isDiv),
832
        .sgn(isDivs),
833
        .isDivi(isDivi),
834
        .a(a),
835
        .b(b),
836
        .imm(imm),
837
        .qo(div_q),
838
        .ro(div_r),
839
        .dvByZr(),
840
        .done(div_done)
841
);
842
 
843
wire [63:0] fpZLOut;
844
wire [63:0] fpLooOut;
845
wire fpLooDone;
846
 
847
fpZLUnit #(64) u30
848
(
849
        .op(xFunc[5:0]),
850
        .a(a),
851
        .b(b),  // for fcmp
852
        .o(fpZLOut),
853
        .nanx()
854
);
855
 
856
fpLOOUnit #(64) u31
857
(
858
        .clk(clk),
859
        .ce(1'b1),
860
        .rm(rm),
861
        .op(xFunc[5:0]),
862
        .a(a),
863
        .o(fpLooOut),
864
        .done(fpLooDone)
865
);
866
 
867
function [2:0] popcnt6;
868
input [5:0] a;
869
begin
870
case(a)
871
6'b000000:      popcnt6 = 3'd0;
872
6'b000001:      popcnt6 = 3'd1;
873
6'b000010:      popcnt6 = 3'd1;
874
6'b000011:      popcnt6 = 3'd2;
875
6'b000100:      popcnt6 = 3'd1;
876
6'b000101:      popcnt6 = 3'd2;
877
6'b000110:      popcnt6 = 3'd2;
878
6'b000111:      popcnt6 = 3'd3;
879
6'b001000:      popcnt6 = 3'd1;
880
6'b001001:      popcnt6 = 3'd2;
881
6'b001010:      popcnt6 = 3'd2;
882
6'b001011:      popcnt6 = 3'd3;
883
6'b001100:      popcnt6 = 3'd2;
884
6'b001101:      popcnt6 = 3'd3;
885
6'b001110:      popcnt6 = 3'd3;
886
6'b001111:  popcnt6 = 3'd4;
887
6'b010000:      popcnt6 = 3'd1;
888
6'b010001:      popcnt6 = 3'd2;
889
6'b010010:  popcnt6 = 3'd2;
890
6'b010011:      popcnt6 = 3'd3;
891
6'b010100:  popcnt6 = 3'd2;
892
6'b010101:  popcnt6 = 3'd3;
893
6'b010110:  popcnt6 = 3'd3;
894
6'b010111:      popcnt6 = 3'd4;
895
6'b011000:      popcnt6 = 3'd2;
896
6'b011001:      popcnt6 = 3'd3;
897
6'b011010:      popcnt6 = 3'd3;
898
6'b011011:      popcnt6 = 3'd4;
899
6'b011100:      popcnt6 = 3'd3;
900
6'b011101:      popcnt6 = 3'd4;
901
6'b011110:      popcnt6 = 3'd4;
902
6'b011111:      popcnt6 = 3'd5;
903
6'b100000:      popcnt6 = 3'd1;
904
6'b100001:      popcnt6 = 3'd2;
905
6'b100010:      popcnt6 = 3'd2;
906
6'b100011:      popcnt6 = 3'd3;
907
6'b100100:      popcnt6 = 3'd2;
908
6'b100101:      popcnt6 = 3'd3;
909
6'b100110:      popcnt6 = 3'd3;
910
6'b100111:      popcnt6 = 3'd4;
911
6'b101000:      popcnt6 = 3'd2;
912
6'b101001:      popcnt6 = 3'd3;
913
6'b101010:      popcnt6 = 3'd3;
914
6'b101011:      popcnt6 = 3'd4;
915
6'b101100:      popcnt6 = 3'd3;
916
6'b101101:      popcnt6 = 3'd4;
917
6'b101110:      popcnt6 = 3'd4;
918
6'b101111:      popcnt6 = 3'd5;
919
6'b110000:      popcnt6 = 3'd2;
920
6'b110001:      popcnt6 = 3'd3;
921
6'b110010:      popcnt6 = 3'd3;
922
6'b110011:      popcnt6 = 3'd4;
923
6'b110100:      popcnt6 = 3'd3;
924
6'b110101:      popcnt6 = 3'd4;
925
6'b110110:      popcnt6 = 3'd4;
926
6'b110111:      popcnt6 = 3'd5;
927
6'b111000:      popcnt6 = 3'd3;
928
6'b111001:      popcnt6 = 3'd4;
929
6'b111010:      popcnt6 = 3'd4;
930
6'b111011:      popcnt6 = 3'd5;
931
6'b111100:      popcnt6 = 3'd4;
932
6'b111101:      popcnt6 = 3'd5;
933
6'b111110:      popcnt6 = 3'd5;
934
6'b111111:      popcnt6 = 3'd6;
935
endcase
936
end
937
endfunction
938
 
939
wire [63:0] jmp_tgt = dOpcode[6:4]==`IMM ? {dIR[26:0],insn[34:0],2'b00} : {pc_axc[63:37],insn[34:0],2'b00};
940
 
941
//-----------------------------------------------------------------------------
942
// Branch history table.
943
// The history table is updated by the EX stage and read in
944
// both the EX and IF stages.
945
// A separate global branch history is kept for each context.
946
//-----------------------------------------------------------------------------
947
reg [2:0] gbl_branch_hist [15:0];
948
reg [1:0] branch_history_table [511:0];
949
wire [7:0] bht_wa = {xpc[6:0],gbl_branch_hist[xAXC][2:1]};                // write address
950
wire [7:0] bht_ra1 = {xpc[6:0],gbl_branch_hist[xAXC][2:1]};               // read address (EX stage)
951
wire [7:0] bht_ra2 = {pc_axc[6:0],gbl_branch_hist[AXC][2:1]};     // read address (IF stage)
952
wire [1:0] bht_xbits = branch_history_table[bht_ra1];
953
wire [1:0] bht_ibits = branch_history_table[bht_ra2];
954
wire predict_taken = bht_ibits==2'd0 || bht_ibits==2'd1;
955
 
956
wire isxBranchI = (xOpcode==`BRAI || xOpcode==`BRNI || xOpcode==`BEQI || xOpcode==`BNEI ||
957
                                        xOpcode==`BLTI || xOpcode==`BLEI || xOpcode==`BGTI || xOpcode==`BGEI ||
958
                                        xOpcode==`BLTUI || xOpcode==`BLEUI || xOpcode==`BGTUI || xOpcode==`BGEUI)
959
                                ;
960
wire isxBranch = isxBranchI || xOpcode==`TRAPcc || xOpcode==`TRAPcci || xOpcode==`BTRI || xOpcode==`BTRR;
961
 
962
reg [1:0] xbits_new;
963
 
964
always @(takb or bht_xbits)
965
if (takb) begin
966
        if (bht_xbits != 2'd1)
967
                xbits_new <= bht_xbits + 2'd1;
968
        else
969
                xbits_new <= bht_xbits;
970
end
971
else begin
972
        if (bht_xbits != 2'd2)
973
                xbits_new <= bht_xbits - 2'd1;
974
        else
975
                xbits_new <= bht_xbits;
976
end
977
 
978
// For simulation only, initialize the history table to zeros.
979
// In the real world we don't care.
980
initial begin
981
        for (n = 0; n < 256; n = n + 1)
982
                branch_history_table[n] = 0;
983
end
984
 
985
//-----------------------------------------------------------------------------
986
// Evaluate branch conditions.
987
//-----------------------------------------------------------------------------
988
wire signed [63:0] as = a;
989
wire signed [63:0] bs = b;
990
wire signed [63:0] imms = imm;
991
wire aeqz = a==64'd0;
992
wire beqz = b==64'd0;
993
wire immeqz = imm==64'd0;
994
wire eq = a==b;
995
wire eqi = a==imm;
996
wire lt = as < bs;
997
wire lti = as < imms;
998
wire ltu = a < b;
999
wire ltui = a < imm;
1000
 
1001
always @(xOpcode or xFunc or a or eq or eqi or lt or lti or ltu or ltui or aeqz or beqz or rsf or xIR)
1002
case (xOpcode)
1003
`BTRR:
1004
        case(xFunc)
1005
        `BRA:   takb = 1'b1;
1006
        `BRN:   takb = 1'b0;
1007
        `BEQ:   takb = eq;
1008
        `BNE:   takb = !eq;
1009
        `BLT:   takb = lt;
1010
        `BLE:   takb = lt|eq;
1011
        `BGT:   takb = !(lt|eq);
1012
        `BGE:   takb = !lt;
1013
        `BLTU:  takb = ltu;
1014
        `BLEU:  takb = ltu|eq;
1015
        `BGTU:  takb = !(ltu|eq);
1016
        `BGEU:  takb = !ltu;
1017
        `BOR:   takb = !aeqz || !beqz;
1018
        `BAND:  takb = !aeqz && !beqz;
1019
        `BNR:   takb = !rsf;
1020
        `BEQR:  takb = eq;
1021
        `BNER:  takb = !eq;
1022
        `BLTR:  takb = lt;
1023
        `BLER:  takb = lt|eq;
1024
        `BGTR:  takb = !(lt|eq);
1025
        `BGER:  takb = !lt;
1026
        `BLTUR: takb = ltu;
1027
        `BLEUR: takb = ltu|eq;
1028
        `BGTUR: takb = !(ltu|eq);
1029
        `BGEUR: takb = !ltu;
1030
        default:        takb = 1'b0;
1031
        endcase
1032
`BRAI:  takb = 1'b1;
1033
`BRNI:  takb = 1'b0;
1034
`BEQI:  takb = eqi;
1035
`BNEI:  takb = !eqi;
1036
`BLTI:  takb = lti;
1037
`BLEI:  takb = lti|eqi;
1038
`BGTI:  takb = !(lti|eqi);
1039
`BGEI:  takb = !lti;
1040
`BLTUI: takb = ltui;
1041
`BLEUI: takb = ltui|eqi;
1042
`BGTUI: takb = !(ltui|eqi);
1043
`BGEUI: takb = !ltui;
1044
`BTRI:
1045
        case(xIR[24:18])
1046
        `BRA:   takb = 1'b1;
1047
        `BRN:   takb = 1'b0;
1048
        `BEQ:   takb = eqi;
1049
        `BNE:   takb = !eqi;
1050
        `BLT:   takb = lti;
1051
        `BLE:   takb = lti|eqi;
1052
        `BGT:   takb = !(lti|eqi);
1053
        `BGE:   takb = !lti;
1054
        `BLTU:  takb = ltui;
1055
        `BLEU:  takb = ltui|eqi;
1056
        `BGTU:  takb = !(ltui|eqi);
1057
        `BGEU:  takb = !ltui;
1058
        default:        takb = 1'b0;
1059
        endcase
1060
`TRAPcc:
1061
        case(xFunc)
1062
        `TEQ:   takb = eq;
1063
        `TNE:   takb = !eq;
1064
        `TLT:   takb = lt;
1065
        `TLE:   takb = lt|eq;
1066
        `TGT:   takb = !(lt|eq);
1067
        `TGE:   takb = !lt;
1068
        `TLO:   takb = ltu;
1069
        `TLS:   takb = ltu|eq;
1070
        `THI:   takb = !(ltu|eq);
1071
        `THS:   takb = !ltu;
1072
        default:        takb = 1'b0;
1073
        endcase
1074
`TRAPcci:
1075
        case(xIR[29:25])
1076
        `TEQI:  takb = eqi;
1077
        `TNEI:  takb = !eqi;
1078
        `TLTI:  takb = lti;
1079
        `TLEI:  takb = lti|eqi;
1080
        `TGTI:  takb = !(lti|eqi);
1081
        `TGEI:  takb = !lti;
1082
        `TLOI:  takb = ltui;
1083
        `TLSI:  takb = ltui|eqi;
1084
        `THII:  takb = !(ltui|eqi);
1085
        `THSI:  takb = !ltui;
1086
        default:        takb = 1'b0;
1087
        endcase
1088
default:
1089
        takb = 1'b0;
1090
endcase
1091
 
1092
 
1093
//-----------------------------------------------------------------------------
1094
// Datapath (ALU) operations.
1095
//-----------------------------------------------------------------------------
1096
wire [6:0] cntlzo,cntloo;
1097
cntlz64 u12 ( .i(a),  .o(cntlzo) );
1098
cntlo64 u13 ( .i(a),  .o(cntloo) );
1099
 
1100
reg [1:0] shftop;
1101
wire [63:0] shfto;
1102
always @(xFunc)
1103
        if (xFunc==`SHL)
1104
                shftop = 2'b00;
1105
        else if (xFunc==`ROL || xFunc==`ROR)
1106
                shftop = 2'b01;
1107
        else if (xFunc==`SHRU)
1108
                shftop = 2'b10;
1109
        else if (xFunc==`SHR)
1110
                shftop = 2'b11;
1111
        else
1112
                shftop = 2'b01;
1113
 
1114
wire [63:0] masko;
1115
shiftAndMask u15
1116
(
1117
        .op(shftop),
1118
        .oz(1'b0),              // zero the output
1119
        .a(a),
1120
        .b(b[5:0]),
1121
        .mb(xIR[12:7]),
1122
        .me(xIR[18:13]),
1123
        .o(shfto),
1124
        .mo(masko)
1125
);
1126
 
1127
always @(xOpcode or xFunc or a or b or imm or as or bs or imms or xpc or
1128
        sqrt_out or cntlzo or cntloo or tick or ipc or tba or regset or
1129
        lt or eq or ltu or mult_out or lti or eqi or ltui or xIR or div_q or div_r or
1130
        shfto or masko or bcdaddo or bcdsubo or fpLooOut or fpZLOut or
1131
        Wired or Index or Random or TLBPhysPage0 or TLBPhysPage1 or TLBVirtPage or TLBASID or
1132
        PageTableAddr or BadVAddr or ASID or TLBPageMask
1133
)
1134 16 robfinch
casex(xOpcode)
1135 14 robfinch
`R:
1136
        casex(xFunc)
1137
        `SETLO: xData = imm;
1138
        `SETHI: xData = {imm[63:32],a[31:0]};
1139
        `COM:   xData = ~a;
1140
        `NOT:   xData = ~|a;
1141
        `NEG:   xData = -a;
1142
        `ABS:   xData = a[63] ? -a : a;
1143
        `SQRT:  xData = sqrt_out;
1144
        `SWAP:  xData = {a[31:0],a[63:32]};
1145
 
1146
        `REDOR:         xData = |a;
1147
        `REDAND:        xData = &a;
1148
 
1149
        `CTLZ:  xData = cntlzo;
1150
        `CTLO:  xData = cntloo;
1151
        `CTPOP: xData = {4'd0,popcnt6(a[5:0])} +
1152
                                        {4'd0,popcnt6(a[11:6])} +
1153
                                        {4'd0,popcnt6(a[17:12])} +
1154
                                        {4'd0,popcnt6(a[23:18])} +
1155
                                        {4'd0,popcnt6(a[29:24])} +
1156
                                        {4'd0,popcnt6(a[35:30])} +
1157
                                        {4'd0,popcnt6(a[41:36])} +
1158
                                        {4'd0,popcnt6(a[47:42])} +
1159
                                        {4'd0,popcnt6(a[53:48])} +
1160
                                        {4'd0,popcnt6(a[59:54])} +
1161
                                        {4'd0,popcnt6(a[63:60])}
1162
                                        ;
1163
        `SEXT8:         xData = {{56{a[7]}},a[7:0]};
1164
        `SEXT16:        xData = {{48{a[15]}},a[15:0]};
1165
        `SEXT32:        xData = {{32{a[31]}},a[31:0]};
1166
 
1167
        `MFSPR:
1168
                case(xIR[12:7])
1169
                `Wired:                 xData = Wired;
1170
                `TLBIndex:              xData = Index;
1171
                `TLBRandom:             xData = Random;
1172
                `TLBPhysPage0:  xData = {TLBPhysPage0,13'd0};
1173
                `TLBPhysPage1:  xData = {TLBPhysPage1,13'd0};
1174
                `TLBVirtPage:   xData = {TLBVirtPage,13'd0};
1175
                `TLBPageMask:   xData = {TLBPageMask,13'd0};
1176
                `TLBASID:               begin
1177
                                                xData[0] = TLBValid;
1178
                                                xData[1] = TLBD;
1179
                                                xData[2] = TLBG;
1180
                                                xData[15:8] = TLBASID;
1181
                                                end
1182
                `PageTableAddr: xData = {PageTableAddr,13'd0};
1183
                `BadVAddr:              xData = {BadVAddr[xAXC],13'd0};
1184
                `ASID:                  xData = ASID;
1185
                `EP0:                   xData = EP[0];
1186
                `EP1:                   xData = EP[1];
1187
                `EP2:                   xData = EP[2];
1188
                `EP3:                   xData = EP[3];
1189
                `AXC:                   xData = xAXC;
1190
                `Tick:                  xData = tick;
1191
                `EPC:                   xData = EPC[xAXC];
1192
                `CauseCode:             xData = CauseCode[xAXC];
1193
                `TBA:                   xData = TBA;
1194
                default:        xData = 65'd0;
1195
                endcase
1196
        `OMG:           xData = mutex_gate[a[5:0]];
1197
        `CMG:           xData = mutex_gate[a[5:0]];
1198
        `OMGI:          xData = mutex_gate[xIR[12:7]];
1199
        `CMGI:          xData = mutex_gate[xIR[12:7]];
1200
        default:        xData = 65'd0;
1201
        endcase
1202
`RR:
1203
        case(xFunc)
1204
        `ADD:   xData = a + b;
1205
        `ADDU:  xData = a + b;
1206
        `SUB:   xData = a - b;
1207
        `SUBU:  xData = a - b;
1208
        `CMP:   xData = lt ? 64'hFFFFFFFFFFFFF : eq ? 64'd0 : 64'd1;
1209
        `CMPU:  xData = ltu ? 64'hFFFFFFFFFFFFF : eq ? 64'd0 : 64'd1;
1210
        `SEQ:   xData = eq;
1211
        `SNE:   xData = !eq;
1212
        `SLT:   xData = lt;
1213
        `SLE:   xData = lt|eq;
1214
        `SGT:   xData = !(lt|eq);
1215
        `SGE:   xData = !lt;
1216
        `SLTU:  xData = ltu;
1217
        `SLEU:  xData = ltu|eq;
1218
        `SGTU:  xData = !(ltu|eq);
1219
        `SGEU:  xData = !ltu;
1220
        `AND:   xData = a & b;
1221
        `OR:    xData = a | b;
1222
        `XOR:   xData = a ^ b;
1223
        `ANDC:  xData = a & ~b;
1224
        `NAND:  xData = ~(a & b);
1225
        `NOR:   xData = ~(a | b);
1226
        `XNOR:  xData = ~(a ^ b);
1227
        `ORC:   xData = a | ~b;
1228
        `MIN:   xData = lt ? a : b;
1229
        `MAX:   xData = lt ? b : a;
1230
        `MOVZ:  xData = b;
1231
        `MOVNZ: xData = b;
1232
        `MULS:  xData = mult_out[63:0];
1233
        `MULU:  xData = mult_out[63:0];
1234
        `DIVS:  xData = div_q;
1235
        `DIVU:  xData = div_q;
1236
        `MOD:   xData = div_r;
1237
 
1238
        `SHL:   xData = shfto;
1239
        `SHRU:  xData = shfto;
1240
        `ROL:   xData = shfto;
1241
        `ROR:   xData = {a[0],a[63:1]};
1242
        `SHR:   xData = shfto;
1243
        `ROLAM: xData = shfto & masko;
1244
 
1245
        `BCD_ADD:       xData = bcdaddo;
1246
        `BCD_SUB:       xData = bcdsubo;
1247
 
1248
        default:        xData = 65'd0;
1249
        endcase
1250
`SHFTI:
1251
        case(xFunc)
1252
        `SHLI:  xData = shfto;
1253
        `SHRUI: xData = shfto;
1254
        `ROLI:  xData = shfto;
1255
        `RORI:  xData = {a[0],a[63:1]};
1256
        `SHRI:  xData = shfto;
1257
        `ROLAMI:        xData = shfto & masko;
1258
        `BFINS:         begin for (n = 0; n < 64; n = n + 1) xData[n] = masko[n] ? shfto[n] : b[n]; xData[64] = 1'b0; end
1259
        `BFSET:         begin for (n = 0; n < 64; n = n + 1) xData[n] = masko[n] ? 1'b1 : b[n]; xData[64] = 1'b0; end
1260
        `BFCLR:         begin for (n = 0; n < 64; n = n + 1) xData[n] = masko[n] ? 1'b0 : b[n]; xData[64] = 1'b0; end
1261
        `BFCHG:         begin for (n = 0; n < 64; n = n + 1) xData[n] = masko[n] ? ~b[n] : b[n]; xData[64] = 1'b0; end
1262
        default:        xData = 65'd0;
1263
        endcase
1264 21 robfinch
`BTRR:
1265
        case(xIR[4:0])
1266
        `LOOP:          xData = b - 64'd1;
1267
        default:        xData = 65'd0;
1268
        endcase
1269 14 robfinch
`SETLO: xData = imm;
1270
`SETHI: xData = {imm[63:32],a[31:0]};
1271
`ADDI:  xData = a + imm;
1272
`ADDUI: xData = a + imm;
1273
`SUBI:  xData = a - imm;
1274
`CMPI:  xData = lti ? 64'hFFFFFFFFFFFFF : eqi ? 64'd0 : 64'd1;
1275
`CMPUI: xData = ltui ? 64'hFFFFFFFFFFFFF : eqi ? 64'd0 : 64'd1;
1276
`MULSI: xData = mult_out[63:0];
1277
`MULUI: xData = mult_out[63:0];
1278
`DIVSI: xData = div_q;
1279
`DIVUI: xData = div_q;
1280
`ANDI:  xData = a & imm;
1281
`ORI:   xData = a | imm;
1282
`XORI:  xData = a ^ imm;
1283
`SEQI:  xData = eqi;
1284
`SNEI:  xData = !eqi;
1285
`SLTI:  xData = lti;
1286
`SLEI:  xData = lti|eqi;
1287
`SGTI:  xData = !(lti|eqi);
1288
`SGEI:  xData = !lti;
1289
`SLTUI: xData = ltui;
1290
`SLEUI: xData = ltui|eqi;
1291
`SGTUI: xData = !(ltui|eqi);
1292
`SGEUI: xData = !ltui;
1293
`INB,`INCH,`INH,`INW:
1294
                xData = a + imm;
1295
`OUTB,`OUTC,`OUTH,`OUTW:
1296
                xData = a + imm;
1297
`LW,`LH,`LC,`LB,`LHU,`LCU,`LBU,`LWR:
1298
                xData = a + imm;
1299
`SW,`SH,`SC,`SB,`SWC:
1300
                xData = a + imm;
1301
`MEMNDX:
1302
                xData = a + b + imm;
1303
`BEQ,`BNE,`BLT,`BLE,`BGT,`BGE,`BLTU,`BLEU,`BGTU,`BGEU,`BOR,`BAND:
1304
                xData = 64'd0;
1305
`TRAPcc:        xData = fnIncPC(xpc);
1306
`TRAPcci:       xData = fnIncPC(xpc);
1307
`CALL:          xData = fnIncPC(xpc);
1308
`JAL:           xData = xpc + {xIR[29:25],2'b00};
1309
`RET:   xData = a + {imm,2'b00};
1310
`FPLOO: xData = fpLooOut;
1311
`FPZL:  xData = fpZLOut;
1312
default:        xData = 65'd0;
1313
endcase
1314
 
1315
wire dbz_error = (xOpcode==`DIVSI||xOpcode==`DIVUI) && b==64'd0;
1316
wire ovr_error = (xOpcode==`ADDI || xOpcode==`SUBI) && (xData[64]!=xData[63]);
1317
wire priv_violation = !xKernelMode && (xOpcode==`MISC &&
1318
        (xFunc==`IRET || xFunc==`ERET || xFunc==`CLI || xFunc==`SEI ||
1319
         xFunc==`TLBP || xFunc==`TLBR || xFunc==`TLBWR || xFunc==`TLBWI
1320
        ));
1321
wire xIsSqrt = xOpcode==`R && xFunc==`SQRT;
1322
wire xIsMult = (xOpcode==`RR && (xFunc==`MULU || xFunc==`MULS)) ||
1323
        xOpcode==`MULSI || xOpcode==`MULUI;
1324
wire xIsDiv = (xOpcode==`RR && (xFunc==`DIVU || xFunc==`DIVS)) ||
1325
        xOpcode==`DIVSI || xOpcode==`DIVUI;
1326
 
1327
wire xIsLoad =
1328
        xOpcode==`LW || xOpcode==`LH || xOpcode==`LB || xOpcode==`LWR ||
1329
        xOpcode==`LHU || xOpcode==`LBU ||
1330 16 robfinch
        xOpcode==`LC || xOpcode==`LCU
1331 14 robfinch
        ;
1332
wire xIsStore =
1333 16 robfinch
        xOpcode==`SW || xOpcode==`SH || xOpcode==`SB || xOpcode==`SC || xOpcode==`SWC
1334 14 robfinch
        ;
1335
wire xIsSWC = xOpcode==`SWC;
1336 16 robfinch
wire xIsIn = xOpcode==`INW || xOpcode==`INH || xOpcode==`INCH || xOpcode==`INB;
1337
wire xIsOut = xOpcode==`OUTW || xOpcode==`OUTH || xOpcode==`OUTC || xOpcode==`OUTB;
1338 14 robfinch
//wire mIsSWC = mOpcode==`SWC;
1339
 
1340
//wire mIsLoad =
1341
//      mOpcode==`LW || mOpcode==`LH || mOpcode==`LB || mOpcode==`LC || mOpcode==`LWR ||
1342
//      mOpcode==`LHU || mOpcode==`LBU || mOpcode==`LCU ||
1343
//      mOpcode==`INW || mOpcode==`INB || mOpcode==`INH
1344
//      ;
1345
wire m1IsLoad =
1346
        m1Opcode==`LW || m1Opcode==`LH || m1Opcode==`LB || m1Opcode==`LC || m1Opcode==`LWR ||
1347
        m1Opcode==`LHU || m1Opcode==`LBU || m1Opcode==`LCU
1348
        ;
1349 16 robfinch
wire m1IsIn = m1Opcode==`INW || m1Opcode==`INH || m1Opcode==`INCH || m1Opcode==`INB;
1350
wire m1IsStore = m1Opcode==`SW || m1Opcode==`SH || m1Opcode==`SB || m1Opcode==`SC || m1Opcode==`SWC;
1351
wire m2IsStore = m2Opcode==`SW || m2Opcode==`SH || m2Opcode==`SB || m2Opcode==`SC || m2Opcode==`SWC;
1352
wire m1IsIO = m1IsIn || m1Opcode==`OUTW || m1Opcode==`OUTH || m1Opcode==`OUTC || m1Opcode==`OUTB;
1353 14 robfinch
wire m3IsIO =
1354
        m3Opcode==`INW || m3Opcode==`INH || m3Opcode==`INCH || m3Opcode==`INB ||
1355
        m3Opcode==`OUTW || m3Opcode==`OUTH || m3Opcode==`OUTC || m3Opcode==`OUTB
1356
        ;
1357
 
1358
wire m2IsLoad =
1359
        m2Opcode==`LW || m2Opcode==`LH || m2Opcode==`LB || m2Opcode==`LC || m2Opcode==`LWR ||
1360
        m2Opcode==`LHU || m2Opcode==`LBU || m2Opcode==`LCU
1361
        ;
1362
wire m3IsLoad =
1363
        m3Opcode==`LW || m3Opcode==`LH || m3Opcode==`LB || m3Opcode==`LC || m3Opcode==`LWR ||
1364
        m3Opcode==`LHU || m3Opcode==`LBU || m3Opcode==`LCU
1365
        ;
1366 16 robfinch
wire m3IsLoadW = m3Opcode==`LW || m3Opcode==`LWR;
1367
wire m3IsStoreW = m3Opcode==`SW || m3Opcode==`SWC;
1368
wire m4IsLoadW = m4Opcode==`LW || m4Opcode==`LWR;
1369
wire m4IsLoad = m4Opcode==`LW || m4Opcode==`LWR;
1370
wire m4IsStoreW = m4Opcode==`SW || m4Opcode==`SWC;
1371
wire m2IsInW = m2Opcode==`INW;
1372
wire m3IsInW = m3Opcode==`INW;
1373
wire m3IsOutW = m3Opcode==`OUTW;
1374
wire m2IsOutW = m2Opcode==`OUTW;
1375 14 robfinch
wire xIsFPLoo = xOpcode==`FPLOO;
1376
 
1377
// Stall on SWC allows rsf flag to be loaded for the next instruction
1378
// Currently stalls on load of R0, but doesn't need to.
1379
wire xStall = ((xIsLoad||xIsIn) && ((xRt==dRa)||(xRt==dRb)||(xRt==dRt))) || xIsSWC;
1380
wire m1Stall = ((m1IsLoad||m1IsIn) && ((m1Rt==dRa)||(m1Rt==dRb)||(m1Rt==dRt)));// || mIsSWC;
1381
wire m2Stall = ((m2IsLoad) && ((m2Rt==dRa)||(m2Rt==dRb)||(m2Rt==dRt)));// || mIsSWC;
1382
wire m3Stall = ((m3IsLoad) && ((m3Rt==dRa)||(m3Rt==dRb)||(m3Rt==dRt)));// || mIsSWC;
1383
wire m4Stall = ((m4IsLoad) && ((m4Rt==dRa)||(m4Rt==dRb)||(m4Rt==dRt)));// || mIsSWC;
1384
wire eomc = dccyc ? dhit : cyc_o & !icaccess & !dcaccess ? ack_i : 1'b1;        // end of memory cycle
1385
 
1386 16 robfinch
wire xneedIOPort = xIsIn | xIsOut;
1387
wire m1needIOPort = (((m1IsLoad & !m1IsCacheElement)|m1IsStore) & !m1DRAMBus) || m1IsIO;
1388
wire m2needIOPort = (((m2IsLoad)|m2IsStore) & !m2DRAMBus) || m2IsInW || m2IsOutW;
1389
wire m3needIOPort = (((m3IsLoadW)|m3IsStoreW) & !m3DRAMBus) || m3IsInW || m3IsOutW;
1390
wire m4needIOPort = (((m4IsLoadW)|m4IsStoreW) & !m4DRAMBus);
1391 14 robfinch
 
1392 16 robfinch
wire m1needWritePort = m1IsStore & m1DRAMBus;
1393
wire m2needWritePort = (m2Opcode==`SW||m2Opcode==`SWC) & m2DRAMBus;
1394
wire m2needReadPort = m2IsLoad & m2DRAMBus;
1395
wire m3needReadPort = (m3Opcode==`LW || m3Opcode==`LWR) & m3DRAMBus;
1396
wire m1needCmdPort = m1IsLoad && !m1IsCacheElement & m1DRAMBus;
1397
wire m2needCmdPort = (m2Opcode==`SH||m2Opcode==`SC||m2Opcode==`SB) & m2DRAMBus;
1398
wire m3needCmdPort = (m3Opcode==`SW || m3Opcode==`SWC) & m3DRAMBus;
1399
 
1400 14 robfinch
// Stall for the write port
1401
wire StallM1 = (m1needWritePort && m2needWritePort) ||  // Write port collision
1402 16 robfinch
        (m1needCmdPort && (m2needCmdPort||m3needCmdPort)) ||// Stall on the command port        // SW,SWC are still using the wr port in M2
1403
        (m1needIOPort && (m2needIOPort|m3needIOPort|m4needIOPort)) ||   // I/O port collision
1404
        icaccess || dcaccess            // cache access is taking place                                         
1405 14 robfinch
        ;
1406
// M3 is using the command port
1407 16 robfinch
wire StallM2 = (m2needCmdPort && m3needCmdPort) ||
1408
                                (m2needReadPort && m3needReadPort)||
1409
                                (m2needIOPort && (m3needIOPort | m4needIOPort)) ||
1410
                                icaccess||dcaccess
1411
                                ;
1412
wire StallM3 =  (m3needIOPort & m4needIOPort) ||
1413
                                icaccess||dcaccess
1414
                                ;
1415 14 robfinch
wire advanceT = !resetA;
1416
wire advanceW = advanceT;
1417 16 robfinch
wire advanceM4 = advanceW &&
1418
                                (m4IsLoadW && m4DRAMBus ? !rd_empty : 1'b1) &&
1419
                                (((m4IsLoadW|m4IsStoreW) && !m4DRAMBus) ? ack_i : 1'b1)
1420
                                ;
1421
wire advanceM3 = advanceM4 &&
1422
                                (m3IsIO ? ack_i : 1'b1) &&
1423
                                (m3IsLoad && m3DRAMBus ? !rd_empty : 1'b1) &&
1424
                                !StallM3
1425
                                ;
1426
wire advanceM2 = advanceM3 &&
1427
                                (((m2IsLoad|m2IsStore) && !m2DRAMBus) ? ack_i : 1'b1) &&
1428
                                !StallM2
1429
                                ;
1430
wire advanceM1 = advanceM2 &&
1431
                                (m1IsIO ? ack_i : 1'b1) &&
1432
                                ((m1IsLoad & !m1IsCacheElement) ? !cmd_full : 1'b1) &&
1433
                                ((m1IsLoad & m1IsCacheElement) ? dhit : 1'b1) &&
1434
                                (m1IsStore ? !wr_full : 1'b1) &&
1435
                                !StallM1
1436
                                ;
1437 14 robfinch
wire advanceX = advanceM1 & !cyc_o & (
1438 16 robfinch
                                xIsSqrt ? sqrt_done :
1439
                                xIsMult ? mult_done :
1440
                                xIsDiv ? div_done :
1441
                                xIsFPLoo ? fpLooDone :
1442
                                1'b1);
1443 14 robfinch
wire advanceR = advanceX & !xStall & !m1Stall && !m2Stall && !m3Stall && !m4Stall;
1444
wire advanceI = advanceR & ihit;
1445
 
1446
wire triggerDCacheLoad = (m1IsLoad & m1IsCacheElement & !dhit) &&       // there is a miss
1447
                                                !(icaccess | dcaccess | iciaccess) &&   // caches are not active
1448
                                                m2Opcode==`NOPI &&                      // and the pipeline is free of memory-ops
1449
                                                m3Opcode==`NOPI &&
1450
                                                m4Opcode==`NOPI &&
1451
                                                wr_empty                                        // and the write buffer is empty
1452
                                                ;
1453
// Since IMM is "sticky" we have to check for it.
1454
wire triggerICacheLoad = !ihit & !triggerDCacheLoad &   // There is a miss
1455
                                                (dOpcode==`NOPI || dOpcode[6:4]==`IMM) &&                       // and the pipeline is flushed
1456
                                                (xOpcode==`NOPI || xOpcode[6:4]==`IMM) &&
1457
                                                m1Opcode==`NOPI &&
1458
                                                m2Opcode==`NOPI &&
1459
                                                m3Opcode==`NOPI &&
1460
                                                m4Opcode==`NOPI
1461
                                                ;
1462
wire EXexception_pending = ovr_error || dbz_error || priv_violation || xOpcode==`TRAPcci || xOpcode==`TRAPcc;
1463
wire M1exception_pending = advanceM1 & (m1IsLoad|m1IsStore) & DTLBMiss;
1464
wire exception_pending = EXexception_pending | M1exception_pending;
1465
 
1466
wire xWillLoadStore = (xIsLoad||xIsStore) & advanceX;
1467
wire stallCacheLoad = xWillLoadStore;
1468
 
1469
reg prev_nmi,nmi_edge;
1470
 
1471
 
1472
//---------------------------------------------------------
1473
// Register file.
1474
//---------------------------------------------------------
1475
 
1476
syncRam512x64_1rw3r u5
1477
(
1478
        .wrst(1'b0),
1479
        .wclk(clk),
1480
        .wce(advanceW),
1481
        .we(1'b1),
1482
        .wadr(wRt),
1483
        .i(wData),
1484
        .wo(),
1485
 
1486
        .rrsta(1'b0),
1487
        .rclka(~clk),
1488
        .rcea(advanceR),
1489
        .radra(dRa),
1490
        .roa(rfoa),
1491
 
1492
        .rrstb(1'b0),
1493
        .rclkb(~clk),
1494
        .rceb(advanceR),
1495
        .radrb(dRb),
1496
        .rob(rfob),
1497
 
1498
        .rrstc(1'b0),
1499
        .rclkc(~clk),
1500
        .rcec(advanceR),
1501
        .radrc(dRc),
1502
        .roc(rfoc)
1503
);
1504
 
1505
 
1506
reg m1clkoff,m2clkoff,m3clkoff,m4clkoff,wclkoff;
1507
reg [15:0] dFip;
1508
reg xFip,m1Fip,m2Fip,m3Fip,m4Fip,wFip;
1509
 
1510
always @(posedge clk)
1511
if (rst_i) begin
1512
        bte_o <= 2'b00;
1513
        cti_o <= 3'b000;
1514
        cyc_o <= 1'b0;
1515
        stb_o <= 1'b0;
1516
        we_o <= 1'b0;
1517
        sel_o <= 8'h00;
1518
        adr_o <= 64'd0;
1519
        dat_o <= 64'd0;
1520
        dccyc <= 1'b0;
1521
 
1522
        cmd_en <= 1'b0;
1523
        cmd_instr <= 3'b001;
1524
        cmd_bl <= 6'd1;
1525
        cmd_byte_addr <= 30'd0;
1526
 
1527
        rd_en <= 1'b0;
1528
        wr_en <= 1'b0;
1529
 
1530
//      pc[0] <= 64'hFFFF_FFFF_FFFF_FFE0;
1531
        m1Opcode <= `NOPI;
1532
        m2Opcode <= `NOPI;
1533
        m3Opcode <= `NOPI;
1534
        m4Opcode <= `NOPI;
1535
        dIR <= `NOP_INSN;
1536
        dRt <= 9'd0;
1537
        tRt <= 9'd0;
1538
        wRt <= 9'd0;
1539
        m1Rt <= 9'd0;
1540
        m2Rt <= 9'd0;
1541
        m3Rt <= 9'd0;
1542
        m4Rt <= 9'd0;
1543
        tData <= 64'd0;
1544
        wData <= 64'd0;
1545
        m1Data <= 64'd0;
1546
        m2Data <= 64'd0;
1547
        m3Data <= 64'd0;
1548
        m4Data <= 64'd0;
1549
        icaccess <= 1'b0;
1550
        dcaccess <= 1'b0;
1551
        nopI <= 1'b0;
1552
        prev_ihit <= 1'b0;
1553
        wirqf <= 1'b0;
1554
        m1irqf <= 1'b0;
1555
        m2irqf <= 1'b0;
1556
        m3irqf <= 1'b0;
1557
        m4irqf <= 1'b0;
1558
        wFip <= 1'b0;
1559
        m4Fip <= 1'b0;
1560
        m3Fip <= 1'b0;
1561
        m2Fip <= 1'b0;
1562
        m1Fip <= 1'b0;
1563
        xFip <= 1'b0;
1564
        dFip <= 16'h0000;
1565
        dirqf <= 16'h0000;
1566
        tick <= 32'd0;
1567
        cstate <= IDLE;
1568
        dImm <= 64'd0;
1569
        regset <= 4'd0;
1570
        xirqf <= 1'b0;
1571
        xextype <= 8'h00;
1572
        xIR <= `NOP_INSN;
1573
        xpc <= 64'd0;
1574
        a <= 64'd0;
1575
        b <= 64'd0;
1576
        imm <= 64'd0;
1577
        xRt <= 9'd0;
1578
        clk_en <= 1'b1;
1579
        Random <= 4'hF;
1580
        Wired <= 4'd0;
1581
        StatusEXL <= 16'b0;
1582
        StatusHWI <= 16'h0;
1583
        epcnt <= 5'd0;
1584
        EP[0] <= 32'h00000000;
1585
        EP[1] <= 32'h00000000;
1586
        EP[2] <= 32'h00000000;
1587
        EP[3] <= 32'h00000000;
1588
        AXC <= 4'd0;
1589
        dAXC <= 4'd0;
1590
        xAXC <= 4'd0;
1591
        m1AXC <= 4'd0;
1592
        m2AXC <= 4'd0;
1593
        m3AXC <= 4'd0;
1594
        m4AXC <= 4'd0;
1595
        wAXC <= 4'd0;
1596
        resetA <= 1'b1;
1597
//      gbl_branch_hist <= 3'b000;
1598
end
1599
else begin
1600
 
1601
//---------------------------------------------------------
1602
// Initialize program counters
1603
//---------------------------------------------------------
1604
if (resetA) begin
1605
        pc[xAXC] <= `RESET_VECTOR;
1606
        gbl_branch_hist[AXC] <= 3'b000;
1607
        xAXC <= xAXC + 4'd1;
1608
        if (xAXC==4'hF)
1609
                resetA <= 1'b0;
1610
end
1611
 
1612
cmd_en <= 1'b0;                         // allow this signal only to pulse for a single clock cycle
1613
wr_en <= 1'b0;                                  // allow this signal to only pulse for a single cycle
1614
if (Random==Wired)
1615
        Random <= 4'hF;
1616
else
1617
        Random <= Random - 4'd1;
1618
 
1619
tick <= tick + 64'd1;
1620
 
1621
prev_nmi <= nmi_i;
1622
if (!prev_nmi & nmi_i)
1623
        nmi_edge <= 1'b1;
1624
 
1625
 
1626
// A store by any device in the system to a reserved address blcok
1627
// clears the reservation.
1628
 
1629
if (sys_adv && sys_adr[63:5]==resv_address)
1630
        resv_address <= 59'd0;
1631
 
1632
//---------------------------------------------------------
1633
// TRAILER:
1634
// - placeholder to allow the use of synchronous register
1635
//   memory
1636
//---------------------------------------------------------
1637
if (advanceT) begin
1638
        tRt <= 9'd0;
1639
        tData <= 64'd0;
1640
end
1641
 
1642
//---------------------------------------------------------
1643
// WRITEBACK:
1644
// - update the register file with results
1645
// - record exception address and type
1646
// - jump to exception handler routine (below)
1647
//---------------------------------------------------------
1648
if (advanceW) begin
1649
        textype <= wextype;
1650
        wextype <= `EX_NON;
1651
        tRt <= wRt;
1652
        tData <= wData;
1653
//      regfile[wRt] <= wData;  <- regfile.v
1654
        $display("Writing regfile[%d:%d] with %h", wRt[8:5],wRt[4:0], wData);
1655
        wRt <= 9'd0;
1656
        wData <= 64'd0;
1657
        if (wirqf) begin
1658
                wirqf <= 1'b0;
1659
                if (m1AXC==wAXC) m1irqf <= 1'b0;
1660
                if (m2AXC==wAXC) m2irqf <= 1'b0;
1661
                if (m3AXC==wAXC) m3irqf <= 1'b0;
1662
                if (m4AXC==wAXC) m4irqf <= 1'b0;
1663
                if (xAXC==wAXC) xirqf <= 1'b0;
1664
                dirqf[wAXC] <= 1'b0;
1665
                exception_type <= wextype;
1666
        end
1667
        clk_en <= 1'b1;
1668
        if (wclkoff)
1669
                clk_en <= 1'b0;
1670
        wclkoff <= 1'b0;
1671
        m1clkoff <= 1'b0;
1672
        m2clkoff <= 1'b0;
1673
        m3clkoff <= 1'b0;
1674
        m4clkoff <= 1'b0;
1675
        if (wFip) begin
1676
                wFip <= 1'b0;
1677
                if (m4AXC==wAXC) m4Fip <= 1'b0;
1678
                if (m3AXC==wAXC) m3Fip <= 1'b0;
1679
                if (m2AXC==wAXC) m2Fip <= 1'b0;
1680
                if (m1AXC==wAXC) m1Fip <= 1'b0;
1681
                if (xAXC==wAXC) xFip <= 1'b0;
1682
                dFip[wAXC] <= 1'b0;
1683
        end
1684
end
1685
 
1686
//---------------------------------------------------------
1687
// MEMORY:
1688
// - merge word load data into pipeline.
1689
//---------------------------------------------------------
1690
if (advanceM4) begin
1691
        wirqf <= m4irqf;
1692
        wFip <= m4Fip;
1693
        wAXC <= m4AXC;
1694
        wextype <= m4extype;
1695
        wRt <= m4Rt;
1696
        wpc <= m4pc;
1697
        wclkoff <= m4clkoff;
1698
        wData <= m4Data;
1699
 
1700
        m4Rt <= 9'd0;
1701
        m4Opcode <= `NOPI;
1702
        m4Data <= 64'd0;
1703
        m4clkoff <= 1'b0;
1704
        m4Opcode <= `NOPI;
1705
        m4extype <= `EX_NON;
1706
        if (m4extype==`EX_NON) begin
1707
                case(m4Opcode)
1708 16 robfinch
                `LW,`LWR:
1709
                        if (m4DRAMBus) begin
1710
                                wData <= {rd_data,m4Data[31:0]};
1711
                                rd_en <= 1'b0;  // only if LW/LWR
1712
                        end
1713
                        else begin
1714
                                cyc_o <= 1'b0;
1715
                                stb_o <= 1'b0;
1716
                                we_o <= 1'b0;
1717
                                sel_o <= 4'h0;
1718
                                wData <= {dat_i,m4Data[31:0]};
1719
                        end
1720
                `SW,`SWC:
1721
                        if (!m4DRAMBus) begin
1722
                                cyc_o <= 1'b0;
1723
                                stb_o <= 1'b0;
1724
                                we_o <= 1'b0;
1725
                                sel_o <= 4'h0;
1726
                        end
1727 14 robfinch
                default:        wData <= m4Data;
1728
                endcase
1729
        end
1730
end
1731
 
1732
 
1733
//---------------------------------------------------------
1734
// MEMORY:
1735
//---------------------------------------------------------
1736
if (advanceM3) begin
1737
        m4Opcode <= m3Opcode;
1738
        m4Func <= m3Func;
1739
        m4irqf <= m3irqf;
1740
        m4Fip <= m3Fip;
1741
        m4AXC <= m3AXC;
1742
        m4extype <= m3extype;
1743
        m4Rt <= m3Rt;
1744
        m4pc <= m3pc;
1745
        m4clkoff <= m3clkoff;
1746
 
1747
        m3Rt <= 9'd0;
1748
        m3Opcode <= `NOPI;
1749
        m3Func <= 7'd0;
1750
        m3clkoff <= 1'b0;
1751
        m3pc <= 64'd0;
1752
        m4Data <= m3Data;
1753
        m3Addr <= 64'd0;
1754
        m3Data <= 64'd0;
1755
        m3extype <= `EX_NON;
1756
        if (m3extype==`EX_NON) begin
1757
                case(m3Opcode)
1758
                `INW:
1759
                        begin
1760
                                cyc_o <= 1'b0;
1761
                                stb_o <= 1'b0;
1762
                                sel_o <= 4'h0;
1763
                                m4Data <= {dat_i,m3Data[31:0]};
1764
                        end
1765
                `OUTW:
1766
                        begin
1767
                                cyc_o <= 1'b0;
1768
                                stb_o <= 1'b0;
1769
                                we_o <= 1'b0;
1770
                                sel_o <= 4'h0;
1771
                        end
1772
                `LW,`LWR:
1773 16 robfinch
                        if (m3DRAMBus) begin
1774 14 robfinch
                                rd_en <= 1'b1;
1775
                                m4Data <= {32'd0,rd_data};
1776
                        end
1777 16 robfinch
                        else begin
1778
                                stb_o <= 1'b1;
1779
                                sel_o <= 4'hF;
1780
                                adr_o <= {m3Addr[63:2]+60'd1,2'b00};
1781
                        end
1782 14 robfinch
                `LH:
1783
                        begin
1784
                        rd_en <= 1'b0;
1785
                        m4Data <= {{32{rd_data[31]}},rd_data};
1786
                        end
1787
                `LHU:
1788
                        begin
1789
                        rd_en <= 1'b0;
1790
                        m4Data <= rd_data;
1791
                        end
1792
                `LC:
1793
                        begin
1794
                        rd_en <= 1'b0;
1795
                        case(m3Addr[1])
1796
                        1'b0:   m4Data <= {{48{rd_data[15]}},rd_data[15:0]};
1797
                        1'b1:   m4Data <= {{48{rd_data[31]}},rd_data[31:16]};
1798
                        endcase
1799
                        end
1800
                `LCU:
1801
                        begin
1802
                        rd_en <= 1'b0;
1803
                        case(m3Addr[1])
1804
                        1'b0:   m4Data <= {48'd0,rd_data[15:0]};
1805
                        1'b1:   m4Data <= {48'd0,rd_data[31:16]};
1806
                        endcase
1807
                        end
1808
                `LB:
1809
                        begin
1810
                        rd_en <= 1'b0;
1811
                        case(m3Addr[1:0])
1812
                        2'd0:   m4Data <= {{56{rd_data[7]}},rd_data[7:0]};
1813
                        2'd1:   m4Data <= {{56{rd_data[15]}},rd_data[15:8]};
1814
                        2'd2:   m4Data <= {{56{rd_data[23]}},rd_data[23:16]};
1815
                        2'd3:   m4Data <= {{56{rd_data[31]}},rd_data[31:24]};
1816
                        endcase
1817
                        end
1818
                `LBU:
1819
                        begin
1820
                        case(m3Addr[1:0])
1821
                        2'd0:   m4Data <= {{56{rd_data[7]}},rd_data[7:0]};
1822
                        2'd1:   m4Data <= {{56{rd_data[15]}},rd_data[15:8]};
1823
                        2'd2:   m4Data <= {{56{rd_data[23]}},rd_data[23:16]};
1824
                        2'd3:   m4Data <= {{56{rd_data[31]}},rd_data[31:24]};
1825
                        endcase
1826
                        rd_en <= 1'b0;
1827
                        end
1828
                `SW,`SWC:
1829 16 robfinch
                        if (m3DRAMBus) begin
1830 14 robfinch
                                cmd_en <= 1'b1;
1831
                                cmd_instr <= 3'b000;    // WRITE
1832
                                cmd_bl <= 6'd2;                 // 2-words
1833
                                cmd_byte_addr <= {m3Addr[29:3],3'b000};
1834
                        end
1835 16 robfinch
                        else begin
1836
                                stb_o <= 1'b1;
1837
                                we_o <= 1'b1;
1838
                                sel_o <= 4'hF;
1839
                                adr_o <= {m3Addr[63:2]+60'd1,2'b00};
1840
                                dat_o <= m3Data[63:32];
1841
                        end
1842 14 robfinch
                default:        ;
1843
                endcase
1844
        end
1845
end
1846
 
1847
//---------------------------------------------------------
1848
// MEMORY:
1849
//---------------------------------------------------------
1850
if (advanceM2) begin
1851
        m3Opcode <= m2Opcode;
1852
        m3Func <= m2Func;
1853
        m3Addr <= m2Addr;
1854
        m3Data <= m2Data;
1855
        m3irqf <= m2irqf;
1856
        m3AXC <= m2AXC;
1857
        m3extype <= m2extype;
1858
        m3Rt <= m2Rt;
1859
        m3pc <= m2pc;
1860
        m3clkoff <= m2clkoff;
1861
        m3Fip <= m2Fip;
1862
 
1863
        m2Rt <= 9'd0;
1864
        m2Opcode <= `NOPI;
1865
        m2Func <= 7'd0;
1866
        m2Addr <= 64'd0;
1867
        m2Data <= 64'd0;
1868
        m2clkoff <= 1'b0;
1869
        m2pc <= 64'd0;
1870
        m2extype <= `EX_NON;
1871
        if (m2extype==`EX_NON) begin
1872
                case(m2Opcode)
1873
                `INW:
1874
                        begin
1875
                        stb_o <= 1'b1;
1876
                        sel_o <= 4'hF;
1877
                        adr_o <= {m2Addr[63:3],3'b100};
1878
                        end
1879
                `OUTW:
1880
                        begin
1881
                        stb_o <= 1'b1;
1882
                        we_o <= 1'b1;
1883
                        sel_o <= 4'hF;
1884
                        adr_o <= {m2Addr[63:3],3'b100};
1885
                        dat_o <= m2Data[63:32];
1886
                        end
1887
                // Load fifo with upper half of word
1888
                `SW,`SWC:
1889 16 robfinch
                        if (m2DRAMBus) begin
1890 14 robfinch
                                wr_en <= 1'b1;
1891
                                wr_data <= m2Data[63:32];
1892
                                wr_mask <= 4'h0;
1893
                                wr_addr <= {m2Addr[63:3],3'b100};
1894
                        end
1895 16 robfinch
                        else begin
1896
                                stb_o <= 1'b0;
1897
                                we_o <= 1'b0;
1898
                                sel_o <= 4'h0;
1899
                        end
1900 14 robfinch
                `SH,`SC,`SB:
1901 16 robfinch
                        if (m2DRAMBus) begin
1902 14 robfinch
                                cmd_en <= 1'b1;
1903
                                cmd_instr <= 3'b000;    // WRITE
1904
                                cmd_bl <= 6'd1;                 // 1-word
1905
                                cmd_byte_addr <= {m2Addr[29:2],2'b00};
1906
                        end
1907 16 robfinch
                        else begin
1908
                                cyc_o <= 1'b0;
1909
                                stb_o <= 1'b0;
1910
                                we_o <= 1'b0;
1911
                                sel_o <= 4'h0;
1912
                                m3Opcode <= `NOPI;
1913
                        end
1914 14 robfinch
                // Initiate read operation
1915 16 robfinch
                `LW,`LWR:
1916
                        if (m2DRAMBus) begin
1917 14 robfinch
                                rd_en <= 1'b1;
1918
                        end
1919 16 robfinch
                        else begin
1920
                                stb_o <= 1'b0;
1921
                                sel_o <= 4'h0;
1922
                                m3Data <= dat_i;
1923
                        end
1924
                `LH:
1925
                        if (m2DRAMBus) begin
1926
                                rd_en <= 1'b1;
1927
                        end
1928
                        else begin
1929
                                cyc_o <= 1'b0;
1930
                                stb_o <= 1'b0;
1931
                                sel_o <= 4'h0;
1932
                                case(m2Addr[1:0])
1933
                                2'd0:   m3Data <= {{32{dat_i[31]}},dat_i};
1934
                                2'd1:   m3Data <= {{40{dat_i[31]}},dat_i[31:8]};
1935
                                2'd2:   m3Data <= {{48{dat_i[31]}},dat_i[31:16]};
1936
                                2'd3:   m3Data <= {{56{dat_i[31]}},dat_i[31:24]};
1937
                                endcase
1938
                        end
1939
                `LHU:
1940
                        if (m2DRAMBus) begin
1941
                                rd_en <= 1'b1;
1942
                        end
1943
                        else begin
1944
                                m3Opcode <= `NOPI;
1945
                                cyc_o <= 1'b0;
1946
                                stb_o <= 1'b0;
1947
                                sel_o <= 4'h0;
1948
                                case(m2Addr[1:0])
1949
                                2'd0:   m3Data <= dat_i;
1950
                                2'd1:   m3Data <= dat_i[31: 8];
1951
                                2'd2:   m3Data <= dat_i[31:16];
1952
                                2'd3:   m3Data <= dat_i[31:24];
1953
                                endcase
1954
                        end
1955
 
1956
                `LC:
1957
                        if (m2DRAMBus) begin
1958
                                rd_en <= 1'b1;
1959
                        end
1960
                        else begin
1961
                                m3Opcode <= `NOPI;
1962
                                cyc_o <= 1'b0;
1963
                                stb_o <= 1'b0;
1964
                                sel_o <= 4'h0;
1965
                                case(m2Addr[1:0])
1966
                                2'd0:   m3Data <= {{48{dat_i[15]}},dat_i[15:0]};
1967
                                2'd1:   m3Data <= {{48{dat_i[23]}},dat_i[23:8]};
1968
                                2'd2:   m3Data <= {{48{dat_i[31]}},dat_i[31:16]};
1969
                                2'd3:   m3Data <= {{56{dat_i[31]}},dat_i[31:24]};
1970
                                endcase
1971
                        end
1972
 
1973
                `LCU:
1974
                        if (m2DRAMBus) begin
1975
                                rd_en <= 1'b1;
1976
                        end
1977
                        else begin
1978
                                m3Opcode <= `NOPI;
1979
                                cyc_o <= 1'b0;
1980
                                stb_o <= 1'b0;
1981
                                sel_o <= 4'h0;
1982
                                case(m2Addr[1:0])
1983
                                2'd0:   m3Data <= dat_i[15:0];
1984
                                2'd1:   m3Data <= dat_i[23:8];
1985
                                2'd2:   m3Data <= dat_i[31:16];
1986
                                2'd3:   m3Data <= dat_i[31:24];
1987
                                endcase
1988
                        end
1989
                `LB:
1990
                        if (m2DRAMBus) begin
1991
                                rd_en <= 1'b1;
1992
                        end
1993
                        else begin
1994
                                m3Opcode <= `NOPI;
1995
                                cyc_o <= 1'b0;
1996
                                stb_o <= 1'b0;
1997
                                sel_o <= 4'h0;
1998
                                case(m2Addr[1:0])
1999
                                2'd0:   m3Data <= {{56{dat_i[ 7]}},dat_i[ 7: 0]};
2000
                                2'd1:   m3Data <= {{56{dat_i[15]}},dat_i[15: 8]};
2001
                                2'd2:   m3Data <= {{56{dat_i[23]}},dat_i[23:16]};
2002
                                2'd3:   m3Data <= {{56{dat_i[31]}},dat_i[31:24]};
2003
                                endcase
2004
                        end
2005
                `LBU:
2006
                        if (m2DRAMBus) begin
2007
                                rd_en <= 1'b1;
2008
                        end
2009
                        else begin
2010
                                m3Opcode <= `NOPI;
2011
                                cyc_o <= 1'b0;
2012
                                stb_o <= 1'b0;
2013
                                sel_o <= 4'h0;
2014
                                case(m2Addr[1:0])
2015
                                2'd0:   m3Data <= dat_i[ 7: 0];
2016
                                2'd1:   m3Data <= dat_i[15: 8];
2017
                                2'd2:   m3Data <= dat_i[23:16];
2018
                                2'd3:   m3Data <= dat_i[31:24];
2019
                                endcase
2020
                        end
2021 14 robfinch
                default:        ;
2022
                endcase
2023
        end
2024
end
2025
 
2026
wrhit <= 1'b0;
2027
//---------------------------------------------------------
2028
// MEMORY:
2029
// On a data cache hit for a load, the load is essentially
2030
// finished in this stage. We switch the opcode to 'LDONE'
2031
// to cause the pipeline to advance as if a NOPs were
2032
// present.
2033
//---------------------------------------------------------
2034
if (advanceM1) begin
2035
        m2Opcode <= m1Opcode;
2036
        m2Func <= m1Func;
2037
        m2Addr <= pea;
2038
        m2Data <= m1Data;
2039
        m2irqf <= m1irqf;
2040
        m2AXC <= m1AXC;
2041
        m2extype <= m1extype;
2042
        m2Rt <= m1Rt;
2043
        m2pc <= m1pc;
2044
        m2clkoff <= m1clkoff;
2045
        m2Fip <= m1Fip;
2046
 
2047
        m1Rt <= 9'd0;
2048
        m1Opcode <= `NOPI;
2049
        m1Func <= 7'd0;
2050
        m1Data <= 64'd0;
2051
        m1clkoff <= 1'b0;
2052
        m1pc <= 64'd0;
2053
        m1IsCacheElement <= 1'b0;
2054
        m1extype <= `EX_NON;
2055
 
2056
        if (m1extype == `EX_NON) begin
2057
                case(m1Opcode)
2058
                `MISC:
2059
                        case(m1Func)
2060
                        `TLBP:  Index[31] <= ~|DMatch;
2061
                        `TLBR:
2062
                                begin
2063
                                        TLBPageMask <= tTLBPageMask[i];
2064
                                        TLBVirtPage <= tTLBVirtPage[i];
2065
                                        TLBPhysPage0 <= tTLBPhysPage0[i];
2066
                                        TLBPhysPage1 <= tTLBPhysPage1[i];
2067
                                        TLBASID <= tTLBASID[i];
2068
                                        TLBG <= tTLBG[i];
2069
                                        TLBD <= tTLBD[i];
2070
                                        TLBValid <= tTLBValid[i];
2071
                                end
2072
                        `TLBWI,`TLBWR:
2073
                                begin
2074
                                        tTLBValid[i] <= 1'b1;
2075
                                        tTLBVirtPage[i] <= TLBVirtPage;
2076
                                        tTLBPhysPage0[i] <= TLBPhysPage0;
2077
                                        tTLBPhysPage1[i] <= TLBPhysPage1;
2078
                                        tTLBPageMask[i] <= TLBPageMask;
2079
                                        tTLBASID[i] <= TLBASID;
2080
                                        tTLBD[i] <= TLBD;
2081
                                        tTLBG[i] <= TLBG;
2082
                                        tTLBValid[i] <= TLBValid;
2083
                                end
2084
                        endcase
2085
                `INW:
2086
                        begin
2087
                                stb_o <= 1'b0;
2088
                                m2Data <= {32'd0,dat_i};
2089
                        end
2090
                `INH:
2091
                        begin
2092
                                cyc_o <= 1'b0;
2093
                                stb_o <= 1'b0;
2094
                                sel_o <= 4'd0;
2095
                                m2Data <= {{32{dat_i[31]}},dat_i[31: 0]};
2096
                        end
2097
                `INCH:
2098
                        begin
2099
                                cyc_o <= 1'b0;
2100
                                stb_o <= 1'b0;
2101
                                sel_o <= 4'd0;
2102
                                case(sel_o)
2103
                                4'b0011:        m2Data <= {{48{dat_i[15]}},dat_i[15: 0]};
2104
                                4'b1100:        m2Data <= {{48{dat_i[31]}},dat_i[31:16]};
2105
                                default:        m2Data <= 64'hDEADDEADDEADDEAD;
2106
                                endcase
2107
                        end
2108
                `INB:
2109
                        begin
2110
                                cyc_o <= 1'b0;
2111
                                stb_o <= 1'b0;
2112
                                sel_o <= 4'd0;
2113
                                case(sel_o)
2114
                                4'b0001:        m2Data <= {{56{dat_i[ 7]}},dat_i[ 7: 0]};
2115
                                4'b0010:        m2Data <= {{56{dat_i[15]}},dat_i[15: 8]};
2116
                                4'b0100:        m2Data <= {{56{dat_i[23]}},dat_i[23:16]};
2117
                                4'b1000:        m2Data <= {{56{dat_i[31]}},dat_i[31:24]};
2118
                                default:        m2Data <= 64'hDEADDEADDEADDEAD;
2119
                                endcase
2120
                        end
2121
                `OUTW:
2122
                        begin
2123
                                stb_o <= 1'b0;
2124
                                we_o <= 1'b0;
2125
                                sel_o <= 4'd0;
2126
                        end
2127
                `OUTH,`OUTC,`OUTB:
2128
                        begin
2129
                                cyc_o <= 1'b0;
2130
                                stb_o <= 1'b0;
2131
                                we_o <= 1'b0;
2132
                                sel_o <= 4'd0;
2133
                        end
2134 16 robfinch
 
2135 14 robfinch
                `LW:
2136
                        if (!m1IsCacheElement) begin
2137 16 robfinch
                                if (m1DRAMBus) begin
2138
                                        cmd_en <= 1'b1;
2139
                                        cmd_bl <= 6'd2;                 // 2-words (from 32-bit interface)
2140
                                        cmd_instr <= 3'b001;    // READ
2141
                                        cmd_byte_addr <= {pea[63:3],3'b000};
2142
                                end
2143
                                else begin
2144
                                        cyc_o <= 1'b1;
2145
                                        stb_o <= 1'b1;
2146
                                        adr_o <= pea;
2147
                                        sel_o <= fnSel1(pea);
2148
                                end
2149 14 robfinch
                        end
2150
                        else if (dhit) begin
2151
                                m2Opcode <= `LDONE;
2152
                                m2Data <= cdat;
2153
                        end
2154 16 robfinch
 
2155 14 robfinch
                `LWR:
2156
                        if (!m1IsCacheElement) begin
2157 16 robfinch
                                if (m1DRAMBus) begin
2158
                                        cmd_en <= 1'b1;
2159
                                        cmd_bl <= 6'd2;                 // 2-words (from 32-bit interface)
2160
                                        cmd_instr <= 3'b001;    // READ
2161
                                        cmd_byte_addr <= {pea[63:3],3'b000};
2162
                                end
2163
                                else begin
2164
                                        cyc_o <= 1'b1;
2165
                                        stb_o <= 1'b1;
2166
                                        adr_o <= pea;
2167
                                        sel_o <= fnSel1(pea);
2168
                                end
2169 14 robfinch
                                rsv_o <= 1'b1;
2170
                                resv_address <= pea[63:5];
2171
                        end
2172
                        else if (dhit) begin
2173 16 robfinch
                                m2Opcode <= `NOPI;
2174 14 robfinch
                                m2Data <= cdat;
2175
                                rsv_o <= 1'b1;
2176
                                resv_address <= pea[63:5];
2177
                        end
2178 16 robfinch
 
2179 14 robfinch
                `LH:
2180
                        if (!m1IsCacheElement) begin
2181 16 robfinch
                                if (m1DRAMBus) begin
2182
                                        cmd_en <= 1'b1;
2183
                                        cmd_bl <= 6'd1;                 // 1-words (from 32-bit interface)
2184
                                        cmd_instr <= 3'b001;    // READ
2185
                                        cmd_byte_addr <= {pea[63:2],2'b00};
2186
                                end
2187
                                else begin
2188
                                        cyc_o <= 1'b1;
2189
                                        stb_o <= 1'b1;
2190
                                        adr_o <= pea;
2191
                                        sel_o <= fnSel1(pea);
2192
                                end
2193 14 robfinch
                        end
2194
                        else if (dhit) begin
2195 16 robfinch
                                m2Opcode <= `NOPI;
2196 14 robfinch
                                if (pea[1])
2197
                                        m2Data <= {{32{cdat[31]}},cdat[31:0]};
2198
                                else
2199
                                        m2Data <= {{32{cdat[63]}},cdat[63:32]};
2200
                        end
2201 16 robfinch
 
2202 14 robfinch
                `LHU:
2203
                        if (!m1IsCacheElement) begin
2204 16 robfinch
                                if (m1DRAMBus) begin
2205
                                        cmd_en <= 1'b1;
2206
                                        cmd_bl <= 6'd1;                 // 1-words (from 32-bit interface)
2207
                                        cmd_instr <= 3'b001;    // READ
2208
                                        cmd_byte_addr <= {pea[63:2],2'b00};
2209
                                end
2210
                                else begin
2211
                                        cyc_o <= 1'b1;
2212
                                        stb_o <= 1'b1;
2213
                                        adr_o <= pea;
2214
                                        sel_o <= fnSel1(pea);
2215
                                end
2216 14 robfinch
                        end
2217
                        else if (dhit) begin
2218 16 robfinch
                                m2Opcode <= `NOPI;
2219 14 robfinch
                                if (pea[1])
2220
                                        m2Data <= {32'd0,cdat};
2221
                                else
2222
                                        m2Data <= {32'd0,cdat[63:32]};
2223
                        end
2224 16 robfinch
 
2225 14 robfinch
                `LC:
2226
                        if (!m1IsCacheElement) begin
2227 16 robfinch
                                if (m1DRAMBus) begin
2228
                                        cmd_en <= 1'b1;
2229
                                        cmd_bl <= 6'd1;                 // 1-words (from 32-bit interface)
2230
                                        cmd_instr <= 3'b001;    // READ
2231
                                        cmd_byte_addr <= {pea[63:2],2'b00};
2232
                                end
2233
                                else begin
2234
                                        cyc_o <= 1'b1;
2235
                                        stb_o <= 1'b1;
2236
                                        adr_o <= pea;
2237
                                        sel_o <= fnSel2(pea);
2238
                                end
2239 14 robfinch
                        end
2240
                        else if (dhit) begin
2241 16 robfinch
                                m2Opcode <= `NOPI;
2242 14 robfinch
                                case(pea[2:1])
2243
                                2'd0:   m2Data <= {{48{cdat[15]}},cdat[15:0]};
2244
                                2'd1:   m2Data <= {{48{cdat[31]}},cdat[31:16]};
2245
                                2'd2:   m2Data <= {{48{cdat[47]}},cdat[47:32]};
2246
                                2'd3:   m2Data <= {{48{cdat[63]}},cdat[63:48]};
2247
                                endcase
2248
                        end
2249 16 robfinch
 
2250 14 robfinch
                `LCU:
2251
                        if (!m1IsCacheElement) begin
2252 16 robfinch
                                if (m1DRAMBus) begin
2253
                                        cmd_en <= 1'b1;
2254
                                        cmd_bl <= 6'd1;                 // 1-words (from 32-bit interface)
2255
                                        cmd_instr <= 3'b001;    // READ
2256
                                        cmd_byte_addr <= {pea[63:2],2'b00};
2257
                                end
2258
                                else begin
2259
                                        cyc_o <= 1'b1;
2260
                                        stb_o <= 1'b1;
2261
                                        adr_o <= pea;
2262
                                        sel_o <= fnSel2(pea);
2263
                                end
2264 14 robfinch
                        end
2265
                        else if (dhit) begin
2266 16 robfinch
                                m2Opcode <= `NOPI;
2267 14 robfinch
                                case(pea[2:1])
2268
                                2'd0:   m2Data <= {48'd0,cdat[15: 0]};
2269
                                2'd1:   m2Data <= {48'd0,cdat[31:16]};
2270
                                2'd2:   m2Data <= {48'd0,cdat[47:32]};
2271
                                2'd3:   m2Data <= {48'd0,cdat[63:48]};
2272
                                endcase
2273
                        end
2274 16 robfinch
 
2275 14 robfinch
                `LB:
2276
                        if (!m1IsCacheElement) begin
2277 16 robfinch
                                if (m1DRAMBus) begin
2278
                                        cmd_en <= 1'b1;
2279
                                        cmd_bl <= 6'd1;                 // 1-words (from 32-bit interface)
2280
                                        cmd_instr <= 3'b001;    // READ
2281
                                        cmd_byte_addr <= {pea[63:2],2'b00};
2282
                                end
2283
                                else begin
2284
                                        cyc_o <= 1'b1;
2285
                                        stb_o <= 1'b1;
2286
                                        adr_o <= pea;
2287
                                        sel_o <= fnSel4(pea);
2288
                                end
2289 14 robfinch
                        end
2290
                        else if (dhit) begin
2291 16 robfinch
                                m2Opcode <= `NOPI;
2292 14 robfinch
                                case(pea[2:0])
2293
                                3'b000: m2Data <= {{56{cdat[ 7]}},cdat[ 7: 0]};
2294
                                3'b001: m2Data <= {{56{cdat[15]}},cdat[15: 8]};
2295
                                3'b010: m2Data <= {{56{cdat[23]}},cdat[23:16]};
2296
                                3'b011: m2Data <= {{56{cdat[31]}},cdat[31:24]};
2297
                                3'b100: m2Data <= {{56{cdat[39]}},cdat[39:32]};
2298
                                3'b101: m2Data <= {{56{cdat[47]}},cdat[47:40]};
2299
                                3'b110: m2Data <= {{56{cdat[55]}},cdat[55:48]};
2300
                                3'b111: m2Data <= {{56{cdat[63]}},cdat[63:56]};
2301
                                endcase
2302
                        end
2303 16 robfinch
 
2304 14 robfinch
                `LBU:
2305
                        if (!m1IsCacheElement) begin
2306 16 robfinch
                                if (m1DRAMBus) begin
2307
                                        cmd_en <= 1'b1;
2308
                                        cmd_bl <= 6'd1;                 // 1-words (from 32-bit interface)
2309
                                        cmd_instr <= 3'b001;    // READ
2310
                                        cmd_byte_addr <= {pea[63:2],2'b00};
2311
                                end
2312
                                else begin
2313
                                        cyc_o <= 1'b1;
2314
                                        stb_o <= 1'b1;
2315
                                        adr_o <= pea;
2316
                                        sel_o <= fnSel4(pea);
2317
                                end
2318 14 robfinch
                        end
2319
                        else if (dhit) begin
2320 16 robfinch
                                m2Opcode <= `NOPI;
2321 14 robfinch
                                case(pea[2:0])
2322
                                3'b000: m2Data <= {56'd0,cdat[ 7: 0]};
2323
                                3'b001: m2Data <= {56'd0,cdat[15: 8]};
2324
                                3'b010: m2Data <= {56'd0,cdat[23:16]};
2325
                                3'b011: m2Data <= {56'd0,cdat[31:23]};
2326
                                3'b100: m2Data <= {56'd0,cdat[39:32]};
2327
                                3'b101: m2Data <= {56'd0,cdat[47:40]};
2328
                                3'b110: m2Data <= {56'd0,cdat[55:48]};
2329
                                3'b111: m2Data <= {56'd0,cdat[63:56]};
2330
                                endcase
2331
                        end
2332 16 robfinch
 
2333 14 robfinch
                `SW,`SH:
2334
                        begin
2335
                                if (!m1UnmappedDataArea & !q[4]) begin
2336
                                        tTLBD[q] <= 1'b1;
2337
                                end
2338
                                if (resv_address==pea[63:5])
2339
                                        resv_address <= 59'd0;
2340 16 robfinch
                                wrhit <= dhit;
2341
                                m2Addr <= {pea[63:1],2'b00};
2342
                                if (m1DRAMBus) begin
2343
                                        wr_en <= 1'b1;
2344
                                        wr_data <= m1b[31:0];
2345
                                        wr_mask <= ~fnSel1(pea);
2346
                                        wr_addr <= {pea[63:3],3'b000};
2347
                                end
2348
                                else begin
2349
                                        cyc_o <= 1'b1;
2350
                                        stb_o <= 1'b1;
2351
                                        we_o <= 1'b1;
2352
                                        adr_o <= pea;
2353
                                        sel_o <= fnSel1(pea);
2354
                                        dat_o <= m1Data[31:0];
2355
                                end
2356 14 robfinch
                        end
2357 16 robfinch
 
2358 14 robfinch
                `SC:
2359
                        begin
2360
                                $display("Storing char to %h, ea=%h",pea,ea);
2361
                                if (!m1UnmappedDataArea & !q[4]) begin
2362
                                        tTLBD[q] <= 1'b1;
2363
                                end
2364
                                if (resv_address==pea[63:5])
2365
                                        resv_address <= 59'd0;
2366 16 robfinch
                                wrhit <= dhit;
2367
                                m2Addr <= {pea[63:1],1'b0};
2368
                                if (m1DRAMBus) begin
2369
                                        wr_en <= 1'b1;
2370
                                        wr_data <= {2{m1b[15:0]}};
2371
                                        wr_mask <= ~fnSel2(pea);
2372
                                        wr_addr <= {pea[63:2],2'b00};
2373
                                end
2374
                                else begin
2375
                                        cyc_o <= 1'b1;
2376
                                        stb_o <= 1'b1;
2377
                                        we_o <= 1'b1;
2378
                                        adr_o <= pea;
2379
                                        sel_o <= fnSel2(pea);
2380
                                        dat_o <= {2{m1Data[15:0]}};
2381
                                end
2382 14 robfinch
                        end
2383 16 robfinch
 
2384 14 robfinch
                `SB:
2385
                        begin
2386
                                if (!m1UnmappedDataArea & !q[4]) begin
2387
                                        tTLBD[q] <= 1'b1;
2388
                                end
2389 16 robfinch
                                if (resv_address==pea[63:5])
2390
                                        resv_address <= 59'd0;
2391 14 robfinch
                                wrhit <= dhit;
2392
                                m2Addr <= {pea[63:2],2'b00};
2393 16 robfinch
                                if (m1DRAMBus) begin
2394
                                        wr_en <= 1'b1;
2395
                                        wr_data <= {4{m1b[7:0]}};
2396
                                        wr_addr <= {pea[63:2],2'b00};
2397
                                        wr_mask <= ~fnSel4(pea);
2398
                                end
2399
                                else begin
2400
                                        cyc_o <= 1'b1;
2401
                                        stb_o <= 1'b1;
2402
                                        we_o <= 1'b1;
2403
                                        adr_o <= pea;
2404
                                        sel_o <= fnSel4(pea);
2405
                                        dat_o <= {4{m1Data[7:0]}};
2406
                                end
2407 14 robfinch
                        end
2408 16 robfinch
 
2409 14 robfinch
                `SWC:
2410
                        begin
2411
                                rsf <= 1'b0;
2412
                                if (resv_address==pea[63:5]) begin
2413
                                        if (!m1UnmappedDataArea & !q[4]) begin
2414
                                                tTLBD[q] <= 1'b1;
2415
                                        end
2416
                                        wrhit <= dhit;
2417
                                        m2Addr <= {pea[63:3],3'b000};
2418
                                        resv_address <= 59'd0;
2419
                                        rsf <= 1'b1;
2420 16 robfinch
                                        if (m1DRAMBus) begin
2421
                                                wr_en <= 1'b1;
2422
                                                wr_data <= m1b[31:0];
2423
                                                wr_mask <= 4'h0;
2424
                                                wr_addr <= {pea[63:3],3'b000};
2425
                                        end
2426
                                        else begin
2427
                                                cyc_o <= 1'b1;
2428
                                                stb_o <= 1'b1;
2429
                                                we_o <= 1'b1;
2430
                                                adr_o <= pea;
2431
                                                sel_o <= fnSel1(pea);
2432
                                                dat_o <= m1Data[31:0];
2433
                                        end
2434 14 robfinch
                                end
2435
                                else
2436
                                        m2Opcode <= `NOPI;
2437
                        end
2438
                endcase
2439
        end
2440
end
2441
 
2442
//---------------------------------------------------------
2443
// EXECUTE:
2444
// - perform datapath operation
2445
// - Stores always initiate a bus cycle
2446
// - Loads initiate a bus cycle only from non-cacheable
2447
//   addresses
2448
//---------------------------------------------------------
2449
if (advanceX) begin
2450
        m1irqf <= xirqf;
2451
        m1Fip <= xFip;
2452
        m1extype <= xextype;
2453
        m1Opcode <= xOpcode;
2454
        m1Func <= xFunc;
2455
        m1Rt <= xRt;
2456
        m1Data <= xData;
2457
        m1IsCacheElement <= xisCacheElement;
2458
        m1UnmappedDataArea <= unmappedDataArea;
2459
        m1AXC <= xAXC;
2460
        if (xOpcode==`MOVZ && !aeqz) begin
2461
                m1Rt <= 9'd0;
2462
                m1Data <= 64'd0;
2463
        end
2464
        if (xOpcode==`MOVNZ && aeqz) begin
2465
                m1Rt <= 9'd0;
2466
                m1Data <= 64'd0;
2467
        end
2468
        m1pc <= xpc;
2469
        xRt <= 9'd0;
2470
        a <= 64'd0;
2471
        b <= 64'd0;
2472
        imm <= 64'd0;
2473
        xextype <= `EX_NON;
2474
        if (xOpcode[6:4]!=`IMM) begin
2475
                xIR <= `NOP_INSN;
2476
        end
2477
//      xpc <= 64'd0;
2478
        case(xOpcode)
2479
        `MISC:
2480
                case(xFunc)
2481 16 robfinch
                `SEI:   im <= 1'b1;
2482
                `CLI:   im <= 1'b0;
2483 14 robfinch
                `WAIT:  m1clkoff <= 1'b1;
2484
                `TLBP:  ea <= TLBVirtPage;
2485
                `TLBR,`TLBWI:
2486
                        begin
2487
                                i <= Index;
2488
                        end
2489
                `TLBWR:
2490
                        begin
2491
                                i <= Random;
2492
                        end
2493
                default:        ;
2494
                endcase
2495
        `R:
2496
                case(xFunc)
2497
                `MTSPR:
2498
                        case(xIR[12:7])
2499 16 robfinch
                        `Wired:                 Wired <= a[3:0];
2500
                        `ASID:                  ASID <= a[7:0];
2501
                        `TLBIndex:              Index <= a[3:0];
2502
                        `TLBVirtPage:   TLBVirtPage <= a[63:13];
2503
                        `TLBPhysPage0:  TLBPhysPage0 <= a[63:13];
2504
                        `TLBPhysPage1:  TLBPhysPage1 <= a[63:13];
2505
                        `TLBPageMask:   TLBPageMask <= a[24:13];
2506 14 robfinch
                        `TLBASID:               begin
2507 16 robfinch
                                                        TLBASID <= a[15:8];
2508
                                                        TLBD <= a[1];
2509
                                                        TLBValid <= a[0];
2510
                                                        TLBG <= a[2];
2511 14 robfinch
                                                        end
2512 16 robfinch
                        `PageTableAddr: PageTableAddr <= a[63:13];
2513
                        `BadVAddr:              BadVAddr[xAXC] <= a[63:13];
2514
                        `EP0:                   begin
2515
                                                        $display("Updating EP0=%h",{a[31:4],4'd0});
2516
                                                        EP[0] <= {a[31:4],4'd0};
2517
                                                        end
2518
                        `EP1:                   EP[1] <= a[31:0];
2519
                        `EP2:                   EP[2] <= a[31:0];
2520
                        `EP3:                   EP[3] <= a[31:0];
2521
                        `EPC:                   EPC[xAXC] <= a;
2522
                        `TBA:                   TBA <= a;
2523 14 robfinch
                        default:        ;
2524
                        endcase
2525
                `OMG:   mutex_gate[a[5:0]] <= 1'b1;
2526
                `CMG:   mutex_gate[a[5:0]] <= 1'b0;
2527
                `OMGI:  mutex_gate[xIR[12:7]] <= 1'b1;
2528
                `CMGI:  mutex_gate[xIR[12:7]] <= 1'b0;
2529
                default:        ;
2530
                endcase
2531
        `CALL:  m1Data <= fnIncPC(xpc);
2532
        `INW:
2533
                        begin
2534
                        cyc_o <= 1'b1;
2535
                        stb_o <= 1'b1;
2536
                        sel_o <= 4'hF;
2537
                        adr_o <= {xData[63:3],3'b000};
2538
                        end
2539
        `INH:
2540
                        begin
2541
                        cyc_o <= 1'b1;
2542
                        stb_o <= 1'b1;
2543
                        sel_o <= 4'b1111;
2544
                        adr_o <= {xData[63:2],2'b00};
2545
                        end
2546
        `INCH:
2547
                        begin
2548
                        cyc_o <= 1'b1;
2549
                        stb_o <= 1'b1;
2550
                        case(xData[1])
2551
                        1'b0:   sel_o <= 4'b0011;
2552
                        1'b1:   sel_o <= 4'b1100;
2553
                        endcase
2554
                        adr_o <= {xData[63:1],1'b0};
2555
                        end
2556
        `INB:
2557
                        begin
2558
                        cyc_o <= 1'b1;
2559
                        stb_o <= 1'b1;
2560
                        case(xData[1:0])
2561
                        2'b00:  sel_o <= 8'b0001;
2562
                        2'b01:  sel_o <= 8'b0010;
2563
                        2'b10:  sel_o <= 8'b0100;
2564
                        2'b11:  sel_o <= 8'b1000;
2565
                        endcase
2566
                        adr_o <= xData;
2567
                        end
2568
        `OUTW:
2569
                        begin
2570
                        cyc_o <= 1'b1;
2571
                        stb_o <= 1'b1;
2572
                        we_o <= 1'b1;
2573
                        sel_o <= 4'hF;
2574
                        adr_o <= {xData[63:3],3'b000};
2575
                        dat_o <= b[31:0];
2576 16 robfinch
                        m1Data <= b;
2577 14 robfinch
                        end
2578
        `OUTH:
2579
                        begin
2580
                        cyc_o <= 1'b1;
2581
                        stb_o <= 1'b1;
2582
                        we_o <= 1'b1;
2583
                        sel_o <= 4'b1111;
2584
                        adr_o <= {xData[63:2],2'b00};
2585
                        dat_o <= b[31:0];
2586
                        end
2587
        `OUTC:
2588
                        begin
2589
                        cyc_o <= 1'b1;
2590
                        stb_o <= 1'b1;
2591
                        we_o <= 1'b1;
2592
                        case(xData[1])
2593
                        1'b0:   sel_o <= 4'b0011;
2594
                        1'b1:   sel_o <= 4'b1100;
2595
                        endcase
2596
                        adr_o <= {xData[63:1],1'b0};
2597
                        dat_o <= {2{b[15:0]}};
2598
                        end
2599
        `OUTB:
2600
                        begin
2601
                        cyc_o <= 1'b1;
2602
                        stb_o <= 1'b1;
2603
                        we_o <= 1'b1;
2604
                        case(xData[1:0])
2605
                        2'b00:  sel_o <= 4'b0001;
2606
                        2'b01:  sel_o <= 4'b0010;
2607
                        2'b10:  sel_o <= 4'b0100;
2608
                        2'b11:  sel_o <= 4'b1000;
2609
                        endcase
2610
                        adr_o <= xData;
2611
                        dat_o <= {4{b[7:0]}};
2612
                        end
2613
        `LB,`LBU,`LC,`LCU,`LH,`LHU,`LW,`LWR,`SW,`SH,`SC,`SB,`SWC:
2614
                        begin
2615 16 robfinch
                        m1Data <= b;
2616 14 robfinch
                        ea <= xData;
2617
                        end
2618
        `MEMNDX:
2619
                        begin
2620
                        m1Opcode <= xFunc;
2621 16 robfinch
                        m1Data <= c;
2622 14 robfinch
                        ea <= xData;
2623
                        end
2624
        `DIVSI,`DIVUI:
2625
                if (b==64'd0) begin
2626
                        xextype <= `EX_DBZ;
2627
                end
2628
        default:        ;
2629
        endcase
2630
        // Update the branch history
2631
        if (isxBranch) begin
2632
                gbl_branch_hist[xAXC] <= {gbl_branch_hist[xAXC],takb};
2633
                branch_history_table[bht_wa] <= xbits_new;
2634
        end
2635
end
2636
 
2637
//---------------------------------------------------------
2638
// RFETCH:
2639
// Register fetch stage
2640
//---------------------------------------------------------
2641
if (advanceR) begin
2642
        xirqf <= dirqf[dAXC];
2643
        xFip <= dFip[dAXC];
2644
        xextype <= dextype;
2645
        xAXC <= dAXC;
2646
        xIR <= dIR;
2647
        xpc <= dpc;
2648
        xbranch_taken <= dbranch_taken;
2649
        dbranch_taken <= 1'b0;
2650
        dextype <= `EX_NON;
2651
        if (dOpcode[6:4]!=`IMM) // IMM is "sticky"
2652
                dIR <= `NOP_INSN;
2653
        dRa <= 9'd0;
2654
        dRb <= 9'd0;
2655
 
2656
        // Result forward muxes
2657
        casex(dRa)
2658
        9'bxxxx00000:   a <= 64'd0;
2659
        xRt:    a <= xData;
2660
        m1Rt:   a <= m1Data;
2661
        m2Rt:   a <= m2Data;
2662
        m3Rt:   a <= m3Data;
2663
        m4Rt:   a <= m4Data;
2664
        wRt:    a <= wData;
2665
        tRt:    a <= tData;
2666
        default:        a <= rfoa;
2667
        endcase
2668
        casex(dRb)
2669
        9'bxxxx00000:   b <= 64'd0;
2670
        xRt:    b <= disRightShift ? -xData[5:0] : xData;
2671
        m1Rt:   b <= disRightShift ? -m1Data[5:0] : m1Data;
2672
        m2Rt:   b <= disRightShift ? -m2Data[5:0] : m2Data;
2673
        m3Rt:   b <= disRightShift ? -m3Data[5:0] : m3Data;
2674
        m4Rt:   b <= disRightShift ? -m4Data[5:0] : m4Data;
2675
        wRt:    b <= disRightShift ? -wData[5:0] : wData;
2676
        tRt:    b <= disRightShift ? -tData[5:0] : tData;
2677
        default:        b <= disRightShift ? -rfob[5:0] : rfob;
2678
        endcase
2679
        if (dOpcode==`SHFTI)
2680
                case(dFunc)
2681
                `RORI:          b <= {58'd0,~dIR[24:19]+6'd1};
2682
                default:        b <= {58'd0,dIR[24:19]};
2683
                endcase
2684
        casex(dRc)
2685
        9'bxxxx00000:   c <= 64'd0;
2686
        xRt:    c <= xData;
2687
        m1Rt:   c <= m1Data;
2688
        m2Rt:   c <= m2Data;
2689
        m3Rt:   c <= m3Data;
2690
        m4Rt:   c <= m4Data;
2691
        wRt:    c <= wData;
2692
        tRt:    c <= tData;
2693
        default:        c <= rfoc;
2694
        endcase
2695
 
2696
        // Set the target register
2697
        casex(dOpcode)
2698 16 robfinch
        `SETLO:         xRt <= {dAXC,dRa};
2699
        `SETHI:         xRt <= {dAXC,dRa};
2700 14 robfinch
        `RR:            xRt <= {dAXC,dIR[24:20]};
2701
        `BTRI:          xRt <= 9'd0;
2702 21 robfinch
        `BTRR:
2703
                case(dIR[4:0])
2704
                `LOOP:  xRt <= {dAXC,dRb};
2705
                default: xRt <= 9'd0;
2706
                endcase
2707 14 robfinch
        `TRAPcc:        xRt <= 9'd0;
2708
        `TRAPcci:       xRt <= 9'd0;
2709
        `JMP:           xRt <= 9'd00;
2710
        `CALL:          xRt <= {dAXC,5'd31};
2711
        `RET:           xRt <= {dAXC,dIR[24:20]};
2712
        `MEMNDX:
2713
                case(dFunc)
2714
                `SW,`SH,`SC,`SB,`OUTW,`OUTH,`OUTC,`OUTB:
2715
                                xRt <= 9'd0;
2716
                default:        xRt <= {dAXC,dIR[24:20]};
2717
                endcase
2718
        `SW,`SH,`SC,`SB,`OUTW,`OUTH,`OUTC,`OUTB:
2719
                                xRt <= 9'd0;
2720
        `NOPI:          xRt <= 9'd0;
2721
        `BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
2722
                                xRt <= 9'd0;
2723
        default:        xRt <= {dAXC,dIR[29:25]};
2724
        endcase
2725
        if (dOpcode[6:4]==`IMM)
2726
                xRt <= 9'd0;
2727
 
2728
        // Set immediate value
2729
        if (xOpcode[6:4]==`IMM) begin
2730
                imm <= {xIR[38:0],dIR[24:0]};
2731
        end
2732
        else
2733
                casex(dOpcode)
2734
                `SETLO: imm <= {{32{dIR[31]}},dIR[31:0]};
2735
                `SETHI: imm <= {dIR[31:0],32'h00000000};
2736
                `BTRI:  imm <= {{44{dIR[19]}},dIR[19:0]};
2737
                `BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
2738
                        imm <= {{46{dIR[17]}},dIR[17:0]};
2739
                `ANDI:  imm <= {39'h7FFFFFFFFF,dIR[24:0]};
2740
                `ORI:   imm <= {39'h0000000000,dIR[24:0]};
2741
                `XORI:  imm <= {39'h0000000000,dIR[24:0]};
2742
                `RET:   imm <= {44'h00000000000,dIR[19:0]};
2743
                `MEMNDX:        imm <= {{51{dIR[19]}},dIR[19:7]};
2744
                default:        imm <= {{39{dIR[24]}},dIR[24:0]};
2745
                endcase
2746
 
2747
end
2748
 
2749
//---------------------------------------------------------
2750
// IFETCH:
2751
// - check for external hardware interrupt
2752
// - fetch instruction
2753
// - increment PC
2754
// - set special register defaults for some instructions
2755
//---------------------------------------------------------
2756
if (advanceI) begin
2757
        dextype <= `EX_NON;
2758
        if (iOpcode[6:4]!=`IMM) begin
2759
                epcnt <= epcnt + 5'd1;
2760
                case(epcnt)
2761
                5'd0:   AXC <= EP[0][ 3: 0];
2762
                5'd1:   AXC <= EP[0][ 7: 4];
2763
                5'd2:   AXC <= EP[0][11: 8];
2764
                5'd3:   AXC <= EP[0][15:12];
2765
                5'd4:   AXC <= EP[0][19:16];
2766
                5'd5:   AXC <= EP[0][23:20];
2767
                5'd6:   AXC <= EP[0][27:24];
2768
                5'd7:   AXC <= EP[0][31:28];
2769
                5'd8:   AXC <= EP[1][ 3: 0];
2770
                5'd9:   AXC <= EP[1][ 7: 4];
2771
                5'd10:  AXC <= EP[1][11: 8];
2772
                5'd11:  AXC <= EP[1][15:12];
2773
                5'd12:  AXC <= EP[1][19:16];
2774
                5'd13:  AXC <= EP[1][23:20];
2775
                5'd14:  AXC <= EP[1][27:24];
2776
                5'd15:  AXC <= EP[1][31:28];
2777
                5'd16:  AXC <= EP[2][ 3: 0];
2778
                5'd17:  AXC <= EP[2][ 7: 4];
2779
                5'd18:  AXC <= EP[2][11: 8];
2780
                5'd19:  AXC <= EP[2][15:12];
2781
                5'd20:  AXC <= EP[2][19:16];
2782
                5'd21:  AXC <= EP[2][23:20];
2783
                5'd22:  AXC <= EP[2][27:24];
2784
                5'd23:  AXC <= EP[2][31:28];
2785
                5'd24:  AXC <= EP[3][ 3: 0];
2786
                5'd25:  AXC <= EP[3][ 7: 4];
2787
                5'd26:  AXC <= EP[3][11: 8];
2788
                5'd27:  AXC <= EP[3][15:12];
2789
                5'd28:  AXC <= EP[3][19:16];
2790
                5'd29:  AXC <= EP[3][23:20];
2791
                5'd30:  AXC <= EP[3][27:24];
2792
                5'd31:  AXC <= EP[3][31:28];
2793
                endcase
2794
        end
2795
//      AXC <= EP[epcnt[4:3]][{epcnt[2:0],2'b11}:{epcnt[2:0],2'b00}];
2796
 
2797
//  Interrupt won't be recognized if the context is already processing another
2798
//  exception
2799
        if (nmi_edge & !StatusHWI[AXC]) begin
2800
                StatusHWI[AXC] <= 1'b1;
2801
                IPC[AXC] <= pc_axc;
2802
                nmi_edge <= 1'b0;
2803
                dirqf[AXC] <= 1'b1;
2804
                dIR <= `NOP_INSN;
2805
                dextype <= `EX_NMI;
2806
        end
2807
        else if (irq_i & !im & !StatusHWI[AXC]) begin
2808 16 robfinch
                im <= 1'b1;
2809 14 robfinch
                StatusHWI[AXC] <= 1'b1;
2810
                IPC[AXC] <= pc_axc;
2811
                dirqf[AXC] <= 1'b1;
2812
                dIR <= `NOP_INSN;
2813
                dextype <= `EX_IRQ;
2814
        end
2815
        // Are we filling the pipeline with NOP's as a result of a previous
2816
        // hardware interrupt ? Only NOP out the pipeline for the context
2817
        // servicing the interrupt.
2818
        else if (dirqf[AXC]|dFip[AXC]) begin
2819
                dIR <= `NOP_INSN;
2820
        end
2821
        else if (ITLBMiss)
2822
                dIR <= `NOP_INSN;
2823
        else begin
2824
                dIR <= insn;
2825
`include "insn_dump.v"
2826
        end
2827
        nopI <= 1'b0;
2828
        if (dOpcode[6:4]!=`IMM) begin
2829
                dpc <= pc_axc;
2830
        end
2831
        dAXC <= AXC;
2832
        casex(iOpcode)
2833
        `SETLO:         dRa <= {AXC,insn[36:32]};
2834
        `SETHI:         dRa <= {AXC,insn[36:32]};
2835
        default:        dRa <= {AXC,insn[34:30]};
2836
        endcase
2837
        dRb <= {AXC,insn[29:25]};
2838
        dRc <= {AXC,insn[24:20]};
2839
        if (ITLBMiss) begin
2840
                CauseCode[AXC] <= `EX_TLBI;
2841
                StatusEXL[AXC] <= 1'b1;
2842
                BadVAddr[AXC] <= pc_axc[63:13];
2843
                pc[AXC] <= `ITLB_MissHandler;
2844
                EPC[AXC] <= pc_axc;
2845
        end
2846
        else begin
2847
                dbranch_taken <= 1'b0;
2848
                pc[AXC] <= fnIncPC(pc_axc);
2849
                case(iOpcode)
2850
                `MISC:
2851
                        case(iFunc)
2852
                        `FIP:   dFip[AXC] <= 1'b1;
2853
                        default:        ;
2854
                        endcase
2855
                `JMP,`CALL:
2856
                        begin
2857
                                dbranch_taken <= 1'b1;
2858
                                pc[AXC] <= jmp_tgt;
2859
                        end
2860
                `BTRR:
2861
                        case(insn[4:0])
2862 21 robfinch
                        `BEQ,`BNE,`BLT,`BLE,`BGT,`BGE,`BLTU,`BLEU,`BGTU,`BGEU,`BAND,`BOR,`BNR,`LOOP,`BRA:
2863 14 robfinch
                                if (predict_taken) begin
2864
                                        $display("Taking predicted branch: %h",{pc_axc[63:4] + {{42{insn[24]}},insn[24:7]},insn[6:5],2'b00});
2865
                                        dbranch_taken <= 1'b1;
2866
                                        pc[AXC] <= {pc_axc[63:4] + {{42{insn[24]}},insn[24:7]},insn[6:5],2'b00};
2867
                                end
2868
                        default:        ;
2869
                        endcase
2870
                `BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
2871
                        begin
2872
                                if (predict_taken) begin
2873
                                        dbranch_taken <= 1'b1;
2874
                                        pc[AXC] <= {pc_axc[63:4] + {{50{insn[29]}},insn[29:20]},insn[19:18],2'b00};
2875
                                end
2876
                        end
2877
                `TRAPcc:        if (predict_taken) begin pc[AXC] <= {TBA[63:13],`GEN_TRAP_OFFSET}; dbranch_taken <= 1'b1; end
2878
                `TRAPcci:       if (predict_taken) begin pc[AXC] <= {TBA[63:13],`GEN_TRAP_OFFSET}; dbranch_taken <= 1'b1; end
2879
                default:        ;
2880
                endcase
2881
        end
2882
end
2883
 
2884
//`include "RPSTAGE.v"
2885
//---------------------------------------------------------
2886
// EXECUTE - part two:
2887
// - override the default program counter increment for
2888
//   control flow instructions
2889
// - NOP out the instructions following a branch in the
2890
//   pipeline
2891
//---------------------------------------------------------
2892
if (advanceX) begin
2893
        case(xOpcode)
2894
        `MISC:
2895
                case(xFunc)
2896
                `IRET:
2897
                        if (StatusHWI[xAXC]) begin
2898
                                pc[xAXC] <= IPC[xAXC];
2899
                                if (xAXC==AXC) begin
2900
                                        dpc <= EPC[xAXC];
2901
                                        dIR <= `NOP_INSN;
2902
                                end
2903
                                if (xAXC==dAXC) begin
2904
                                        xpc <= EPC[xAXC];
2905
                                        xIR <= `NOP_INSN;
2906
                                        xRt <= 9'd0;
2907
                                end
2908
                                StatusHWI[xAXC] <= 1'b0;
2909
                        end
2910
                `ERET:  begin
2911
                                        if (StatusEXL[xAXC]) begin
2912
                                                pc[xAXC] <= EPC[xAXC];
2913
                                                if (xAXC==AXC) begin
2914
                                                        dpc <= EPC[xAXC];
2915
                                                        dIR <= `NOP_INSN;
2916
                                                end
2917
                                                if (xAXC==dAXC) begin
2918
                                                        xpc <= EPC[xAXC];
2919
                                                        xIR <= `NOP_INSN;
2920
                                                        xRt <= 9'd0;
2921
                                                end
2922
                                        end
2923
                                        StatusEXL[xAXC] <= 1'b0;
2924
                                end
2925
                default:        ;
2926
                endcase
2927
        `BTRR:
2928
                case(xIR[4:0])
2929
        // BEQ r1,r2,label
2930 21 robfinch
                `BEQ,`BNE,`BLT,`BLE,`BGT,`BGE,`BLTU,`BLEU,`BGTU,`BGEU,`BAND,`BOR,`BNR,`BRA,`BRN,`LOOP:
2931 14 robfinch
                        if (takb & !xbranch_taken) begin
2932
                                $display("Taking branch %h",xpc[63:4] + {{42{xIR[24]}},xIR[24:7]});
2933
                                pc[xAXC][63:4] <= xpc[63:4] + {{42{xIR[24]}},xIR[24:7]};
2934
                                pc[xAXC][3:2] <= xIR[6:5];
2935
                                if (xAXC==AXC) begin
2936
                                        dpc[63:4] <= xpc[63:4] + {{42{xIR[24]}},xIR[24:7]};
2937
                                        dpc[3:2] <= xIR[6:5];
2938
                                        dIR <= `NOP_INSN;
2939
                                end
2940
                                if (xAXC==dAXC) begin
2941
                                        xpc[63:4] <= xpc[63:4] + {{42{xIR[24]}},xIR[24:7]};
2942
                                        xpc[3:2] <= xIR[6:5];
2943
                                        xIR <= `NOP_INSN;
2944
                                        xRt <= 9'd0;
2945
                                end
2946
                        end
2947
                        else if (!takb & xbranch_taken) begin
2948
                                $display("Fixing branch misprediction %h",fnIncPC(xpc));
2949
                                pc[xAXC] <= fnIncPC(xpc);
2950
                                if (xAXC==AXC) begin
2951
                                        dpc <= fnIncPC(xpc);
2952
                                        dIR <= `NOP_INSN;
2953
                                end
2954
                                if (xAXC==dAXC) begin
2955
                                        xpc <= fnIncPC(xpc);
2956
                                        xIR <= `NOP_INSN;
2957
                                        xRt <= 9'd0;
2958
                                end
2959
                        end
2960
        // BEQ r1,r2,r10
2961
                `BEQR,`BNER,`BLTR,`BLER,`BGTR,`BGER,`BLTUR,`BLEUR,`BGTUR,`BGEUR://,`BANDR,`BORR,`BNRR:
2962
                        if (takb) begin
2963
                                pc[xAXC][63:2] <= c[63:2];
2964
                                pc[xAXC][1:0] <= 2'b00;
2965
                                if (xAXC==AXC) begin
2966
                                        dpc[63:2] <= c[63:2];
2967
                                        dpc[1:0] <= 2'b00;
2968
                                        dIR <= `NOP_INSN;
2969
                                end
2970
                                if (dAXC==xAXC) begin
2971
                                        xpc[63:2] <= c[63:2];
2972
                                        xpc[1:0] <= 2'b00;
2973
                                        xIR <= `NOP_INSN;
2974
                                        xRt <= 9'd0;
2975
                                end
2976
                        end
2977
                default:        ;
2978
                endcase
2979
        // JMP and CALL change the program counter immediately in the IF stage.
2980
        // There's no work to do here. The pipeline does not need to be cleared.
2981
        `JMP:   ;
2982
        `CALL:  ;
2983
        `JAL:   begin
2984
                                pc[xAXC][63:2] <= a[63:2] + imm[63:2];
2985
                                if (AXC==xAXC) begin
2986
                                        dIR <= `NOP_INSN;
2987
                                        dpc[63:2] <= a[63:2] + imm[63:2];
2988
                                end
2989
                                if (dAXC==xAXC) begin
2990
                                        xpc[63:2] <= a[63:2] + imm[63:2];
2991
                                        xIR <= `NOP_INSN;
2992
                                        xRt <= 9'd0;
2993
                                end
2994
                        end
2995
        `RET:   begin
2996
                                pc[xAXC][63:2] <= b[63:2];
2997
                                $display("returning to: %h", {b,2'b00});
2998
                                if (AXC==xAXC) begin
2999
                                        dpc[63:2] <= b[63:2];
3000
                                        dIR <= `NOP_INSN;
3001
                                end
3002
                                if (xAXC==dAXC) begin
3003
                                        xpc[63:2] <= b[63:2];
3004
                                        xIR <= `NOP_INSN;
3005
                                        xRt <= 9'd0;
3006
                                end
3007
                        end
3008
        // BEQ r1,#3,r10
3009
        `BTRI:
3010
                if (takb) begin
3011
                        pc[xAXC][63:2] <= b[63:2];
3012
                        pc[xAXC][1:0] <= 2'b00;
3013
                        if (xAXC==AXC) begin
3014
                                dpc[63:2] <= b[63:2];
3015
                                dpc[1:0] <= 2'b00;
3016
                                dIR <= `NOP_INSN;
3017
                        end
3018
                        if (dAXC==xAXC) begin
3019
                                xpc[63:2] <= b[63:2];
3020
                                xpc[1:0] <= 2'b00;
3021
                                xIR <= `NOP_INSN;
3022
                                xRt <= 9'd0;
3023
                        end
3024
                end
3025
        // BEQI r1,#3,label
3026
        `BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
3027
                if (takb) begin
3028
                        if (!xbranch_taken) begin
3029
                                pc[xAXC][63:4] <= xpc[63:4] + {{50{xIR[29]}},xIR[29:20]};
3030
                                pc[xAXC][3:2] <= xIR[19:18];
3031
                                if (AXC==xAXC) begin
3032
                                        dpc[63:4] <= xpc[63:4] + {{50{xIR[29]}},xIR[29:20]};
3033
                                        dpc[3:2] <= xIR[19:18];
3034
                                        dIR <= `NOP_INSN;
3035
                                end
3036
                                if (dAXC==xAXC) begin
3037
                                        xpc[63:4] <= xpc[63:4] + {{50{xIR[29]}},xIR[29:20]};
3038
                                        xpc[3:2] <= xIR[19:18];
3039
                                        xIR <= `NOP_INSN;
3040
                                        xRt <= 9'd0;
3041
                                end
3042
                        end
3043
                end
3044
                else begin
3045
                        if (xbranch_taken) begin
3046
                                pc[xAXC] <= fnIncPC(xpc);
3047
                                if (AXC==xAXC) begin
3048
                                        dpc <= fnIncPC(xpc);
3049
                                        dIR <= `NOP_INSN;
3050
                                end
3051
                                if (dAXC==xAXC) begin
3052
                                        xpc <= fnIncPC(xpc);
3053
                                        xIR <= `NOP_INSN;
3054
                                        xRt <= 9'd0;
3055
                                end
3056
                        end
3057
                end
3058
        `TRAPcc,`TRAPcci:
3059
                if (takb) begin
3060
                        StatusEXL[xAXC] <= 1'b1;
3061
                        CauseCode[xAXC] <= `EX_TRAP;
3062
                        EPC[xAXC] <= xpc;
3063
                        if (!xbranch_taken) begin
3064
                                pc[xAXC] <= {TBA[63:13],`GEN_TRAP_OFFSET};
3065
                                if (xAXC==AXC) begin
3066
                                        dpc <= {TBA[63:13],`GEN_TRAP_OFFSET};
3067
                                        dIR <= `NOP_INSN;
3068
                                end
3069
                                if (xAXC==dAXC) begin
3070
                                        xpc <= {TBA[63:13],`GEN_TRAP_OFFSET};
3071
                                        xIR <= `NOP_INSN;
3072
                                        xRt <= 9'd0;
3073
                                end
3074
                        end
3075
                end
3076
                else begin
3077
                        if (xbranch_taken) begin
3078
                                pc[xAXC] <= fnIncPC(xpc);
3079
                                if (xAXC==AXC) begin
3080
                                        dpc <= fnIncPC(xpc);
3081
                                        dIR <= `NOP_INSN;
3082
                                end
3083
                                if (xAXC==dAXC) begin
3084
                                        xpc <= fnIncPC(xpc);
3085
                                        xIR <= `NOP_INSN;
3086
                                        xRt <= 9'd0;
3087
                                end
3088
                        end
3089
                end
3090
        default:        ;
3091
        endcase
3092
        if (dbz_error) begin
3093
                $display("Divide by zero error");
3094
                CauseCode[xAXC] <= `EX_DBZ;
3095
                StatusEXL[xAXC] <= 1'b1;
3096
                EPC[xAXC] <= xpc;
3097
                pc[xAXC] <= {TBA[63:13],`DBZ_TRAP_OFFSET};
3098
                if (xAXC==AXC) begin
3099
                        dpc <= {TBA[63:13],`DBZ_TRAP_OFFSET};
3100
                        dIR <= `NOP_INSN;
3101
                end
3102
                if (xAXC==dAXC) begin
3103
                        xpc <= {TBA[63:13],`DBZ_TRAP_OFFSET};
3104
                        xIR <= `NOP_INSN;
3105
                        xRt <= 9'd0;
3106
                end
3107
        end
3108
        if (ovr_error) begin
3109
                $display("Overflow error");
3110
                CauseCode[xAXC] <= `EX_OFL;
3111
                StatusEXL[xAXC] <= 1'b1;
3112
                EPC[xAXC] <= xpc;
3113
                pc[xAXC] <= {TBA[63:13],`OFL_TRAP_OFFSET};
3114
                if (xAXC==AXC) begin
3115
                        dpc <= {TBA[63:13],`OFL_TRAP_OFFSET};
3116
                        dIR <= `NOP_INSN;
3117
                end
3118
                if (xAXC==dAXC) begin
3119
                        xpc <= {TBA[63:13],`OFL_TRAP_OFFSET};
3120
                        xIR <= `NOP_INSN;
3121
                        xRt <= 9'd0;
3122
                end
3123
        end
3124 16 robfinch
        if (priv_violation) begin
3125
                $display("Privledge violation");
3126
                CauseCode[xAXC] <= `EX_PRIV;
3127
                StatusEXL[xAXC] <= 1'b1;
3128
                EPC[xAXC] <= xpc;
3129
                pc[xAXC] <= {TBA[63:13],`PRIV_OFFSET};
3130
                if (xAXC==AXC) begin
3131
                        dpc <= {TBA[63:13],`PRIV_OFFSET};
3132
                        dIR <= `NOP_INSN;
3133
                end
3134
                if (xAXC==dAXC) begin
3135
                        xpc <= {TBA[63:13],`PRIV_OFFSET};
3136
                        xIR <= `NOP_INSN;
3137
                        xRt <= 9'd0;
3138
                end
3139
        end
3140 14 robfinch
end
3141
 
3142
//---------------------------------------------------------
3143
// MEMORY1 (M1') - part two:
3144
// Check for a TLB miss.
3145
//---------------------------------------------------------
3146
if (advanceM1) begin
3147
        if (m1IsLoad|m1IsStore) begin
3148
                if (DTLBMiss) begin
3149
                        $display("DTLB miss on address: %h",ea);
3150
                        m1extype <= `EX_TLBD;
3151
                        CauseCode[m1AXC] <= `EX_TLBD;
3152
                        StatusEXL[m1AXC] <= 1'b1;
3153
                        BadVAddr[m1AXC] <= ea[63:13];
3154
                        EPC[m1AXC] <= m1pc;
3155
                        pc[m1AXC] <= `DTLB_MissHandler;
3156
                        if (m1AXC==xAXC) begin
3157
                                m1pc <= `DTLB_MissHandler;
3158
                                m1Opcode <= `NOPI;
3159
                                m1Rt <= 9'd0;
3160
                        end
3161
                        if (m1AXC==dAXC) begin
3162
                                xpc <= `DTLB_MissHandler;
3163
                                xIR <= `NOP_INSN;
3164
                                xRt <= 9'd0;
3165
                        end
3166
                        if (m1AXC==AXC) begin
3167
                                dpc <= `DTLB_MissHandler;
3168
                                dIR <= `NOP_INSN;
3169
                        end
3170
                end
3171
        end
3172
end
3173
 
3174
//---------------------------------------------------------
3175
// MEMORY2 (M2')
3176
//---------------------------------------------------------
3177
if (advanceM2) begin
3178
end
3179
 
3180
//---------------------------------------------------------
3181
// MEMORY4 (M3')
3182
//---------------------------------------------------------
3183
if (advanceM3) begin
3184
end
3185
 
3186
//---------------------------------------------------------
3187
// MEMORY4 (M4')
3188
// - no exceptions
3189
//---------------------------------------------------------
3190
if (advanceM4) begin
3191
end
3192
 
3193
//---------------------------------------------------------
3194
// WRITEBACK (WB') - part two:
3195
// - vector to exception handler address
3196
// In the case of a hardware interrupt (NMI/IRQ) we know
3197
// the pipeline following the interrupt is filled with
3198
// NOP instructions. This means there is no need to 
3199
// invalidate the pipeline.
3200
//---------------------------------------------------------
3201
if (advanceW) begin
3202
        case(wextype)
3203
        `EX_RST:        pc[wAXC] <= `RESET_VECTOR;
3204
        `EX_NMI:        pc[wAXC] <= `NMI_VECTOR;
3205
        `EX_IRQ:        pc[wAXC] <= `IRQ_VECTOR;
3206
        default:        ;//pc[63:2] <= exception_address[63:2];
3207
        endcase
3208
end
3209
 
3210
 
3211
//---------------------------------------------------------
3212
// Cache loader
3213
//---------------------------------------------------------
3214
if (rst_i) begin
3215
        cstate <= IDLE;
3216
//      wr_icache <= 1'b0;
3217
        wr_dcache <= 1'b0;
3218
end
3219
else begin
3220
//wr_icache <= 1'b0;
3221
wr_dcache <= 1'b0;
3222
case(cstate)
3223
IDLE:
3224
        // we can't do anything until the command buffer is available
3225
        // in theory the command fifo should always be available
3226
        if (!cmd_full) begin
3227
                if (triggerDCacheLoad) begin
3228
                        dcaccess <= 1'b1;
3229 16 robfinch
                        if (pea[63]) begin
3230
                                cmd_en <= 1'b1;
3231
                                cmd_instr <= 3'b001;    // READ
3232
                                cmd_byte_addr <= {pea[29:5],5'b00000};
3233
                                dadr_o <= {pea[63:5],5'b00000};
3234
                                cmd_bl <= 6'd8; // Eight words per cache line
3235
                                cstate <= DCACT;
3236
                        end
3237
                        else begin
3238
                                bte_o <= 2'b00;                 // linear burst
3239
                                cti_o <= 3'b010;                // burst access
3240
                                cyc_o <= 1'b1;
3241
                                stb_o <= 1'b1;
3242
                                adr_o <= {pea[63:5],5'h00};
3243
                                dadr_o <= {pea[63:5],5'h00};
3244
                                cstate <= DCACT2;
3245
                        end
3246 14 robfinch
                end
3247
                else if (triggerICacheLoad) begin
3248
                        if (!ppc[63]) begin
3249
                                icaccess <= 1'b1;
3250
                                cmd_en <= 1'b1; // the command fifo should always be available
3251
                                cmd_instr <= 3'b001;    // READ
3252
                                cmd_byte_addr <= {ppc[29:6],6'h00};
3253
                                iadr_o <= {ppc[63:6],6'h00};
3254
                                cmd_bl <= 6'd16;        // Sixteen words per cache line
3255
                                cstate <= ICACT;
3256
                        end
3257
                        else begin
3258
                                iciaccess <= 1'b1;
3259
                                bte_o <= 2'b00;                 // linear burst
3260
                                cti_o <= 3'b010;                // burst access
3261
                                cyc_o <= 1'b1;
3262
                                stb_o <= 1'b1;
3263
                                adr_o <= {ppc[63:6],6'h00};
3264
                                iadr_o <= {ppc[63:6],6'h00};
3265
                                cstate <= ICACT1;
3266
                        end
3267
                end
3268
        end
3269
        // Sometime after the read command is issued, the read fifo will begin to fill
3270
ICACT:
3271
        begin
3272
                rd_en <= 1'b1;
3273
                cstate <= ICACT0;
3274
        end
3275
//ICACT0:       // Read word 0
3276
        // At this point it should not be necessary to check rd_empty
3277
//      if (!rd_empty) begin
3278
//              wr_icache <= 1'b1;
3279
//              idat <= rd_data;
3280
//              cstate <= ICACT1;
3281
//      end
3282
 
3283
ICACT0: // Read word 1-15
3284
        // Might have to wait for subsequent data to be available
3285
        if (!rd_empty) begin
3286
//              wr_icache <= 1'b1;
3287
//              idat <= rd_data;
3288
                iadr_o[5:2] <= iadr_o[5:2] + 4'h1;
3289
                if (iadr_o[5:2]==4'hF) begin
3290
                        rd_en <= 1'b0;
3291
                        tmem[iadr_o[12:6]] <= {1'b1,iadr_o[63:13]};     // This will cause ihit to go high
3292
                        tvalid[iadr_o[12:6]] <= 1'b1;
3293
                        cstate <= ICDLY;
3294
                end
3295
        end
3296
ICDLY:
3297
        // The fifo should have emptied out, if not we force it to empty
3298
        if (!rd_empty) begin
3299
                rd_en <= 1'b1;
3300
        end
3301
        else begin
3302
                icaccess <= 1'b0;
3303
                rd_en <= 1'b0;
3304
                cstate <= IDLE;
3305
        end
3306
 
3307
// WISHBONE burst accesses
3308
//
3309
ICACT1:
3310
        if (ack_i) begin
3311
                adr_o[5:2] <= adr_o[5:2] + 4'd1;
3312
                iadr_o[5:2] <= iadr_o[5:2] + 4'd1;
3313
                if (adr_o[5:2]==4'hE)
3314
                        cti_o <= 3'b111;        // Last cycle ahead
3315
                if (adr_o[5:2]==4'hF) begin
3316
                        cti_o <= 3'b000;        // back to non-burst mode
3317
                        cyc_o <= 1'b0;
3318
                        stb_o <= 1'b0;
3319
                        tmem[iadr_o[12:6]] <= {1'b1,iadr_o[63:13]};     // This will cause ihit to go high
3320
                        tvalid[iadr_o[12:6]] <= 1'b1;
3321
                        iciaccess <= 1'b0;
3322
                        cstate <= IDLE;
3323
                end
3324
        end
3325
 
3326
DCACT:
3327
        begin
3328
                rd_en <= 1'b1;          // Data should be available on the next clock cycle
3329
                cstate <= DCACT0;
3330
        end
3331
DCACT0: // Read word 0
3332
        // At this point it should not be necessary to check rd_empty
3333
        if (!rd_empty) begin
3334
                wr_dcache <= 1'b1;
3335
                ddat <= rd_data;
3336
                dadr_o[4:2] <= 3'b000;
3337
                cstate <= DCACT1;
3338
        end
3339
DCACT1: // Read word 1
3340
        // Might have to wait for subsequent data to be available
3341
        if (!rd_empty) begin
3342
                wr_dcache <= 1'b1;
3343
                ddat <= rd_data;
3344
                dadr_o[4:2] <= dadr_o[4:2]+3'd1;
3345
                if (dadr_o[4:2]==3'b111) begin
3346
                        rd_en <= 1'b0;
3347
                        cstate <= DCDLY;
3348
                end
3349
        end
3350 16 robfinch
// WISHBONE burst accesses
3351
//
3352
DCACT2:
3353
        if (ack_i) begin
3354
                adr_o[4:2] <= adr_o[4:2] + 3'd1;
3355
                dadr_o[4:2] <= dadr_o[4:2] + 3'd1;
3356
                if (adr_o[4:2]==3'h6)
3357
                        cti_o <= 3'b111;        // Last cycle ahead
3358
                if (adr_o[4:2]==3'h7) begin
3359
                        cti_o <= 3'b000;        // back to non-burst mode
3360
                        cyc_o <= 1'b0;
3361
                        stb_o <= 1'b0;
3362
                        dcaccess <= 1'b0;
3363
                        cstate <= IDLE;
3364
                end
3365
        end
3366
 
3367 14 robfinch
DCDLY:
3368
        // The fifo should have emptied out, if not, empty it out.
3369
        if (!rd_empty) begin
3370
                rd_en <= 1'b1;
3371
        end
3372
        else begin
3373
                dcaccess <= 1'b0;
3374
                rd_en <= 1'b0;
3375
                cstate <= IDLE;
3376
        end
3377
endcase
3378
end
3379
 
3380
end
3381
 
3382
endmodule

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