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[/] [raptor64/] [trunk/] [rtl/] [verilog/] [Raptor64mc.v] - Blame information for rev 14

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1 14 robfinch
// ============================================================================
2
// (C) 2012 Robert Finch
3
// All Rights Reserved.
4
// robfinch<remove>@opencores.org
5
//
6
// Raptor64.v
7
//  - 64 bit CPU
8
//
9
// This source file is free software: you can redistribute it and/or modify 
10
// it under the terms of the GNU Lesser General Public License as published 
11
// by the Free Software Foundation, either version 3 of the License, or     
12
// (at your option) any later version.                                      
13
//                                                                          
14
// This source file is distributed in the hope that it will be useful,      
15
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
16
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
17
// GNU General Public License for more details.                             
18
//                                                                          
19
// You should have received a copy of the GNU General Public License        
20
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
21
//                                                                          
22
// ============================================================================
23
//
24
`define RESET_VECTOR    64'hFFFF_FFFF_FFFF_FFF0
25
`define NMI_VECTOR              64'hFFFF_FFFF_FFFF_FFE0
26
`define IRQ_VECTOR              64'hFFFF_FFFF_FFFF_FFD0
27
`define TRAP_VECTOR             64'h0000_0000_0000_0000
28
 
29
`define TLBMissPage             52'hFFFF_FFFF_FFFF_F
30
`define ITLB_MissHandler        64'hFFFF_FFFF_FFFF_FFC0
31
`define DTLB_MissHandler        64'hFFFF_FFFF_FFFF_FFB0
32
 
33
`define GEN_TRAP_OFFSET         13'h0200
34
`define DBZ_TRAP_OFFSET         13'h0050
35
`define OFL_TRAP_OFFSET         13'h0070
36
 
37
`define EX_NON          8'd0
38
`define EX_RST          8'd1
39
`define EX_NMI          8'd2
40
`define EX_IRQ          8'd3
41
`define EX_TRAP         8'd4
42
`define EX_OFL          8'd16   // overflow
43
`define EX_DBZ          8'd17   // divide by zero
44
`define EX_TLBI         8'd19   // TLB exception - ifetch
45
`define EX_TLBD         8'd20   // TLB exception - data
46
 
47
`define EXCEPT_Int              5'd00
48
`define EXCEPT_Mod              5'd01   // TLB modification
49
`define EXCEPT_TLBL             5'd02   // TLB exception - load or ifetch
50
`define EXCEPT_TLBS             5'd03   // TLB exception - store
51
`define EXCEPT_AdEL             5'd04   // Address error - load or ifetch
52
`define EXCEPT_AdES             5'd05   // Address error - store
53
`define EXCEPT_IBE              5'd06   // Bus Error - instruction fetch
54
`define EXCEPT_DBE              5'd07   // Bus Error - load or store
55
`define EXCEPT_Sys              5'd08
56
`define EXCEPT_Bp               5'd09
57
`define EXCEPT_RI               5'd10   // reserved instruction
58
`define EXCEPT_CpU              5'd11   // Coprocessor unusable
59
`define EXCEPT_Ov               5'd12   // Integer Overflow
60
`define EXCEPT_Tr               5'd13   // Trap exception
61
// 14-22 Reserved
62
`define EXCEPT_WATCH    5'd23
63
`define EXCEPT_MCheck   5'd24   // Machine check
64
// 25-31 Reserved
65
 
66
 
67
`define MISC    7'd0
68
`define         BRK             7'd0
69
`define         IRQ             7'd1
70
`define     FIP         7'd20
71
`define         IRET    7'd32
72
`define         ERET    7'd33
73
`define         WAIT    7'd40
74
`define         TLBP    7'd49
75
`define     TLBR        7'd50
76
`define     TLBWI       7'd51
77
`define     TLBWR       7'd52
78
`define         CLI             7'd64
79
`define         SEI             7'd65
80
`define R               7'd1
81
`define         COM             7'd4
82
`define         NOT             7'd5
83
`define         NEG             7'd6
84
`define         ABS             7'd7
85
`define         SWAP    7'd13
86
`define         CTLZ    7'd16
87
`define         CTLO    7'd17
88
`define         CTPOP   7'd18
89
`define         SEXT8   7'd19
90
`define         SEXT16  7'd20
91
`define         SEXT32  7'd21
92
`define         SQRT    7'd24
93
`define         REDOR   7'd30
94
`define         REDAND  7'd31
95
`define     MFSPR       7'd40
96
`define     MTSPR       7'd41
97
`define         TLBIndex        6'd01
98
`define         TLBRandom               6'd02
99
`define         PageTableAddr   6'd04
100
`define         BadVAddr        6'd08
101
`define         TLBPhysPage0    6'd10
102
`define         TLBPhysPage1    6'd11
103
`define         TLBVirtPage             6'd12
104
`define                 TLBPageMask             6'd13
105
`define                 TLBASID                 6'd14
106
`define         ASID                    6'd15
107
`define                 Wired                   6'd16
108
`define         EP0             6'd17
109
`define         EP1             6'd18
110
`define         EP2             6'd19
111
`define         EP3             6'd20
112
`define         AXC             6'd21
113
`define                 Tick                    6'd22
114
`define                 EPC                             6'd23
115
`define                 CauseCode               6'd24
116
`define                 TBA                             6'd25
117
`define         OMG             7'd50
118
`define         CMG             7'd51
119
`define         OMGI    7'd52
120
`define         CMGI    7'd53
121
`define         MFTBA   7'd58
122
`define         MTTBA   7'd59
123
`define RR      7'd2
124
`define         ADD             7'd2
125
`define         ADDU    7'd3
126
`define         SUB             7'd4
127
`define         SUBU    7'd5
128
`define         CMP             7'd6
129
`define         CMPU    7'd7
130
`define         AND             7'd8
131
`define         OR              7'd9
132
`define         XOR             7'd10
133
`define         ANDC    7'd11
134
`define         NAND    7'd12
135
`define         NOR             7'd13
136
`define         XNOR    7'd14
137
`define         ORC             7'd15
138
`define         MIN             7'd20
139
`define         MAX             7'd21
140
`define         MULU    7'd24
141
`define         MULS    7'd25
142
`define         DIVU    7'd26
143
`define         DIVS    7'd27
144
`define         MOD             7'd28
145
`define         MOVZ    7'd30
146
`define         MOVNZ   7'd31
147
 
148
`define         SHL             7'd40
149
`define         SHRU    7'd41
150
`define         ROL             7'd42
151
`define         ROR             7'd43
152
`define         SHR             7'd44
153
`define         ROLAM   7'd45
154
 
155
`define         NOP             7'd60
156
 
157
`define         SLT             7'd96
158
`define         SLE             7'd97
159
`define         SGT             7'd98
160
`define         SGE             7'd99
161
`define         SLTU    7'd100
162
`define         SLEU    7'd101
163
`define         SGTU    7'd102
164
`define         SGEU    7'd103
165
`define         SEQ             7'd104
166
`define         SNE             7'd105
167
 
168
`define     BCD_ADD     7'd110
169
`define     BCD_SUB 7'd111
170
 
171
`define SHFTI   7'd3
172
`define SHLI            7'd0
173
`define SHRUI           7'd1
174
`define ROLI            7'd2
175
`define SHRI            7'd3
176
`define RORI            7'd4
177
`define ROLAMI          7'd5
178
`define BFINS           7'd8
179
`define BFSET           7'd9
180
`define BFCLR           7'd10
181
`define BFCHG           7'd11
182
 
183
`define ADDI    7'd4
184
`define ADDUI   7'd5
185
`define SUBI    7'd6
186
`define SUBUI   7'd7
187
`define CMPI    7'd8
188
`define CMPUI   7'd9
189
`define ANDI    7'd10
190
`define ORI             7'd11
191
`define XORI    7'd12
192
 
193
`define MULUI   7'd13
194
`define MULSI   7'd14
195
`define DIVUI   7'd15
196
`define DIVSI   7'd16
197
 
198
`define TRAPcc  7'd17
199
`define         TEQ             7'd0
200
`define         TNE             7'd1
201
`define         TLT             7'd2
202
`define         TLE             7'd3
203
`define         TGT             7'd4
204
`define         TGE             7'd5
205
`define         TLO             7'd6
206
`define         TLS             7'd7
207
`define         THI             7'd8
208
`define         THS             7'd9
209
`define         TRAP    7'd10
210
`define         TRN             7'd11
211
`define TRAPcci 7'd18
212
`define         TEQI    5'd0
213
`define         TNEI    5'd1
214
`define         TLTI    5'd2
215
`define         TLEI    5'd3
216
`define         TGTI    5'd4
217
`define         TGEI    5'd5
218
`define         TLOI    5'd6
219
`define         TLSI    5'd7
220
`define         THII    5'd8
221
`define         THSI    5'd9
222
`define         TRAI    5'd10
223
`define         TRNI    5'd11
224
`define SETLO   7'b00101xx
225
`define CALL    7'd24
226
`define JMP             7'd25
227
`define JAL             7'd26
228
`define RET             7'd27
229
`define SETHI   7'b00111xx
230
 
231
`define LB              7'd32
232
`define LC              7'd33
233
`define LH              7'd34
234
`define LW              7'd35
235
`define LP              7'd36
236
`define LBU             7'd37
237
`define LCU             7'd38
238
`define LHU             7'd39
239
`define LSH             7'd40
240
`define LSW             7'd41
241
`define LF              7'd42
242
`define LFD             7'd43
243
`define LFP             7'd44
244
`define LFDP    7'd45
245
`define LWR             7'd46
246
`define LDONE   7'd47
247
 
248
`define SB              7'd48
249
`define SC              7'd49
250
`define SH              7'd50
251
`define SW              7'd51
252
`define SP              7'd52
253
`define MEMNDX  7'd53
254
`define SSH             7'd56
255
`define SSW             7'd57
256
`define SF              7'd58
257
`define SFD             7'd59
258
`define SFP             7'd60
259
`define SFDP    7'd61
260
`define SWC             7'd62
261
 
262
`define INB             7'd64
263
`define INCH    7'd65
264
`define INH             7'd66
265
`define INW             7'd67
266
`define OUTB    7'd72
267
`define OUTC    7'd73
268
`define OUTH    7'd74
269
`define OUTW    7'd75
270
 
271
`define BLTI    7'd80
272
`define BGEI    7'd81
273
`define BLEI    7'd82
274
`define BGTI    7'd83
275
`define BLTUI   7'd84
276
`define BGEUI   7'd85
277
`define BLEUI   7'd86
278
`define BGTUI   7'd87
279
`define BEQI    7'd88
280
`define BNEI    7'd89
281
`define BRAI    7'd90
282
`define BRNI    7'd91
283
 
284
`define BTRI    7'd94
285
`define         BLTRI   5'd0
286
`define         BGERI   5'd1
287
`define         BLERI   5'd2
288
`define         BGTRI   5'd3
289
`define         BLTURI  5'd4
290
`define         BGEURI  5'd5
291
`define         BLEURI  5'd6
292
`define         BGTURI  5'd7
293
`define         BEQRI   5'd8
294
`define         BNERI   5'd9
295
`define         BRARI   5'd10
296
`define         BRNRI   5'd11
297
`define         BANDRI  5'd12
298
`define         BORRI   5'd13
299
`define BTRR    7'd95
300
`define         BLT             5'd0
301
`define         BGE             5'd1
302
`define         BLE             5'd2
303
`define         BGT             5'd3
304
`define         BLTU    5'd4
305
`define         BGEU    5'd5
306
`define         BLEU    5'd6
307
`define         BGTU    5'd7
308
`define         BEQ             5'd8
309
`define         BNE             5'd9
310
`define         BRA             5'd10
311
`define         BRN             5'd11
312
`define         BAND    5'd12
313
`define         BOR             5'd13
314
`define         BNR             5'd14
315
`define         BLTR    5'd16
316
`define         BGER    5'd17
317
`define         BLER    5'd18
318
`define         BGTR    5'd19
319
`define         BLTUR   5'd20
320
`define         BGEUR   5'd21
321
`define         BLEUR   5'd22
322
`define         BGTUR   5'd23
323
`define         BEQR    5'd24
324
`define         BNER    5'd25
325
`define         BRAR    5'd26
326
`define         BRNR    5'd27
327
 
328
 
329
`define SLTI    7'd96
330
`define SLEI    7'd97
331
`define SGTI    7'd98
332
`define SGEI    7'd99
333
`define SLTUI   7'd100
334
`define SLEUI   7'd101
335
`define SGTUI   7'd102
336
`define SGEUI   7'd103
337
`define SEQI    7'd104
338
`define SNEI    7'd105
339
 
340
`define FPLOO   7'd109
341
`define FPZL    7'd110
342
`define NOPI    7'd111
343
 
344
`define IMM             3'd7
345
 
346
`define NOP_INSN        42'b1101111_000_00000000_00000000_00000000_00000000
347
 
348
module Raptor64mc(rst_i, clk_i, nmi_i, irq_i,
349
        bte_o, cti_o, cyc_o, stb_o, ack_i, we_o, sel_o, rsv_o, adr_o, dat_i, dat_o, sys_adv, sys_adr,
350
        cmd_en, cmd_instr, cmd_bl, cmd_byte_addr, cmd_full,
351
        wr_en, wr_data, wr_mask, wr_full, wr_empty,
352
        rd_en, rd_data, rd_empty
353
);
354
parameter IDLE = 5'd1;
355
parameter ICACT = 5'd2;
356
parameter ICACT0 = 5'd3;
357
parameter ICACT1 = 5'd4;
358
parameter ICACT2 = 5'd5;
359
parameter ICACT3 = 5'd6;
360
parameter ICACT4 = 5'd7;
361
parameter ICACT5 = 5'd8;
362
parameter ICACT6 = 5'd9;
363
parameter ICACT7 = 5'd10;
364
parameter ICDLY = 5'd11;
365
parameter DCIDLE = 5'd20;
366
parameter DCACT = 5'd21;
367
parameter DCACT0 = 5'd22;
368
parameter DCACT1 = 5'd23;
369
parameter DCACT2 = 5'd24;
370
parameter DCACT3 = 5'd25;
371
parameter DCACT4 = 5'd26;
372
parameter DCACT5 = 5'd27;
373
parameter DCACT6 = 5'd28;
374
parameter DCACT7 = 5'd29;
375
parameter DCDLY = 5'd30;
376
 
377
input rst_i;
378
input clk_i;
379
input nmi_i;
380
input irq_i;
381
 
382
output [1:0] bte_o;
383
reg [1:0] bte_o;
384
output [2:0] cti_o;
385
reg [2:0] cti_o;
386
output cyc_o;
387
reg cyc_o;
388
output stb_o;
389
reg stb_o;
390
input ack_i;
391
output we_o;
392
reg we_o;
393
output [3:0] sel_o;
394
reg [3:0] sel_o;
395
output rsv_o;
396
reg rsv_o;
397
output [31:0] adr_o;
398
reg [31:0] adr_o;
399
input [31:0] dat_i;
400
output [31:0] dat_o;
401
reg [31:0] dat_o;
402
 
403
input sys_adv;
404
input [63:5] sys_adr;
405
 
406
output cmd_en;
407
reg cmd_en;
408
output [2:0] cmd_instr;
409
reg [2:0] cmd_instr;
410
output [5:0] cmd_bl;
411
reg [5:0] cmd_bl;
412
output [29:0] cmd_byte_addr;
413
reg [29:0] cmd_byte_addr;
414
input cmd_full;
415
output wr_en;
416
reg wr_en;
417
output [31:0] wr_data;
418
reg [31:0] wr_data;
419
output [3:0] wr_mask;
420
reg [3:0] wr_mask;
421
input wr_full;
422
input wr_empty;
423
output rd_en;
424
reg rd_en;
425
input [31:0] rd_data;
426
input rd_empty;
427
 
428
reg resetA;
429
reg im;                         // interrupt mask
430
reg [1:0] rm;            // fp rounding mode
431
reg [41:0] dIR;
432
reg [41:0] xIR;
433
reg [4:0] epcnt;
434
reg [3:0] dAXC,AXC,xAXC,m1AXC,m2AXC,m3AXC,m4AXC,wAXC;
435
reg [31:0] EP [3:0];
436
reg [63:0] pc [15:0];
437
reg [63:0] ErrorEPC,EPC[15:0],IPC[15:0];
438
wire [63:0] pc_axc = pc[AXC];
439
reg [63:0] dpc,m1pc,m2pc,m3pc,m4pc,wpc;
440
reg [63:0] xpc;
441
reg [63:0] tlbra;                // return address for a TLB exception
442
reg [8:0] dRa,dRb,dRc;
443
reg [8:0] wRt,mRt,m1Rt,m2Rt,m3Rt,m4Rt,tRt,dRt;
444
reg [8:0] xRt;
445
reg [63:0] dImm;
446
reg [63:0] ea;
447
reg [63:0] iadr_o;
448
reg [31:0] idat;
449
reg [4:0] cstate;
450
reg dbranch_taken,xbranch_taken;
451
reg [63:0] mutex_gate;
452
reg [63:0] TBA;
453
 
454
//reg wr_icache;
455
reg dccyc;
456
wire [63:0] cdat;
457
reg [63:0] wr_addr;
458
wire [41:0] insn;
459
reg [3:0] regset;
460
wire [63:0] rfoa,rfob;
461
reg clk_en;
462
reg cpu_clk_en;
463
reg [15:0] StatusERL;            // 1= in error processing
464
reg [15:0] StatusEXL;            // 1= in exception processing
465
reg [15:0] StatusHWI;
466
reg [7:0] CauseCode[15:0];
467
reg [7:0] ASID;          // address space identifier (process ID)
468
integer n;
469
reg [63:13] BadVAddr [15:0];
470
reg [63:13] PageTableAddr;
471
 
472
function [63:0] fnIncPC;
473
input [63:0] fpc;
474
begin
475
case(fpc[3:2])
476
2'd0:   fnIncPC = {fpc[63:4],4'b0100};
477
2'd1:   fnIncPC = {fpc[63:4],4'b1000};
478
2'd2:   fnIncPC = {fpc[63:4]+60'd1,4'b0000};
479
2'd3:   fnIncPC = {fpc[63:4]+60'd1,4'b0000};
480
endcase
481
end
482
endfunction
483
 
484
wire xKernelMode = StatusEXL[xAXC];
485
 
486
//-----------------------------------------------------------------------------
487
// TLB stuff
488
//-----------------------------------------------------------------------------
489
 
490
reg [24:13] TLBPageMask;
491
reg [63:13] TLBVirtPage;
492
reg [63:13] TLBPhysPage0;
493
reg [63:13] TLBPhysPage1;
494
reg [7:0] TLBASID;
495
reg TLBG,TLBD,TLBValid;
496
reg [3:0] Index;
497
reg [3:0] Random;
498
reg [3:0] Wired;
499
 
500
reg [15:0] IMatch,DMatch;
501
reg [4:0] m,q;
502
reg [3:0] i;
503
reg [31:13] tTLBPageMask [15:0];
504
reg [63:13] tTLBVirtPage [15:0];
505
reg [63:13] tTLBPhysPage0 [15:0];
506
reg [63:13] tTLBPhysPage1 [15:0];
507
reg [15:0] tTLBG;
508
reg [15:0] tTLBD;
509
reg [7:0] tTLBASID [15:0];
510
reg [15:0] tTLBValid;
511
initial begin
512
        for (n = 0; n < 16; n = n + 1)
513
        begin
514
                tTLBPageMask[n] = 0;
515
                tTLBVirtPage[n] = 0;
516
                tTLBPhysPage0[n] = 0;
517
                tTLBPhysPage1[n] = 0;
518
                tTLBG[n] = 0;
519
                tTLBD[n] = 0;
520
                tTLBASID[n] = 0;
521
                tTLBValid[n] = 0;
522
        end
523
end
524
always @*
525
for (n = 0; n < 16; n = n + 1)
526
begin
527
        IMatch[n] = ((pc_axc[63:13]|tTLBPageMask[n])==(tTLBVirtPage[n]|tTLBPageMask[n])) &&
528
                                ((tTLBASID[n]==ASID) || tTLBG[n]) &&
529
                                tTLBValid[n];
530
        DMatch[n] = ((ea[63:13]|tTLBPageMask[n])==(tTLBVirtPage[n]|tTLBPageMask[n])) &&
531
                                ((tTLBASID[n]==ASID) || tTLBG[n]) &&
532
                                tTLBValid[n];
533
end
534
always @(IMatch)
535
if (IMatch[0]) m <= 5'd0;
536
else if (IMatch[1]) m <= 5'd1;
537
else if (IMatch[2]) m <= 5'd2;
538
else if (IMatch[3]) m <= 5'd3;
539
else if (IMatch[4]) m <= 5'd4;
540
else if (IMatch[5]) m <= 5'd5;
541
else if (IMatch[6]) m <= 5'd6;
542
else if (IMatch[7]) m <= 5'd7;
543
else if (IMatch[8]) m <= 5'd8;
544
else if (IMatch[9]) m <= 5'd9;
545
else if (IMatch[10]) m <= 5'd10;
546
else if (IMatch[11]) m <= 5'd11;
547
else if (IMatch[12]) m <= 5'd12;
548
else if (IMatch[13]) m <= 5'd13;
549
else if (IMatch[14]) m <= 5'd14;
550
else if (IMatch[15]) m <= 5'd15;
551
else m <= 5'd31;
552
 
553
wire ioddpage = |({tTLBPageMask[m]+19'd1,13'd0}&pc_axc);
554
wire [63:13] IPFN = ioddpage ? tTLBPhysPage1[m] : tTLBPhysPage0[m];
555
 
556
wire unmappedArea = pc_axc[63:52]==12'hFFD || pc_axc[63:52]==12'hFFE || pc_axc[63:52]==12'hFFF;
557
wire [63:0] ppc;
558
wire ITLBMiss = !unmappedArea & m[4];
559
 
560
assign ppc[63:13] = unmappedArea ? pc_axc[63:13] : m[4] ? `TLBMissPage: IPFN;
561
assign ppc[12:0] = pc_axc[12:0];
562
 
563
always @(DMatch)
564
if (DMatch[0]) q <= 5'd0;
565
else if (DMatch[1]) q <= 5'd1;
566
else if (DMatch[2]) q <= 5'd2;
567
else if (DMatch[3]) q <= 5'd3;
568
else if (DMatch[4]) q <= 5'd4;
569
else if (DMatch[5]) q <= 5'd5;
570
else if (DMatch[6]) q <= 5'd6;
571
else if (DMatch[7]) q <= 5'd7;
572
else if (DMatch[8]) q <= 5'd8;
573
else if (DMatch[9]) q <= 5'd9;
574
else if (DMatch[10]) q <= 5'd10;
575
else if (DMatch[11]) q <= 5'd11;
576
else if (DMatch[12]) q <= 5'd12;
577
else if (DMatch[13]) q <= 5'd13;
578
else if (DMatch[14]) q <= 5'd14;
579
else if (DMatch[15]) q <= 5'd15;
580
else q <= 5'd31;
581
 
582
wire doddpage = |({tTLBPageMask[q]+19'd1,13'd0}&ea);
583
wire [63:13] DPFN = doddpage ? tTLBPhysPage1[q] : tTLBPhysPage0[q];
584
 
585
reg m1UnmappedDataArea;
586
wire unmappedDataArea = ea[63:52]==12'hFFD || ea[63:52]==12'hFFE || ea[63:52]==12'hFFF;
587
wire DTLBMiss = !unmappedDataArea & q[4];
588
 
589
wire [63:0] pea;
590
assign pea[63:13] = unmappedDataArea ? ea[63:13] : q[4] ? `TLBMissPage: DPFN;
591
assign pea[12:0] = ea[12:0];
592
 
593
//-----------------------------------------------------------------------------
594
// Clock control
595
// - reset or NMI reenables the clock
596
// - this circuit must be under the clk_i domain
597
//-----------------------------------------------------------------------------
598
//
599
BUFGCE u20 (.CE(cpu_clk_en), .I(clk_i), .O(clk) );
600
 
601
always @(posedge clk_i)
602
if (rst_i) begin
603
        cpu_clk_en <= 1'b1;
604
end
605
else begin
606
        if (nmi_i)
607
                cpu_clk_en <= 1'b1;
608
        else
609
                cpu_clk_en <= clk_en;
610
end
611
 
612
//-----------------------------------------------------------------------------
613
// Instruction Cache
614
// 8kB
615
// 
616
//-----------------------------------------------------------------------------
617
reg icaccess, iciaccess;
618
wire wr_icache = (!rd_empty & icaccess) | (iciaccess & ack_i);
619
 
620
Raptor64_icache_ram_x32 u1
621
(
622
        .clk(clk),
623
        .wr(wr_icache),
624
        .adr_i(iadr_o[12:0]),
625
        .dat_i(icaccess ?rd_data : dat_i),
626
        .pc(pc_axc),
627
        .insn(insn)
628
);
629
 
630
reg [63:13] tmem [127:0];
631
reg [127:0] tvalid;
632
 
633
initial begin
634
        for (n=0; n < 128; n = n + 1)
635
                tmem[n] = 0;
636
        for (n=0; n < 128; n = n + 1)
637
                tvalid[n] = 0;
638
end
639
 
640
wire [64:13] tgout;
641
assign tgout = {tvalid[pc_axc[12:6]],tmem[pc_axc[12:6]]};
642
assign ihit = (tgout=={1'b1,ppc[63:13]});
643
 
644
 
645
//-----------------------------------------------------------------------------
646
// Data Cache
647
// No-allocate on write
648
//-----------------------------------------------------------------------------
649
reg dcaccess;
650
wire dhit;
651
wire [13:0] dtign;
652
wire [64:14] dtgout;
653
reg wrhit;
654
reg [7:0] dsel_o;
655
reg [63:0] dadr_o;
656
reg [31:0] ddat;
657
reg wr_dcache;
658
 
659
// cache RAM 16Kb
660
Raptor64mc_dcache_ram u10
661
(
662
        .clka(~clk),
663
        .wea(8'h00),
664
        .addra(pea[13:3]),
665
        .dina(64'h0000),
666
        .douta(cdat),
667
 
668
        .clkb(clk),
669
        .web(dcaccess ? {4{wr_dcache}} : wrhit & wr_en ? ~wr_mask : 4'b0000),
670
        .addrb(dcaccess ? dadr_o[13:2] : wr_addr[13:2]),
671
        .dinb(dcaccess ? ddat : wr_data),
672
        .doutb()
673
);
674
 
675
// tag ram
676
syncRam512x64_1rw1r u11
677
(
678
        .wrst(1'b0),
679
        .wclk(clk),
680
        .wce(dadr_o[4:2]==3'b111),
681
        .we(wr_dcache),
682
        .wadr(dadr_o[13:5]),
683
        .i({14'h3FFF,dadr_o[63:14]}),
684
        .wo(),
685
 
686
        .rrst(1'b0),
687
        .rclk(~clk),
688
        .rce(1'b1),
689
        .radr(pea[13:5]),
690
        .ro({dtign,dtgout})
691
);
692
 
693
assign dhit = (dtgout=={1'b1,pea[63:14]});
694
 
695
//-----------------------------------------------------------------------------
696
//-----------------------------------------------------------------------------
697
 
698
reg [64:0] xData;
699
wire xisCacheElement = xData[63:52] != 12'hFFD;
700
reg m1IsCacheElement;
701
 
702
reg nopI;
703
wire [6:0] iFunc = insn[6:0];
704
wire [6:0] dFunc = dIR[6:0];
705
wire [6:0] xFunc = xIR[6:0];
706
wire [6:0] iOpcode = insn[41:35];
707
wire [6:0] xOpcode = xIR[41:35];
708
wire [6:0] dOpcode = dIR[41:35];
709
reg [6:0] m1Opcode,m2Opcode,m3Opcode,m4Opcode;
710
reg [6:0] m1Func,m2Func,m3Func,m4Func;
711
reg [63:0] m1Data,m2Data,m3Data,m4Data,wData,tData;
712
reg [63:0] m2Addr,m3Addr,m4Addr;
713
reg [63:0] tick;
714
reg [63:0] tba;
715
reg [63:0] exception_address,ipc;
716
reg [63:0] a,b,c,imm,m1b;
717
reg prev_ihit;
718
reg rsf;
719
reg [63:5] resv_address;
720
reg [15:0] dirqf;
721
reg rirqf,m1irqf,m2irqf,m3irqf,m4irqf,wirqf,tirqf;
722
reg xirqf;
723
reg [7:0] dextype,m1extype,m2extype,m3extype,m4extype,wextype,textype,exception_type;
724
reg [7:0] xextype;
725
wire advanceX_edge;
726
reg takb;
727
 
728
wire [127:0] mult_out;
729
wire [63:0] sqrt_out;
730
wire [63:0] div_q;
731
wire [63:0] div_r;
732
wire sqrt_done,mult_done,div_done;
733
wire isSqrt = xOpcode==`R && xFunc==`SQRT;
734
wire [7:0] bcdaddo,bcdsubo;
735
 
736
BCDAdd u40(.ci(1'b0),.a(a[7:0]),.b(b[7:0]),.o(bcdaddo),.c());
737
BCDSub u41(.ci(1'b0),.a(a[7:0]),.b(b[7:0]),.o(bcdsubo),.c());
738
 
739
isqrt #(64) u14
740
(
741
        .rst(rst_i),
742
        .clk(clk),
743
        .ce(1'b1),
744
        .ld(isSqrt),
745
        .a(a),
746
        .o(sqrt_out),
747
        .done(sqrt_done)
748
);
749
 
750
wire isMulu = xOpcode==`RR && xFunc==`MULU;
751
wire isMuls = (xOpcode==`RR && xFunc==`MULS) || xOpcode==`MULSI;
752
wire isMuli = xOpcode==`MULSI || xOpcode==`MULUI;
753
wire isMult = xOpcode==`MULSI || xOpcode==`MULUI || (xOpcode==`RR && (xFunc==`MULS || xFunc==`MULU));
754
wire isDivu = xOpcode==`RR && xFunc==`DIVU;
755
wire isDivs = (xOpcode==`RR && xFunc==`DIVS) || xOpcode==`DIVSI;
756
wire isDivi = xOpcode==`DIVSI || xOpcode==`DIVUI;
757
wire isDiv = xOpcode==`DIVSI || xOpcode==`DIVUI || (xOpcode==`RR && (xFunc==`DIVS || xFunc==`DIVU));
758
 
759
wire disRRShift = dOpcode==`RR && (
760
        dFunc==`SHL || dFunc==`ROL || dFunc==`SHR ||
761
        dFunc==`SHRU || dFunc==`ROR || dFunc==`ROLAM
762
        );
763
wire disRightShift = dOpcode==`RR && (
764
        dFunc==`SHR || dFunc==`SHRU || dFunc==`ROR
765
        );
766
 
767
Raptor64Mult u18
768
(
769
        .rst(rst_i),
770
        .clk(clk),
771
        .ld(isMult),
772
        .sgn(isMuls),
773
        .isMuli(isMuli),
774
        .a(a),
775
        .b(b),
776
        .imm(imm),
777
        .o(mult_out),
778
        .done(mult_done)
779
);
780
 
781
Raptor64Div u19
782
(
783
        .rst(rst_i),
784
        .clk(clk),
785
        .ld(isDiv),
786
        .sgn(isDivs),
787
        .isDivi(isDivi),
788
        .a(a),
789
        .b(b),
790
        .imm(imm),
791
        .qo(div_q),
792
        .ro(div_r),
793
        .dvByZr(),
794
        .done(div_done)
795
);
796
 
797
wire [63:0] fpZLOut;
798
wire [63:0] fpLooOut;
799
wire fpLooDone;
800
 
801
fpZLUnit #(64) u30
802
(
803
        .op(xFunc[5:0]),
804
        .a(a),
805
        .b(b),  // for fcmp
806
        .o(fpZLOut),
807
        .nanx()
808
);
809
 
810
fpLOOUnit #(64) u31
811
(
812
        .clk(clk),
813
        .ce(1'b1),
814
        .rm(rm),
815
        .op(xFunc[5:0]),
816
        .a(a),
817
        .o(fpLooOut),
818
        .done(fpLooDone)
819
);
820
 
821
function [2:0] popcnt6;
822
input [5:0] a;
823
begin
824
case(a)
825
6'b000000:      popcnt6 = 3'd0;
826
6'b000001:      popcnt6 = 3'd1;
827
6'b000010:      popcnt6 = 3'd1;
828
6'b000011:      popcnt6 = 3'd2;
829
6'b000100:      popcnt6 = 3'd1;
830
6'b000101:      popcnt6 = 3'd2;
831
6'b000110:      popcnt6 = 3'd2;
832
6'b000111:      popcnt6 = 3'd3;
833
6'b001000:      popcnt6 = 3'd1;
834
6'b001001:      popcnt6 = 3'd2;
835
6'b001010:      popcnt6 = 3'd2;
836
6'b001011:      popcnt6 = 3'd3;
837
6'b001100:      popcnt6 = 3'd2;
838
6'b001101:      popcnt6 = 3'd3;
839
6'b001110:      popcnt6 = 3'd3;
840
6'b001111:  popcnt6 = 3'd4;
841
6'b010000:      popcnt6 = 3'd1;
842
6'b010001:      popcnt6 = 3'd2;
843
6'b010010:  popcnt6 = 3'd2;
844
6'b010011:      popcnt6 = 3'd3;
845
6'b010100:  popcnt6 = 3'd2;
846
6'b010101:  popcnt6 = 3'd3;
847
6'b010110:  popcnt6 = 3'd3;
848
6'b010111:      popcnt6 = 3'd4;
849
6'b011000:      popcnt6 = 3'd2;
850
6'b011001:      popcnt6 = 3'd3;
851
6'b011010:      popcnt6 = 3'd3;
852
6'b011011:      popcnt6 = 3'd4;
853
6'b011100:      popcnt6 = 3'd3;
854
6'b011101:      popcnt6 = 3'd4;
855
6'b011110:      popcnt6 = 3'd4;
856
6'b011111:      popcnt6 = 3'd5;
857
6'b100000:      popcnt6 = 3'd1;
858
6'b100001:      popcnt6 = 3'd2;
859
6'b100010:      popcnt6 = 3'd2;
860
6'b100011:      popcnt6 = 3'd3;
861
6'b100100:      popcnt6 = 3'd2;
862
6'b100101:      popcnt6 = 3'd3;
863
6'b100110:      popcnt6 = 3'd3;
864
6'b100111:      popcnt6 = 3'd4;
865
6'b101000:      popcnt6 = 3'd2;
866
6'b101001:      popcnt6 = 3'd3;
867
6'b101010:      popcnt6 = 3'd3;
868
6'b101011:      popcnt6 = 3'd4;
869
6'b101100:      popcnt6 = 3'd3;
870
6'b101101:      popcnt6 = 3'd4;
871
6'b101110:      popcnt6 = 3'd4;
872
6'b101111:      popcnt6 = 3'd5;
873
6'b110000:      popcnt6 = 3'd2;
874
6'b110001:      popcnt6 = 3'd3;
875
6'b110010:      popcnt6 = 3'd3;
876
6'b110011:      popcnt6 = 3'd4;
877
6'b110100:      popcnt6 = 3'd3;
878
6'b110101:      popcnt6 = 3'd4;
879
6'b110110:      popcnt6 = 3'd4;
880
6'b110111:      popcnt6 = 3'd5;
881
6'b111000:      popcnt6 = 3'd3;
882
6'b111001:      popcnt6 = 3'd4;
883
6'b111010:      popcnt6 = 3'd4;
884
6'b111011:      popcnt6 = 3'd5;
885
6'b111100:      popcnt6 = 3'd4;
886
6'b111101:      popcnt6 = 3'd5;
887
6'b111110:      popcnt6 = 3'd5;
888
6'b111111:      popcnt6 = 3'd6;
889
endcase
890
end
891
endfunction
892
 
893
wire [63:0] jmp_tgt = dOpcode[6:4]==`IMM ? {dIR[26:0],insn[34:0],2'b00} : {pc_axc[63:37],insn[34:0],2'b00};
894
 
895
//-----------------------------------------------------------------------------
896
// Branch history table.
897
// The history table is updated by the EX stage and read in
898
// both the EX and IF stages.
899
// A separate global branch history is kept for each context.
900
//-----------------------------------------------------------------------------
901
reg [2:0] gbl_branch_hist [15:0];
902
reg [1:0] branch_history_table [511:0];
903
wire [7:0] bht_wa = {xpc[6:0],gbl_branch_hist[xAXC][2:1]};                // write address
904
wire [7:0] bht_ra1 = {xpc[6:0],gbl_branch_hist[xAXC][2:1]};               // read address (EX stage)
905
wire [7:0] bht_ra2 = {pc_axc[6:0],gbl_branch_hist[AXC][2:1]};     // read address (IF stage)
906
wire [1:0] bht_xbits = branch_history_table[bht_ra1];
907
wire [1:0] bht_ibits = branch_history_table[bht_ra2];
908
wire predict_taken = bht_ibits==2'd0 || bht_ibits==2'd1;
909
 
910
wire isxBranchI = (xOpcode==`BRAI || xOpcode==`BRNI || xOpcode==`BEQI || xOpcode==`BNEI ||
911
                                        xOpcode==`BLTI || xOpcode==`BLEI || xOpcode==`BGTI || xOpcode==`BGEI ||
912
                                        xOpcode==`BLTUI || xOpcode==`BLEUI || xOpcode==`BGTUI || xOpcode==`BGEUI)
913
                                ;
914
wire isxBranch = isxBranchI || xOpcode==`TRAPcc || xOpcode==`TRAPcci || xOpcode==`BTRI || xOpcode==`BTRR;
915
 
916
reg [1:0] xbits_new;
917
 
918
always @(takb or bht_xbits)
919
if (takb) begin
920
        if (bht_xbits != 2'd1)
921
                xbits_new <= bht_xbits + 2'd1;
922
        else
923
                xbits_new <= bht_xbits;
924
end
925
else begin
926
        if (bht_xbits != 2'd2)
927
                xbits_new <= bht_xbits - 2'd1;
928
        else
929
                xbits_new <= bht_xbits;
930
end
931
 
932
// For simulation only, initialize the history table to zeros.
933
// In the real world we don't care.
934
initial begin
935
        for (n = 0; n < 256; n = n + 1)
936
                branch_history_table[n] = 0;
937
end
938
 
939
//-----------------------------------------------------------------------------
940
// Evaluate branch conditions.
941
//-----------------------------------------------------------------------------
942
wire signed [63:0] as = a;
943
wire signed [63:0] bs = b;
944
wire signed [63:0] imms = imm;
945
wire aeqz = a==64'd0;
946
wire beqz = b==64'd0;
947
wire immeqz = imm==64'd0;
948
wire eq = a==b;
949
wire eqi = a==imm;
950
wire lt = as < bs;
951
wire lti = as < imms;
952
wire ltu = a < b;
953
wire ltui = a < imm;
954
 
955
always @(xOpcode or xFunc or a or eq or eqi or lt or lti or ltu or ltui or aeqz or beqz or rsf or xIR)
956
case (xOpcode)
957
`BTRR:
958
        case(xFunc)
959
        `BRA:   takb = 1'b1;
960
        `BRN:   takb = 1'b0;
961
        `BEQ:   takb = eq;
962
        `BNE:   takb = !eq;
963
        `BLT:   takb = lt;
964
        `BLE:   takb = lt|eq;
965
        `BGT:   takb = !(lt|eq);
966
        `BGE:   takb = !lt;
967
        `BLTU:  takb = ltu;
968
        `BLEU:  takb = ltu|eq;
969
        `BGTU:  takb = !(ltu|eq);
970
        `BGEU:  takb = !ltu;
971
        `BOR:   takb = !aeqz || !beqz;
972
        `BAND:  takb = !aeqz && !beqz;
973
        `BNR:   takb = !rsf;
974
        `BEQR:  takb = eq;
975
        `BNER:  takb = !eq;
976
        `BLTR:  takb = lt;
977
        `BLER:  takb = lt|eq;
978
        `BGTR:  takb = !(lt|eq);
979
        `BGER:  takb = !lt;
980
        `BLTUR: takb = ltu;
981
        `BLEUR: takb = ltu|eq;
982
        `BGTUR: takb = !(ltu|eq);
983
        `BGEUR: takb = !ltu;
984
        default:        takb = 1'b0;
985
        endcase
986
`BRAI:  takb = 1'b1;
987
`BRNI:  takb = 1'b0;
988
`BEQI:  takb = eqi;
989
`BNEI:  takb = !eqi;
990
`BLTI:  takb = lti;
991
`BLEI:  takb = lti|eqi;
992
`BGTI:  takb = !(lti|eqi);
993
`BGEI:  takb = !lti;
994
`BLTUI: takb = ltui;
995
`BLEUI: takb = ltui|eqi;
996
`BGTUI: takb = !(ltui|eqi);
997
`BGEUI: takb = !ltui;
998
`BTRI:
999
        case(xIR[24:18])
1000
        `BRA:   takb = 1'b1;
1001
        `BRN:   takb = 1'b0;
1002
        `BEQ:   takb = eqi;
1003
        `BNE:   takb = !eqi;
1004
        `BLT:   takb = lti;
1005
        `BLE:   takb = lti|eqi;
1006
        `BGT:   takb = !(lti|eqi);
1007
        `BGE:   takb = !lti;
1008
        `BLTU:  takb = ltui;
1009
        `BLEU:  takb = ltui|eqi;
1010
        `BGTU:  takb = !(ltui|eqi);
1011
        `BGEU:  takb = !ltui;
1012
        default:        takb = 1'b0;
1013
        endcase
1014
`TRAPcc:
1015
        case(xFunc)
1016
        `TEQ:   takb = eq;
1017
        `TNE:   takb = !eq;
1018
        `TLT:   takb = lt;
1019
        `TLE:   takb = lt|eq;
1020
        `TGT:   takb = !(lt|eq);
1021
        `TGE:   takb = !lt;
1022
        `TLO:   takb = ltu;
1023
        `TLS:   takb = ltu|eq;
1024
        `THI:   takb = !(ltu|eq);
1025
        `THS:   takb = !ltu;
1026
        default:        takb = 1'b0;
1027
        endcase
1028
`TRAPcci:
1029
        case(xIR[29:25])
1030
        `TEQI:  takb = eqi;
1031
        `TNEI:  takb = !eqi;
1032
        `TLTI:  takb = lti;
1033
        `TLEI:  takb = lti|eqi;
1034
        `TGTI:  takb = !(lti|eqi);
1035
        `TGEI:  takb = !lti;
1036
        `TLOI:  takb = ltui;
1037
        `TLSI:  takb = ltui|eqi;
1038
        `THII:  takb = !(ltui|eqi);
1039
        `THSI:  takb = !ltui;
1040
        default:        takb = 1'b0;
1041
        endcase
1042
default:
1043
        takb = 1'b0;
1044
endcase
1045
 
1046
 
1047
//-----------------------------------------------------------------------------
1048
// Datapath (ALU) operations.
1049
//-----------------------------------------------------------------------------
1050
wire [6:0] cntlzo,cntloo;
1051
cntlz64 u12 ( .i(a),  .o(cntlzo) );
1052
cntlo64 u13 ( .i(a),  .o(cntloo) );
1053
 
1054
reg [1:0] shftop;
1055
wire [63:0] shfto;
1056
always @(xFunc)
1057
        if (xFunc==`SHL)
1058
                shftop = 2'b00;
1059
        else if (xFunc==`ROL || xFunc==`ROR)
1060
                shftop = 2'b01;
1061
        else if (xFunc==`SHRU)
1062
                shftop = 2'b10;
1063
        else if (xFunc==`SHR)
1064
                shftop = 2'b11;
1065
        else
1066
                shftop = 2'b01;
1067
 
1068
wire [63:0] masko;
1069
shiftAndMask u15
1070
(
1071
        .op(shftop),
1072
        .oz(1'b0),              // zero the output
1073
        .a(a),
1074
        .b(b[5:0]),
1075
        .mb(xIR[12:7]),
1076
        .me(xIR[18:13]),
1077
        .o(shfto),
1078
        .mo(masko)
1079
);
1080
 
1081
always @(xOpcode or xFunc or a or b or imm or as or bs or imms or xpc or
1082
        sqrt_out or cntlzo or cntloo or tick or ipc or tba or regset or
1083
        lt or eq or ltu or mult_out or lti or eqi or ltui or xIR or div_q or div_r or
1084
        shfto or masko or bcdaddo or bcdsubo or fpLooOut or fpZLOut or
1085
        Wired or Index or Random or TLBPhysPage0 or TLBPhysPage1 or TLBVirtPage or TLBASID or
1086
        PageTableAddr or BadVAddr or ASID or TLBPageMask
1087
)
1088
case(xOpcode)
1089
`R:
1090
        casex(xFunc)
1091
        `SETLO: xData = imm;
1092
        `SETHI: xData = {imm[63:32],a[31:0]};
1093
        `COM:   xData = ~a;
1094
        `NOT:   xData = ~|a;
1095
        `NEG:   xData = -a;
1096
        `ABS:   xData = a[63] ? -a : a;
1097
        `SQRT:  xData = sqrt_out;
1098
        `SWAP:  xData = {a[31:0],a[63:32]};
1099
 
1100
        `REDOR:         xData = |a;
1101
        `REDAND:        xData = &a;
1102
 
1103
        `CTLZ:  xData = cntlzo;
1104
        `CTLO:  xData = cntloo;
1105
        `CTPOP: xData = {4'd0,popcnt6(a[5:0])} +
1106
                                        {4'd0,popcnt6(a[11:6])} +
1107
                                        {4'd0,popcnt6(a[17:12])} +
1108
                                        {4'd0,popcnt6(a[23:18])} +
1109
                                        {4'd0,popcnt6(a[29:24])} +
1110
                                        {4'd0,popcnt6(a[35:30])} +
1111
                                        {4'd0,popcnt6(a[41:36])} +
1112
                                        {4'd0,popcnt6(a[47:42])} +
1113
                                        {4'd0,popcnt6(a[53:48])} +
1114
                                        {4'd0,popcnt6(a[59:54])} +
1115
                                        {4'd0,popcnt6(a[63:60])}
1116
                                        ;
1117
        `SEXT8:         xData = {{56{a[7]}},a[7:0]};
1118
        `SEXT16:        xData = {{48{a[15]}},a[15:0]};
1119
        `SEXT32:        xData = {{32{a[31]}},a[31:0]};
1120
 
1121
        `MFSPR:
1122
                case(xIR[12:7])
1123
                `Wired:                 xData = Wired;
1124
                `TLBIndex:              xData = Index;
1125
                `TLBRandom:             xData = Random;
1126
                `TLBPhysPage0:  xData = {TLBPhysPage0,13'd0};
1127
                `TLBPhysPage1:  xData = {TLBPhysPage1,13'd0};
1128
                `TLBVirtPage:   xData = {TLBVirtPage,13'd0};
1129
                `TLBPageMask:   xData = {TLBPageMask,13'd0};
1130
                `TLBASID:               begin
1131
                                                xData[0] = TLBValid;
1132
                                                xData[1] = TLBD;
1133
                                                xData[2] = TLBG;
1134
                                                xData[15:8] = TLBASID;
1135
                                                end
1136
                `PageTableAddr: xData = {PageTableAddr,13'd0};
1137
                `BadVAddr:              xData = {BadVAddr[xAXC],13'd0};
1138
                `ASID:                  xData = ASID;
1139
                `EP0:                   xData = EP[0];
1140
                `EP1:                   xData = EP[1];
1141
                `EP2:                   xData = EP[2];
1142
                `EP3:                   xData = EP[3];
1143
                `AXC:                   xData = xAXC;
1144
                `Tick:                  xData = tick;
1145
                `EPC:                   xData = EPC[xAXC];
1146
                `CauseCode:             xData = CauseCode[xAXC];
1147
                `TBA:                   xData = TBA;
1148
                default:        xData = 65'd0;
1149
                endcase
1150
        `OMG:           xData = mutex_gate[a[5:0]];
1151
        `CMG:           xData = mutex_gate[a[5:0]];
1152
        `OMGI:          xData = mutex_gate[xIR[12:7]];
1153
        `CMGI:          xData = mutex_gate[xIR[12:7]];
1154
        default:        xData = 65'd0;
1155
        endcase
1156
`RR:
1157
        case(xFunc)
1158
        `ADD:   xData = a + b;
1159
        `ADDU:  xData = a + b;
1160
        `SUB:   xData = a - b;
1161
        `SUBU:  xData = a - b;
1162
        `CMP:   xData = lt ? 64'hFFFFFFFFFFFFF : eq ? 64'd0 : 64'd1;
1163
        `CMPU:  xData = ltu ? 64'hFFFFFFFFFFFFF : eq ? 64'd0 : 64'd1;
1164
        `SEQ:   xData = eq;
1165
        `SNE:   xData = !eq;
1166
        `SLT:   xData = lt;
1167
        `SLE:   xData = lt|eq;
1168
        `SGT:   xData = !(lt|eq);
1169
        `SGE:   xData = !lt;
1170
        `SLTU:  xData = ltu;
1171
        `SLEU:  xData = ltu|eq;
1172
        `SGTU:  xData = !(ltu|eq);
1173
        `SGEU:  xData = !ltu;
1174
        `AND:   xData = a & b;
1175
        `OR:    xData = a | b;
1176
        `XOR:   xData = a ^ b;
1177
        `ANDC:  xData = a & ~b;
1178
        `NAND:  xData = ~(a & b);
1179
        `NOR:   xData = ~(a | b);
1180
        `XNOR:  xData = ~(a ^ b);
1181
        `ORC:   xData = a | ~b;
1182
        `MIN:   xData = lt ? a : b;
1183
        `MAX:   xData = lt ? b : a;
1184
        `MOVZ:  xData = b;
1185
        `MOVNZ: xData = b;
1186
        `MULS:  xData = mult_out[63:0];
1187
        `MULU:  xData = mult_out[63:0];
1188
        `DIVS:  xData = div_q;
1189
        `DIVU:  xData = div_q;
1190
        `MOD:   xData = div_r;
1191
 
1192
        `SHL:   xData = shfto;
1193
        `SHRU:  xData = shfto;
1194
        `ROL:   xData = shfto;
1195
        `ROR:   xData = {a[0],a[63:1]};
1196
        `SHR:   xData = shfto;
1197
        `ROLAM: xData = shfto & masko;
1198
 
1199
        `BCD_ADD:       xData = bcdaddo;
1200
        `BCD_SUB:       xData = bcdsubo;
1201
 
1202
        default:        xData = 65'd0;
1203
        endcase
1204
`SHFTI:
1205
        case(xFunc)
1206
        `SHLI:  xData = shfto;
1207
        `SHRUI: xData = shfto;
1208
        `ROLI:  xData = shfto;
1209
        `RORI:  xData = {a[0],a[63:1]};
1210
        `SHRI:  xData = shfto;
1211
        `ROLAMI:        xData = shfto & masko;
1212
        `BFINS:         begin for (n = 0; n < 64; n = n + 1) xData[n] = masko[n] ? shfto[n] : b[n]; xData[64] = 1'b0; end
1213
        `BFSET:         begin for (n = 0; n < 64; n = n + 1) xData[n] = masko[n] ? 1'b1 : b[n]; xData[64] = 1'b0; end
1214
        `BFCLR:         begin for (n = 0; n < 64; n = n + 1) xData[n] = masko[n] ? 1'b0 : b[n]; xData[64] = 1'b0; end
1215
        `BFCHG:         begin for (n = 0; n < 64; n = n + 1) xData[n] = masko[n] ? ~b[n] : b[n]; xData[64] = 1'b0; end
1216
        default:        xData = 65'd0;
1217
        endcase
1218
`SETLO: xData = imm;
1219
`SETHI: xData = {imm[63:32],a[31:0]};
1220
`ADDI:  xData = a + imm;
1221
`ADDUI: xData = a + imm;
1222
`SUBI:  xData = a - imm;
1223
`CMPI:  xData = lti ? 64'hFFFFFFFFFFFFF : eqi ? 64'd0 : 64'd1;
1224
`CMPUI: xData = ltui ? 64'hFFFFFFFFFFFFF : eqi ? 64'd0 : 64'd1;
1225
`MULSI: xData = mult_out[63:0];
1226
`MULUI: xData = mult_out[63:0];
1227
`DIVSI: xData = div_q;
1228
`DIVUI: xData = div_q;
1229
`ANDI:  xData = a & imm;
1230
`ORI:   xData = a | imm;
1231
`XORI:  xData = a ^ imm;
1232
`SEQI:  xData = eqi;
1233
`SNEI:  xData = !eqi;
1234
`SLTI:  xData = lti;
1235
`SLEI:  xData = lti|eqi;
1236
`SGTI:  xData = !(lti|eqi);
1237
`SGEI:  xData = !lti;
1238
`SLTUI: xData = ltui;
1239
`SLEUI: xData = ltui|eqi;
1240
`SGTUI: xData = !(ltui|eqi);
1241
`SGEUI: xData = !ltui;
1242
`INB,`INCH,`INH,`INW:
1243
                xData = a + imm;
1244
`OUTB,`OUTC,`OUTH,`OUTW:
1245
                xData = a + imm;
1246
`LW,`LH,`LC,`LB,`LHU,`LCU,`LBU,`LWR:
1247
                xData = a + imm;
1248
`SW,`SH,`SC,`SB,`SWC:
1249
                xData = a + imm;
1250
`MEMNDX:
1251
                xData = a + b + imm;
1252
`BEQ,`BNE,`BLT,`BLE,`BGT,`BGE,`BLTU,`BLEU,`BGTU,`BGEU,`BOR,`BAND:
1253
                xData = 64'd0;
1254
`TRAPcc:        xData = fnIncPC(xpc);
1255
`TRAPcci:       xData = fnIncPC(xpc);
1256
`CALL:          xData = fnIncPC(xpc);
1257
`JAL:           xData = xpc + {xIR[29:25],2'b00};
1258
`RET:   xData = a + {imm,2'b00};
1259
`FPLOO: xData = fpLooOut;
1260
`FPZL:  xData = fpZLOut;
1261
default:        xData = 65'd0;
1262
endcase
1263
 
1264
wire dbz_error = (xOpcode==`DIVSI||xOpcode==`DIVUI) && b==64'd0;
1265
wire ovr_error = (xOpcode==`ADDI || xOpcode==`SUBI) && (xData[64]!=xData[63]);
1266
wire priv_violation = !xKernelMode && (xOpcode==`MISC &&
1267
        (xFunc==`IRET || xFunc==`ERET || xFunc==`CLI || xFunc==`SEI ||
1268
         xFunc==`TLBP || xFunc==`TLBR || xFunc==`TLBWR || xFunc==`TLBWI
1269
        ));
1270
wire xIsSqrt = xOpcode==`R && xFunc==`SQRT;
1271
wire xIsMult = (xOpcode==`RR && (xFunc==`MULU || xFunc==`MULS)) ||
1272
        xOpcode==`MULSI || xOpcode==`MULUI;
1273
wire xIsDiv = (xOpcode==`RR && (xFunc==`DIVU || xFunc==`DIVS)) ||
1274
        xOpcode==`DIVSI || xOpcode==`DIVUI;
1275
 
1276
wire xIsLoad =
1277
        xOpcode==`LW || xOpcode==`LH || xOpcode==`LB || xOpcode==`LWR ||
1278
        xOpcode==`LHU || xOpcode==`LBU ||
1279
        xOpcode==`LC || xOpcode==`LCU ||
1280
        xOpcode==`INW || xOpcode==`INB || xOpcode==`INH || xOpcode==`INCH
1281
        ;
1282
wire xIsStore =
1283
        xOpcode==`SW || xOpcode==`SH || xOpcode==`SB || xOpcode==`SC || xOpcode==`SWC ||
1284
        xOpcode==`OUTW || xOpcode==`OUTH || xOpcode==`OUTB || xOpcode==`OUTC
1285
        ;
1286
wire xIsSWC = xOpcode==`SWC;
1287
wire xIsIn =
1288
        xOpcode==`INW || xOpcode==`INH || xOpcode==`INCH || xOpcode==`INB
1289
        ;
1290
//wire mIsSWC = mOpcode==`SWC;
1291
 
1292
//wire mIsLoad =
1293
//      mOpcode==`LW || mOpcode==`LH || mOpcode==`LB || mOpcode==`LC || mOpcode==`LWR ||
1294
//      mOpcode==`LHU || mOpcode==`LBU || mOpcode==`LCU ||
1295
//      mOpcode==`INW || mOpcode==`INB || mOpcode==`INH
1296
//      ;
1297
wire m1IsLoad =
1298
        m1Opcode==`LW || m1Opcode==`LH || m1Opcode==`LB || m1Opcode==`LC || m1Opcode==`LWR ||
1299
        m1Opcode==`LHU || m1Opcode==`LBU || m1Opcode==`LCU
1300
        ;
1301
wire m1IsIn =
1302
        m1Opcode==`INW || m1Opcode==`INH || m1Opcode==`INCH || m1Opcode==`INB
1303
        ;
1304
wire m1IsStore =
1305
        m1Opcode==`SW || m1Opcode==`SH || m1Opcode==`SB || m1Opcode==`SC || m1Opcode==`SWC
1306
        ;
1307
wire m1IsIO =
1308
        m1IsIn ||
1309
        m1Opcode==`OUTW || m1Opcode==`OUTH || m1Opcode==`OUTC || m1Opcode==`OUTB
1310
        ;
1311
wire m3IsIO =
1312
        m3Opcode==`INW || m3Opcode==`INH || m3Opcode==`INCH || m3Opcode==`INB ||
1313
        m3Opcode==`OUTW || m3Opcode==`OUTH || m3Opcode==`OUTC || m3Opcode==`OUTB
1314
        ;
1315
 
1316
wire m2IsLoad =
1317
        m2Opcode==`LW || m2Opcode==`LH || m2Opcode==`LB || m2Opcode==`LC || m2Opcode==`LWR ||
1318
        m2Opcode==`LHU || m2Opcode==`LBU || m2Opcode==`LCU
1319
        ;
1320
wire m3IsLoad =
1321
        m3Opcode==`LW || m3Opcode==`LH || m3Opcode==`LB || m3Opcode==`LC || m3Opcode==`LWR ||
1322
        m3Opcode==`LHU || m3Opcode==`LBU || m3Opcode==`LCU
1323
        ;
1324
wire m4IsLoad = m4Opcode==`LW || m4Opcode==`LWR
1325
        ;
1326
 
1327
wire xIsFPLoo = xOpcode==`FPLOO;
1328
 
1329
// Stall on SWC allows rsf flag to be loaded for the next instruction
1330
// Currently stalls on load of R0, but doesn't need to.
1331
wire xStall = ((xIsLoad||xIsIn) && ((xRt==dRa)||(xRt==dRb)||(xRt==dRt))) || xIsSWC;
1332
wire m1Stall = ((m1IsLoad||m1IsIn) && ((m1Rt==dRa)||(m1Rt==dRb)||(m1Rt==dRt)));// || mIsSWC;
1333
wire m2Stall = ((m2IsLoad) && ((m2Rt==dRa)||(m2Rt==dRb)||(m2Rt==dRt)));// || mIsSWC;
1334
wire m3Stall = ((m3IsLoad) && ((m3Rt==dRa)||(m3Rt==dRb)||(m3Rt==dRt)));// || mIsSWC;
1335
wire m4Stall = ((m4IsLoad) && ((m4Rt==dRa)||(m4Rt==dRb)||(m4Rt==dRt)));// || mIsSWC;
1336
wire eomc = dccyc ? dhit : cyc_o & !icaccess & !dcaccess ? ack_i : 1'b1;        // end of memory cycle
1337
 
1338
wire m1needWritePort = m1Opcode==`SW || m1Opcode==`SWC || m1Opcode==`SH || m1Opcode==`SC || m1Opcode==`SB;
1339
wire m2needWritePort = m2Opcode==`SW||m2Opcode==`SWC;
1340
wire m1needCmdPort = m1IsLoad && !m1IsCacheElement;
1341
wire m2needCmdPort = m2Opcode==`SH||m2Opcode==`SC||m2Opcode==`SB;
1342
wire m3needCmdPort = m3Opcode==`SW || m3Opcode==`SWC;
1343
wire m2needReadPort = m2IsLoad;
1344
wire m3needReadPort = m3Opcode==`LW || m3Opcode==`LWR;
1345
//wire m4needReadPort = m4Opcode==`LW || m4Opcode==`LWR;
1346
 
1347
// Stall for the write port
1348
wire StallM1 = (m1needWritePort && m2needWritePort) ||  // Write port collision
1349
// Stall on the command port
1350
        (m1needCmdPort && (m2needCmdPort||m3needCmdPort)) ||    // SW,SWC are still using the wr port in M2
1351
// cache access is taking place
1352
        icaccess || dcaccess
1353
        ;
1354
// M3 is using the command port
1355
wire StallM2 = (m2needCmdPort & m3needCmdPort) | (m3needReadPort|icaccess|dcaccess);
1356
wire StallM3 = m3needReadPort & (icaccess|dcaccess);
1357
wire advanceT = !resetA;
1358
wire advanceW = advanceT;
1359
wire advanceM4 = advanceW & (m4IsLoad ? !rd_empty : 1'b1);
1360
wire advanceM3 = advanceM4 &
1361
                                        (m3IsIO ? ack_i : 1'b1) &
1362
                                        (m3IsLoad ? !rd_empty : 1'b1) &
1363
                                        !StallM3
1364
                                        ;
1365
wire advanceM2 = advanceM3 & !StallM2;
1366
wire advanceM1 = advanceM2
1367
                                        &
1368
                                        (m1IsIO ? ack_i : 1'b1) &
1369
                                        ((m1IsLoad & !m1IsCacheElement) ? !cmd_full : 1'b1) &
1370
                                        ((m1IsLoad & m1IsCacheElement) ? dhit : 1'b1) &
1371
                                        (m1IsStore ? !wr_full : 1'b1) &
1372
                                        !StallM1
1373
                                        ;
1374
wire advanceX = advanceM1 & !cyc_o & (
1375
                                        xIsSqrt ? sqrt_done :
1376
                                        xIsMult ? mult_done :
1377
                                        xIsDiv ? div_done :
1378
                                        xIsFPLoo ? fpLooDone :
1379
                                        1'b1);
1380
wire advanceR = advanceX & !xStall & !m1Stall && !m2Stall && !m3Stall && !m4Stall;
1381
wire advanceI = advanceR & ihit;
1382
 
1383
wire triggerDCacheLoad = (m1IsLoad & m1IsCacheElement & !dhit) &&       // there is a miss
1384
                                                !(icaccess | dcaccess | iciaccess) &&   // caches are not active
1385
                                                m2Opcode==`NOPI &&                      // and the pipeline is free of memory-ops
1386
                                                m3Opcode==`NOPI &&
1387
                                                m4Opcode==`NOPI &&
1388
                                                wr_empty                                        // and the write buffer is empty
1389
                                                ;
1390
// Since IMM is "sticky" we have to check for it.
1391
wire triggerICacheLoad = !ihit & !triggerDCacheLoad &   // There is a miss
1392
                                                (dOpcode==`NOPI || dOpcode[6:4]==`IMM) &&                       // and the pipeline is flushed
1393
                                                (xOpcode==`NOPI || xOpcode[6:4]==`IMM) &&
1394
                                                m1Opcode==`NOPI &&
1395
                                                m2Opcode==`NOPI &&
1396
                                                m3Opcode==`NOPI &&
1397
                                                m4Opcode==`NOPI
1398
                                                ;
1399
wire EXexception_pending = ovr_error || dbz_error || priv_violation || xOpcode==`TRAPcci || xOpcode==`TRAPcc;
1400
wire M1exception_pending = advanceM1 & (m1IsLoad|m1IsStore) & DTLBMiss;
1401
wire exception_pending = EXexception_pending | M1exception_pending;
1402
 
1403
wire xWillLoadStore = (xIsLoad||xIsStore) & advanceX;
1404
wire stallCacheLoad = xWillLoadStore;
1405
 
1406
reg prev_nmi,nmi_edge;
1407
 
1408
 
1409
//---------------------------------------------------------
1410
// Register file.
1411
//---------------------------------------------------------
1412
 
1413
syncRam512x64_1rw3r u5
1414
(
1415
        .wrst(1'b0),
1416
        .wclk(clk),
1417
        .wce(advanceW),
1418
        .we(1'b1),
1419
        .wadr(wRt),
1420
        .i(wData),
1421
        .wo(),
1422
 
1423
        .rrsta(1'b0),
1424
        .rclka(~clk),
1425
        .rcea(advanceR),
1426
        .radra(dRa),
1427
        .roa(rfoa),
1428
 
1429
        .rrstb(1'b0),
1430
        .rclkb(~clk),
1431
        .rceb(advanceR),
1432
        .radrb(dRb),
1433
        .rob(rfob),
1434
 
1435
        .rrstc(1'b0),
1436
        .rclkc(~clk),
1437
        .rcec(advanceR),
1438
        .radrc(dRc),
1439
        .roc(rfoc)
1440
);
1441
 
1442
 
1443
reg m1clkoff,m2clkoff,m3clkoff,m4clkoff,wclkoff;
1444
reg [15:0] dFip;
1445
reg xFip,m1Fip,m2Fip,m3Fip,m4Fip,wFip;
1446
 
1447
always @(posedge clk)
1448
if (rst_i) begin
1449
        bte_o <= 2'b00;
1450
        cti_o <= 3'b000;
1451
        cyc_o <= 1'b0;
1452
        stb_o <= 1'b0;
1453
        we_o <= 1'b0;
1454
        sel_o <= 8'h00;
1455
        adr_o <= 64'd0;
1456
        dat_o <= 64'd0;
1457
        dccyc <= 1'b0;
1458
 
1459
        cmd_en <= 1'b0;
1460
        cmd_instr <= 3'b001;
1461
        cmd_bl <= 6'd1;
1462
        cmd_byte_addr <= 30'd0;
1463
 
1464
        rd_en <= 1'b0;
1465
        wr_en <= 1'b0;
1466
 
1467
//      pc[0] <= 64'hFFFF_FFFF_FFFF_FFE0;
1468
        m1Opcode <= `NOPI;
1469
        m2Opcode <= `NOPI;
1470
        m3Opcode <= `NOPI;
1471
        m4Opcode <= `NOPI;
1472
        dIR <= `NOP_INSN;
1473
        dRt <= 9'd0;
1474
        tRt <= 9'd0;
1475
        wRt <= 9'd0;
1476
        m1Rt <= 9'd0;
1477
        m2Rt <= 9'd0;
1478
        m3Rt <= 9'd0;
1479
        m4Rt <= 9'd0;
1480
        tData <= 64'd0;
1481
        wData <= 64'd0;
1482
        m1Data <= 64'd0;
1483
        m2Data <= 64'd0;
1484
        m3Data <= 64'd0;
1485
        m4Data <= 64'd0;
1486
        icaccess <= 1'b0;
1487
        dcaccess <= 1'b0;
1488
        nopI <= 1'b0;
1489
        prev_ihit <= 1'b0;
1490
        wirqf <= 1'b0;
1491
        m1irqf <= 1'b0;
1492
        m2irqf <= 1'b0;
1493
        m3irqf <= 1'b0;
1494
        m4irqf <= 1'b0;
1495
        wFip <= 1'b0;
1496
        m4Fip <= 1'b0;
1497
        m3Fip <= 1'b0;
1498
        m2Fip <= 1'b0;
1499
        m1Fip <= 1'b0;
1500
        xFip <= 1'b0;
1501
        dFip <= 16'h0000;
1502
        dirqf <= 16'h0000;
1503
        tick <= 32'd0;
1504
        cstate <= IDLE;
1505
        dImm <= 64'd0;
1506
        regset <= 4'd0;
1507
        xirqf <= 1'b0;
1508
        xextype <= 8'h00;
1509
        xIR <= `NOP_INSN;
1510
        xpc <= 64'd0;
1511
        a <= 64'd0;
1512
        b <= 64'd0;
1513
        imm <= 64'd0;
1514
        xRt <= 9'd0;
1515
        clk_en <= 1'b1;
1516
        Random <= 4'hF;
1517
        Wired <= 4'd0;
1518
        StatusEXL <= 16'b0;
1519
        StatusHWI <= 16'h0;
1520
        epcnt <= 5'd0;
1521
        EP[0] <= 32'h00000000;
1522
        EP[1] <= 32'h00000000;
1523
        EP[2] <= 32'h00000000;
1524
        EP[3] <= 32'h00000000;
1525
        AXC <= 4'd0;
1526
        dAXC <= 4'd0;
1527
        xAXC <= 4'd0;
1528
        m1AXC <= 4'd0;
1529
        m2AXC <= 4'd0;
1530
        m3AXC <= 4'd0;
1531
        m4AXC <= 4'd0;
1532
        wAXC <= 4'd0;
1533
        resetA <= 1'b1;
1534
//      gbl_branch_hist <= 3'b000;
1535
end
1536
else begin
1537
 
1538
//---------------------------------------------------------
1539
// Initialize program counters
1540
//---------------------------------------------------------
1541
if (resetA) begin
1542
        pc[xAXC] <= `RESET_VECTOR;
1543
        gbl_branch_hist[AXC] <= 3'b000;
1544
        xAXC <= xAXC + 4'd1;
1545
        if (xAXC==4'hF)
1546
                resetA <= 1'b0;
1547
end
1548
 
1549
cmd_en <= 1'b0;                         // allow this signal only to pulse for a single clock cycle
1550
wr_en <= 1'b0;                                  // allow this signal to only pulse for a single cycle
1551
if (Random==Wired)
1552
        Random <= 4'hF;
1553
else
1554
        Random <= Random - 4'd1;
1555
 
1556
tick <= tick + 64'd1;
1557
 
1558
prev_nmi <= nmi_i;
1559
if (!prev_nmi & nmi_i)
1560
        nmi_edge <= 1'b1;
1561
 
1562
 
1563
// A store by any device in the system to a reserved address blcok
1564
// clears the reservation.
1565
 
1566
if (sys_adv && sys_adr[63:5]==resv_address)
1567
        resv_address <= 59'd0;
1568
 
1569
//---------------------------------------------------------
1570
// TRAILER:
1571
// - placeholder to allow the use of synchronous register
1572
//   memory
1573
//---------------------------------------------------------
1574
if (advanceT) begin
1575
        tRt <= 9'd0;
1576
        tData <= 64'd0;
1577
end
1578
 
1579
//---------------------------------------------------------
1580
// WRITEBACK:
1581
// - update the register file with results
1582
// - record exception address and type
1583
// - jump to exception handler routine (below)
1584
//---------------------------------------------------------
1585
if (advanceW) begin
1586
        textype <= wextype;
1587
        wextype <= `EX_NON;
1588
        tRt <= wRt;
1589
        tData <= wData;
1590
//      regfile[wRt] <= wData;  <- regfile.v
1591
        $display("Writing regfile[%d:%d] with %h", wRt[8:5],wRt[4:0], wData);
1592
        wRt <= 9'd0;
1593
        wData <= 64'd0;
1594
        if (wirqf) begin
1595
                wirqf <= 1'b0;
1596
                if (m1AXC==wAXC) m1irqf <= 1'b0;
1597
                if (m2AXC==wAXC) m2irqf <= 1'b0;
1598
                if (m3AXC==wAXC) m3irqf <= 1'b0;
1599
                if (m4AXC==wAXC) m4irqf <= 1'b0;
1600
                if (xAXC==wAXC) xirqf <= 1'b0;
1601
                dirqf[wAXC] <= 1'b0;
1602
                exception_type <= wextype;
1603
        end
1604
        clk_en <= 1'b1;
1605
        if (wclkoff)
1606
                clk_en <= 1'b0;
1607
        wclkoff <= 1'b0;
1608
        m1clkoff <= 1'b0;
1609
        m2clkoff <= 1'b0;
1610
        m3clkoff <= 1'b0;
1611
        m4clkoff <= 1'b0;
1612
        if (wFip) begin
1613
                wFip <= 1'b0;
1614
                if (m4AXC==wAXC) m4Fip <= 1'b0;
1615
                if (m3AXC==wAXC) m3Fip <= 1'b0;
1616
                if (m2AXC==wAXC) m2Fip <= 1'b0;
1617
                if (m1AXC==wAXC) m1Fip <= 1'b0;
1618
                if (xAXC==wAXC) xFip <= 1'b0;
1619
                dFip[wAXC] <= 1'b0;
1620
        end
1621
end
1622
 
1623
//---------------------------------------------------------
1624
// MEMORY:
1625
// - merge word load data into pipeline.
1626
//---------------------------------------------------------
1627
if (advanceM4) begin
1628
        wirqf <= m4irqf;
1629
        wFip <= m4Fip;
1630
        wAXC <= m4AXC;
1631
        wextype <= m4extype;
1632
        wRt <= m4Rt;
1633
        wpc <= m4pc;
1634
        wclkoff <= m4clkoff;
1635
        wData <= m4Data;
1636
 
1637
        m4Rt <= 9'd0;
1638
        m4Opcode <= `NOPI;
1639
        m4Data <= 64'd0;
1640
        m4clkoff <= 1'b0;
1641
        m4Opcode <= `NOPI;
1642
        m4extype <= `EX_NON;
1643
        if (m4extype==`EX_NON) begin
1644
                case(m4Opcode)
1645
                `LW,`LWR:       begin
1646
                                                wData <= {rd_data,m4Data[31:0]};
1647
                                                rd_en <= 1'b0;  // only if LW/LWR
1648
                                        end
1649
                default:        wData <= m4Data;
1650
                endcase
1651
        end
1652
end
1653
 
1654
 
1655
//---------------------------------------------------------
1656
// MEMORY:
1657
//---------------------------------------------------------
1658
if (advanceM3) begin
1659
        m4Opcode <= m3Opcode;
1660
        m4Func <= m3Func;
1661
        m4irqf <= m3irqf;
1662
        m4Fip <= m3Fip;
1663
        m4AXC <= m3AXC;
1664
        m4extype <= m3extype;
1665
        m4Rt <= m3Rt;
1666
        m4pc <= m3pc;
1667
        m4clkoff <= m3clkoff;
1668
 
1669
        m3Rt <= 9'd0;
1670
        m3Opcode <= `NOPI;
1671
        m3Func <= 7'd0;
1672
        m3clkoff <= 1'b0;
1673
        m3pc <= 64'd0;
1674
        m4Data <= m3Data;
1675
        m3Addr <= 64'd0;
1676
        m3Data <= 64'd0;
1677
        m3extype <= `EX_NON;
1678
        if (m3extype==`EX_NON) begin
1679
                case(m3Opcode)
1680
                `INW:
1681
                        begin
1682
                                cyc_o <= 1'b0;
1683
                                stb_o <= 1'b0;
1684
                                sel_o <= 4'h0;
1685
                                m4Data <= {dat_i,m3Data[31:0]};
1686
                        end
1687
                `OUTW:
1688
                        begin
1689
                                cyc_o <= 1'b0;
1690
                                stb_o <= 1'b0;
1691
                                we_o <= 1'b0;
1692
                                sel_o <= 4'h0;
1693
                        end
1694
                `LW,`LWR:
1695
                        begin
1696
                                rd_en <= 1'b1;
1697
                                m4Data <= {32'd0,rd_data};
1698
                        end
1699
                `LH:
1700
                        begin
1701
                        rd_en <= 1'b0;
1702
                        m4Data <= {{32{rd_data[31]}},rd_data};
1703
                        end
1704
                `LHU:
1705
                        begin
1706
                        rd_en <= 1'b0;
1707
                        m4Data <= rd_data;
1708
                        end
1709
                `LC:
1710
                        begin
1711
                        rd_en <= 1'b0;
1712
                        case(m3Addr[1])
1713
                        1'b0:   m4Data <= {{48{rd_data[15]}},rd_data[15:0]};
1714
                        1'b1:   m4Data <= {{48{rd_data[31]}},rd_data[31:16]};
1715
                        endcase
1716
                        end
1717
                `LCU:
1718
                        begin
1719
                        rd_en <= 1'b0;
1720
                        case(m3Addr[1])
1721
                        1'b0:   m4Data <= {48'd0,rd_data[15:0]};
1722
                        1'b1:   m4Data <= {48'd0,rd_data[31:16]};
1723
                        endcase
1724
                        end
1725
                `LB:
1726
                        begin
1727
                        rd_en <= 1'b0;
1728
                        case(m3Addr[1:0])
1729
                        2'd0:   m4Data <= {{56{rd_data[7]}},rd_data[7:0]};
1730
                        2'd1:   m4Data <= {{56{rd_data[15]}},rd_data[15:8]};
1731
                        2'd2:   m4Data <= {{56{rd_data[23]}},rd_data[23:16]};
1732
                        2'd3:   m4Data <= {{56{rd_data[31]}},rd_data[31:24]};
1733
                        endcase
1734
                        end
1735
                `LBU:
1736
                        begin
1737
                        case(m3Addr[1:0])
1738
                        2'd0:   m4Data <= {{56{rd_data[7]}},rd_data[7:0]};
1739
                        2'd1:   m4Data <= {{56{rd_data[15]}},rd_data[15:8]};
1740
                        2'd2:   m4Data <= {{56{rd_data[23]}},rd_data[23:16]};
1741
                        2'd3:   m4Data <= {{56{rd_data[31]}},rd_data[31:24]};
1742
                        endcase
1743
                        rd_en <= 1'b0;
1744
                        end
1745
                `SW,`SWC:
1746
                        begin
1747
                                cmd_en <= 1'b1;
1748
                                cmd_instr <= 3'b000;    // WRITE
1749
                                cmd_bl <= 6'd2;                 // 2-words
1750
                                cmd_byte_addr <= {m3Addr[29:3],3'b000};
1751
                        end
1752
                default:        ;
1753
                endcase
1754
        end
1755
end
1756
 
1757
//---------------------------------------------------------
1758
// MEMORY:
1759
//---------------------------------------------------------
1760
if (advanceM2) begin
1761
        m3Opcode <= m2Opcode;
1762
        m3Func <= m2Func;
1763
        m3Addr <= m2Addr;
1764
        m3Data <= m2Data;
1765
        m3irqf <= m2irqf;
1766
        m3AXC <= m2AXC;
1767
        m3extype <= m2extype;
1768
        m3Rt <= m2Rt;
1769
        m3pc <= m2pc;
1770
        m3clkoff <= m2clkoff;
1771
        m3Fip <= m2Fip;
1772
 
1773
        m2Rt <= 9'd0;
1774
        m2Opcode <= `NOPI;
1775
        m2Func <= 7'd0;
1776
        m2Addr <= 64'd0;
1777
        m2Data <= 64'd0;
1778
        m2clkoff <= 1'b0;
1779
        m2pc <= 64'd0;
1780
        m2extype <= `EX_NON;
1781
        if (m2extype==`EX_NON) begin
1782
                case(m2Opcode)
1783
                `INW:
1784
                        begin
1785
                        stb_o <= 1'b1;
1786
                        sel_o <= 4'hF;
1787
                        adr_o <= {m2Addr[63:3],3'b100};
1788
                        end
1789
                `OUTW:
1790
                        begin
1791
                        stb_o <= 1'b1;
1792
                        we_o <= 1'b1;
1793
                        sel_o <= 4'hF;
1794
                        adr_o <= {m2Addr[63:3],3'b100};
1795
                        dat_o <= m2Data[63:32];
1796
                        end
1797
                // Load fifo with upper half of word
1798
                `SW,`SWC:
1799
                        begin
1800
                                wr_en <= 1'b1;
1801
                                wr_data <= m2Data[63:32];
1802
                                wr_mask <= 4'h0;
1803
                                wr_addr <= {m2Addr[63:3],3'b100};
1804
                        end
1805
                `SH,`SC,`SB:
1806
                        begin
1807
                                cmd_en <= 1'b1;
1808
                                cmd_instr <= 3'b000;    // WRITE
1809
                                cmd_bl <= 6'd1;                 // 1-word
1810
                                cmd_byte_addr <= {m2Addr[29:2],2'b00};
1811
                        end
1812
                // Initiate read operation
1813
                `LW,`LWR,`LH,`LC,`LB,`LHU,`LBU,`LCU:
1814
                        begin
1815
                                rd_en <= 1'b1;
1816
                        end
1817
                default:        ;
1818
                endcase
1819
        end
1820
end
1821
 
1822
wrhit <= 1'b0;
1823
//---------------------------------------------------------
1824
// MEMORY:
1825
// On a data cache hit for a load, the load is essentially
1826
// finished in this stage. We switch the opcode to 'LDONE'
1827
// to cause the pipeline to advance as if a NOPs were
1828
// present.
1829
//---------------------------------------------------------
1830
if (advanceM1) begin
1831
        m2Opcode <= m1Opcode;
1832
        m2Func <= m1Func;
1833
        m2Addr <= pea;
1834
        m2Data <= m1Data;
1835
        m2irqf <= m1irqf;
1836
        m2AXC <= m1AXC;
1837
        m2extype <= m1extype;
1838
        m2Rt <= m1Rt;
1839
        m2pc <= m1pc;
1840
        m2clkoff <= m1clkoff;
1841
        m2Fip <= m1Fip;
1842
 
1843
        m1Rt <= 9'd0;
1844
        m1Opcode <= `NOPI;
1845
        m1Func <= 7'd0;
1846
        m1Data <= 64'd0;
1847
        m1clkoff <= 1'b0;
1848
        m1pc <= 64'd0;
1849
        m1IsCacheElement <= 1'b0;
1850
        m1extype <= `EX_NON;
1851
 
1852
        if (m1extype == `EX_NON) begin
1853
                case(m1Opcode)
1854
                `MISC:
1855
                        case(m1Func)
1856
                        `TLBP:  Index[31] <= ~|DMatch;
1857
                        `TLBR:
1858
                                begin
1859
                                        TLBPageMask <= tTLBPageMask[i];
1860
                                        TLBVirtPage <= tTLBVirtPage[i];
1861
                                        TLBPhysPage0 <= tTLBPhysPage0[i];
1862
                                        TLBPhysPage1 <= tTLBPhysPage1[i];
1863
                                        TLBASID <= tTLBASID[i];
1864
                                        TLBG <= tTLBG[i];
1865
                                        TLBD <= tTLBD[i];
1866
                                        TLBValid <= tTLBValid[i];
1867
                                end
1868
                        `TLBWI,`TLBWR:
1869
                                begin
1870
                                        tTLBValid[i] <= 1'b1;
1871
                                        tTLBVirtPage[i] <= TLBVirtPage;
1872
                                        tTLBPhysPage0[i] <= TLBPhysPage0;
1873
                                        tTLBPhysPage1[i] <= TLBPhysPage1;
1874
                                        tTLBPageMask[i] <= TLBPageMask;
1875
                                        tTLBASID[i] <= TLBASID;
1876
                                        tTLBD[i] <= TLBD;
1877
                                        tTLBG[i] <= TLBG;
1878
                                        tTLBValid[i] <= TLBValid;
1879
                                end
1880
                        endcase
1881
                `INW:
1882
                        begin
1883
                                stb_o <= 1'b0;
1884
                                m2Data <= {32'd0,dat_i};
1885
                        end
1886
                `INH:
1887
                        begin
1888
                                cyc_o <= 1'b0;
1889
                                stb_o <= 1'b0;
1890
                                sel_o <= 4'd0;
1891
                                m2Data <= {{32{dat_i[31]}},dat_i[31: 0]};
1892
                        end
1893
                `INCH:
1894
                        begin
1895
                                cyc_o <= 1'b0;
1896
                                stb_o <= 1'b0;
1897
                                sel_o <= 4'd0;
1898
                                case(sel_o)
1899
                                4'b0011:        m2Data <= {{48{dat_i[15]}},dat_i[15: 0]};
1900
                                4'b1100:        m2Data <= {{48{dat_i[31]}},dat_i[31:16]};
1901
                                default:        m2Data <= 64'hDEADDEADDEADDEAD;
1902
                                endcase
1903
                        end
1904
                `INB:
1905
                        begin
1906
                                cyc_o <= 1'b0;
1907
                                stb_o <= 1'b0;
1908
                                sel_o <= 4'd0;
1909
                                case(sel_o)
1910
                                4'b0001:        m2Data <= {{56{dat_i[ 7]}},dat_i[ 7: 0]};
1911
                                4'b0010:        m2Data <= {{56{dat_i[15]}},dat_i[15: 8]};
1912
                                4'b0100:        m2Data <= {{56{dat_i[23]}},dat_i[23:16]};
1913
                                4'b1000:        m2Data <= {{56{dat_i[31]}},dat_i[31:24]};
1914
                                default:        m2Data <= 64'hDEADDEADDEADDEAD;
1915
                                endcase
1916
                        end
1917
                `OUTW:
1918
                        begin
1919
                                stb_o <= 1'b0;
1920
                                we_o <= 1'b0;
1921
                                sel_o <= 4'd0;
1922
                        end
1923
                `OUTH,`OUTC,`OUTB:
1924
                        begin
1925
                                cyc_o <= 1'b0;
1926
                                stb_o <= 1'b0;
1927
                                we_o <= 1'b0;
1928
                                sel_o <= 4'd0;
1929
                        end
1930
                `LW:
1931
                        if (!m1IsCacheElement) begin
1932
                                cmd_en <= 1'b1;
1933
                                cmd_bl <= 6'd2;                 // 2-words (from 32-bit interface)
1934
                                cmd_instr <= 3'b001;    // READ
1935
                                cmd_byte_addr <= {pea[63:3],3'b000};
1936
                        end
1937
                        else if (dhit) begin
1938
                                m2Opcode <= `LDONE;
1939
                                m2Data <= cdat;
1940
                        end
1941
                `LWR:
1942
                        if (!m1IsCacheElement) begin
1943
                                cmd_en <= 1'b1;
1944
                                cmd_bl <= 6'd2;                 // 2-words (from 32-bit interface)
1945
                                cmd_instr <= 3'b001;    // READ
1946
                                cmd_byte_addr <= {pea[63:3],3'b000};
1947
                                rsv_o <= 1'b1;
1948
                                resv_address <= pea[63:5];
1949
                        end
1950
                        else if (dhit) begin
1951
                                m2Opcode <= `LDONE;
1952
                                m2Data <= cdat;
1953
                                rsv_o <= 1'b1;
1954
                                resv_address <= pea[63:5];
1955
                        end
1956
                `LH:
1957
                        if (!m1IsCacheElement) begin
1958
                                cmd_en <= 1'b1;
1959
                                cmd_bl <= 6'd1;                 // 1-words (from 32-bit interface)
1960
                                cmd_instr <= 3'b001;    // READ
1961
                                cmd_byte_addr <= {pea[63:2],2'b00};
1962
                        end
1963
                        else if (dhit) begin
1964
                                m2Opcode <= `LDONE;
1965
                                if (pea[1])
1966
                                        m2Data <= {{32{cdat[31]}},cdat[31:0]};
1967
                                else
1968
                                        m2Data <= {{32{cdat[63]}},cdat[63:32]};
1969
                        end
1970
                `LHU:
1971
                        if (!m1IsCacheElement) begin
1972
                                cmd_en <= 1'b1;
1973
                                cmd_bl <= 6'd1;                 // 1-words (from 32-bit interface)
1974
                                cmd_instr <= 3'b001;    // READ
1975
                                cmd_byte_addr <= {pea[63:2],2'b00};
1976
                        end
1977
                        else if (dhit) begin
1978
                                m2Opcode <= `LDONE;
1979
                                if (pea[1])
1980
                                        m2Data <= {32'd0,cdat};
1981
                                else
1982
                                        m2Data <= {32'd0,cdat[63:32]};
1983
                        end
1984
                `LC:
1985
                        if (!m1IsCacheElement) begin
1986
                                cmd_en <= 1'b1;
1987
                                cmd_bl <= 6'd1;                 // 1-words (from 32-bit interface)
1988
                                cmd_instr <= 3'b001;    // READ
1989
                                cmd_byte_addr <= {pea[63:2],2'b00};
1990
                        end
1991
                        else if (dhit) begin
1992
                                m2Opcode <= `LDONE;
1993
                                case(pea[2:1])
1994
                                2'd0:   m2Data <= {{48{cdat[15]}},cdat[15:0]};
1995
                                2'd1:   m2Data <= {{48{cdat[31]}},cdat[31:16]};
1996
                                2'd2:   m2Data <= {{48{cdat[47]}},cdat[47:32]};
1997
                                2'd3:   m2Data <= {{48{cdat[63]}},cdat[63:48]};
1998
                                endcase
1999
                        end
2000
                `LCU:
2001
                        if (!m1IsCacheElement) begin
2002
                                cmd_en <= 1'b1;
2003
                                cmd_bl <= 6'd1;                 // 1-words (from 32-bit interface)
2004
                                cmd_instr <= 3'b001;    // READ
2005
                                cmd_byte_addr <= {pea[63:2],2'b00};
2006
                        end
2007
                        else if (dhit) begin
2008
                                m2Opcode <= `LDONE;
2009
                                case(pea[2:1])
2010
                                2'd0:   m2Data <= {48'd0,cdat[15: 0]};
2011
                                2'd1:   m2Data <= {48'd0,cdat[31:16]};
2012
                                2'd2:   m2Data <= {48'd0,cdat[47:32]};
2013
                                2'd3:   m2Data <= {48'd0,cdat[63:48]};
2014
                                endcase
2015
                        end
2016
                `LB:
2017
                        if (!m1IsCacheElement) begin
2018
                                cmd_en <= 1'b1;
2019
                                cmd_bl <= 6'd1;                 // 1-words (from 32-bit interface)
2020
                                cmd_instr <= 3'b001;    // READ
2021
                                cmd_byte_addr <= {pea[63:2],2'b00};
2022
                        end
2023
                        else if (dhit) begin
2024
                                m2Opcode <= `LDONE;
2025
                                case(pea[2:0])
2026
                                3'b000: m2Data <= {{56{cdat[ 7]}},cdat[ 7: 0]};
2027
                                3'b001: m2Data <= {{56{cdat[15]}},cdat[15: 8]};
2028
                                3'b010: m2Data <= {{56{cdat[23]}},cdat[23:16]};
2029
                                3'b011: m2Data <= {{56{cdat[31]}},cdat[31:24]};
2030
                                3'b100: m2Data <= {{56{cdat[39]}},cdat[39:32]};
2031
                                3'b101: m2Data <= {{56{cdat[47]}},cdat[47:40]};
2032
                                3'b110: m2Data <= {{56{cdat[55]}},cdat[55:48]};
2033
                                3'b111: m2Data <= {{56{cdat[63]}},cdat[63:56]};
2034
                                endcase
2035
                        end
2036
                `LBU:
2037
                        if (!m1IsCacheElement) begin
2038
                                cmd_en <= 1'b1;
2039
                                cmd_bl <= 6'd1;                 // 1-words (from 32-bit interface)
2040
                                cmd_instr <= 3'b001;    // READ
2041
                                cmd_byte_addr <= {pea[63:2],2'b00};
2042
                        end
2043
                        else if (dhit) begin
2044
                                m2Opcode <= `LDONE;
2045
                                case(pea[2:0])
2046
                                3'b000: m2Data <= {56'd0,cdat[ 7: 0]};
2047
                                3'b001: m2Data <= {56'd0,cdat[15: 8]};
2048
                                3'b010: m2Data <= {56'd0,cdat[23:16]};
2049
                                3'b011: m2Data <= {56'd0,cdat[31:23]};
2050
                                3'b100: m2Data <= {56'd0,cdat[39:32]};
2051
                                3'b101: m2Data <= {56'd0,cdat[47:40]};
2052
                                3'b110: m2Data <= {56'd0,cdat[55:48]};
2053
                                3'b111: m2Data <= {56'd0,cdat[63:56]};
2054
                                endcase
2055
                        end
2056
                `SW,`SH:
2057
                        begin
2058
                                if (!m1UnmappedDataArea & !q[4]) begin
2059
                                        tTLBD[q] <= 1'b1;
2060
                                end
2061
                                wrhit <= dhit;
2062
                                wr_en <= 1'b1;
2063
                                wr_data <= m1b[31:0];
2064
                                wr_mask <= 4'h0;
2065
                                wr_addr <= {pea[63:3],3'b000};
2066
                                m2Addr <= {pea[63:3],3'b000};
2067
                                if (resv_address==pea[63:5])
2068
                                        resv_address <= 59'd0;
2069
                        end
2070
                `SC:
2071
                        begin
2072
                                $display("Storing char to %h, ea=%h",pea,ea);
2073
                                if (!m1UnmappedDataArea & !q[4]) begin
2074
                                        tTLBD[q] <= 1'b1;
2075
                                end
2076
                                wrhit <= dhit;
2077
                                wr_en <= 1'b1;
2078
                                wr_data <= {2{m1b[15:0]}};
2079
                                wr_mask <= pea[1] ? 4'b0011 : 4'b1100;
2080
                                wr_addr <= {pea[63:2],2'b00};
2081
                                m2Addr <= {pea[63:2],2'b00};
2082
                                if (resv_address==pea[63:5])
2083
                                        resv_address <= 59'd0;
2084
                        end
2085
                `SB:
2086
                        begin
2087
                                if (!m1UnmappedDataArea & !q[4]) begin
2088
                                        tTLBD[q] <= 1'b1;
2089
                                end
2090
                                wrhit <= dhit;
2091
                                wr_en <= 1'b1;
2092
                                wr_data <= {4{m1b[7:0]}};
2093
                                wr_addr <= {pea[63:2],2'b00};
2094
                                m2Addr <= {pea[63:2],2'b00};
2095
                                case(pea[1:0])
2096
                                2'd0:   wr_mask <= 4'b1110;
2097
                                2'd1:   wr_mask <= 4'b1101;
2098
                                2'd2:   wr_mask <= 4'b1011;
2099
                                2'd3:   wr_mask <= 4'b0111;
2100
                                endcase
2101
                                if (resv_address==pea[63:5])
2102
                                        resv_address <= 59'd0;
2103
                        end
2104
                `SWC:
2105
                        begin
2106
                                rsf <= 1'b0;
2107
                                if (resv_address==pea[63:5]) begin
2108
                                        if (!m1UnmappedDataArea & !q[4]) begin
2109
                                                tTLBD[q] <= 1'b1;
2110
                                        end
2111
                                        wrhit <= dhit;
2112
                                        wr_en <= 1'b1;
2113
                                        wr_data <= m1b[31:0];
2114
                                        wr_mask <= 4'h0;
2115
                                        wr_addr <= {pea[63:3],3'b000};
2116
                                        m2Addr <= {pea[63:3],3'b000};
2117
                                        resv_address <= 59'd0;
2118
                                        rsf <= 1'b1;
2119
                                end
2120
                                else
2121
                                        m2Opcode <= `NOPI;
2122
                        end
2123
                endcase
2124
        end
2125
end
2126
 
2127
//---------------------------------------------------------
2128
// EXECUTE:
2129
// - perform datapath operation
2130
// - Stores always initiate a bus cycle
2131
// - Loads initiate a bus cycle only from non-cacheable
2132
//   addresses
2133
//---------------------------------------------------------
2134
if (advanceX) begin
2135
        m1irqf <= xirqf;
2136
        m1Fip <= xFip;
2137
        m1extype <= xextype;
2138
        m1Opcode <= xOpcode;
2139
        m1Func <= xFunc;
2140
        m1Rt <= xRt;
2141
        m1Data <= xData;
2142
        m1IsCacheElement <= xisCacheElement;
2143
        m1UnmappedDataArea <= unmappedDataArea;
2144
        m1AXC <= xAXC;
2145
        if (xOpcode==`MOVZ && !aeqz) begin
2146
                m1Rt <= 9'd0;
2147
                m1Data <= 64'd0;
2148
        end
2149
        if (xOpcode==`MOVNZ && aeqz) begin
2150
                m1Rt <= 9'd0;
2151
                m1Data <= 64'd0;
2152
        end
2153
        m1pc <= xpc;
2154
        xRt <= 9'd0;
2155
        a <= 64'd0;
2156
        b <= 64'd0;
2157
        imm <= 64'd0;
2158
        xextype <= `EX_NON;
2159
        if (xOpcode[6:4]!=`IMM) begin
2160
                xIR <= `NOP_INSN;
2161
        end
2162
//      xpc <= 64'd0;
2163
        case(xOpcode)
2164
        `MISC:
2165
                case(xFunc)
2166
                `WAIT:  m1clkoff <= 1'b1;
2167
                `TLBP:  ea <= TLBVirtPage;
2168
                `TLBR,`TLBWI:
2169
                        begin
2170
                                i <= Index;
2171
                        end
2172
                `TLBWR:
2173
                        begin
2174
                                i <= Random;
2175
                        end
2176
                default:        ;
2177
                endcase
2178
        `R:
2179
                case(xFunc)
2180
                `MTSPR:
2181
                        case(xIR[12:7])
2182
                        `Wired:                 Wired <= xData[3:0];
2183
                        `ASID:                  ASID <= xData[7:0];
2184
                        `TLBIndex:              Index <= xData[3:0];
2185
                        `TLBVirtPage:   TLBVirtPage <= xData[63:13];
2186
                        `TLBPhysPage0:  TLBPhysPage0 <= xData[63:13];
2187
                        `TLBPhysPage1:  TLBPhysPage1 <= xData[63:13];
2188
                        `TLBPageMask:   TLBPageMask <= xData[24:13];
2189
                        `TLBASID:               begin
2190
                                                        TLBASID <= xData[15:8];
2191
                                                        TLBD <= xData[1];
2192
                                                        TLBValid <= xData[0];
2193
                                                        TLBG <= xData[2];
2194
                                                        end
2195
                        `PageTableAddr: PageTableAddr <= xData[63:13];
2196
                        `BadVAddr:              BadVAddr[xAXC] <= xData[63:13];
2197
                        `EP0:                   EP[0] <= {xData[31:4],4'd0};
2198
                        `EP1:                   EP[1] <= xData[31:0];
2199
                        `EP2:                   EP[2] <= xData[31:0];
2200
                        `EP3:                   EP[3] <= xData[31:0];
2201
                        `EPC:                   EPC[xAXC] <= xData;
2202
                        `TBA:                   TBA <= xData;
2203
                        default:        ;
2204
                        endcase
2205
                `MTTBA: tba <= {xData[63:2],2'b00};
2206
                `OMG:   mutex_gate[a[5:0]] <= 1'b1;
2207
                `CMG:   mutex_gate[a[5:0]] <= 1'b0;
2208
                `OMGI:  mutex_gate[xIR[12:7]] <= 1'b1;
2209
                `CMGI:  mutex_gate[xIR[12:7]] <= 1'b0;
2210
                default:        ;
2211
                endcase
2212
        `CALL:  m1Data <= fnIncPC(xpc);
2213
        `INW:
2214
                        begin
2215
                        cyc_o <= 1'b1;
2216
                        stb_o <= 1'b1;
2217
                        sel_o <= 4'hF;
2218
                        adr_o <= {xData[63:3],3'b000};
2219
                        end
2220
        `INH:
2221
                        begin
2222
                        cyc_o <= 1'b1;
2223
                        stb_o <= 1'b1;
2224
                        sel_o <= 4'b1111;
2225
                        adr_o <= {xData[63:2],2'b00};
2226
                        end
2227
        `INCH:
2228
                        begin
2229
                        cyc_o <= 1'b1;
2230
                        stb_o <= 1'b1;
2231
                        case(xData[1])
2232
                        1'b0:   sel_o <= 4'b0011;
2233
                        1'b1:   sel_o <= 4'b1100;
2234
                        endcase
2235
                        adr_o <= {xData[63:1],1'b0};
2236
                        end
2237
        `INB:
2238
                        begin
2239
                        cyc_o <= 1'b1;
2240
                        stb_o <= 1'b1;
2241
                        case(xData[1:0])
2242
                        2'b00:  sel_o <= 8'b0001;
2243
                        2'b01:  sel_o <= 8'b0010;
2244
                        2'b10:  sel_o <= 8'b0100;
2245
                        2'b11:  sel_o <= 8'b1000;
2246
                        endcase
2247
                        adr_o <= xData;
2248
                        end
2249
        `OUTW:
2250
                        begin
2251
                        cyc_o <= 1'b1;
2252
                        stb_o <= 1'b1;
2253
                        we_o <= 1'b1;
2254
                        sel_o <= 4'hF;
2255
                        adr_o <= {xData[63:3],3'b000};
2256
                        dat_o <= b[31:0];
2257
                        end
2258
        `OUTH:
2259
                        begin
2260
                        cyc_o <= 1'b1;
2261
                        stb_o <= 1'b1;
2262
                        we_o <= 1'b1;
2263
                        sel_o <= 4'b1111;
2264
                        adr_o <= {xData[63:2],2'b00};
2265
                        dat_o <= b[31:0];
2266
                        end
2267
        `OUTC:
2268
                        begin
2269
                        cyc_o <= 1'b1;
2270
                        stb_o <= 1'b1;
2271
                        we_o <= 1'b1;
2272
                        case(xData[1])
2273
                        1'b0:   sel_o <= 4'b0011;
2274
                        1'b1:   sel_o <= 4'b1100;
2275
                        endcase
2276
                        adr_o <= {xData[63:1],1'b0};
2277
                        dat_o <= {2{b[15:0]}};
2278
                        end
2279
        `OUTB:
2280
                        begin
2281
                        cyc_o <= 1'b1;
2282
                        stb_o <= 1'b1;
2283
                        we_o <= 1'b1;
2284
                        case(xData[1:0])
2285
                        2'b00:  sel_o <= 4'b0001;
2286
                        2'b01:  sel_o <= 4'b0010;
2287
                        2'b10:  sel_o <= 4'b0100;
2288
                        2'b11:  sel_o <= 4'b1000;
2289
                        endcase
2290
                        adr_o <= xData;
2291
                        dat_o <= {4{b[7:0]}};
2292
                        end
2293
        `LB,`LBU,`LC,`LCU,`LH,`LHU,`LW,`LWR,`SW,`SH,`SC,`SB,`SWC:
2294
                        begin
2295
                        m1b <= b;
2296
                        ea <= xData;
2297
                        end
2298
        `MEMNDX:
2299
                        begin
2300
                        m1Opcode <= xFunc;
2301
                        m1b <= c;
2302
                        ea <= xData;
2303
                        end
2304
        `DIVSI,`DIVUI:
2305
                if (b==64'd0) begin
2306
                        xextype <= `EX_DBZ;
2307
                end
2308
        default:        ;
2309
        endcase
2310
        // Update the branch history
2311
        if (isxBranch) begin
2312
                gbl_branch_hist[xAXC] <= {gbl_branch_hist[xAXC],takb};
2313
                branch_history_table[bht_wa] <= xbits_new;
2314
        end
2315
end
2316
 
2317
//---------------------------------------------------------
2318
// RFETCH:
2319
// Register fetch stage
2320
//---------------------------------------------------------
2321
if (advanceR) begin
2322
        xirqf <= dirqf[dAXC];
2323
        xFip <= dFip[dAXC];
2324
        xextype <= dextype;
2325
        xAXC <= dAXC;
2326
        xIR <= dIR;
2327
        xpc <= dpc;
2328
        xbranch_taken <= dbranch_taken;
2329
        dbranch_taken <= 1'b0;
2330
        dextype <= `EX_NON;
2331
        if (dOpcode[6:4]!=`IMM) // IMM is "sticky"
2332
                dIR <= `NOP_INSN;
2333
        dRa <= 9'd0;
2334
        dRb <= 9'd0;
2335
 
2336
        // Result forward muxes
2337
        casex(dRa)
2338
        9'bxxxx00000:   a <= 64'd0;
2339
        xRt:    a <= xData;
2340
        m1Rt:   a <= m1Data;
2341
        m2Rt:   a <= m2Data;
2342
        m3Rt:   a <= m3Data;
2343
        m4Rt:   a <= m4Data;
2344
        wRt:    a <= wData;
2345
        tRt:    a <= tData;
2346
        default:        a <= rfoa;
2347
        endcase
2348
        casex(dRb)
2349
        9'bxxxx00000:   b <= 64'd0;
2350
        xRt:    b <= disRightShift ? -xData[5:0] : xData;
2351
        m1Rt:   b <= disRightShift ? -m1Data[5:0] : m1Data;
2352
        m2Rt:   b <= disRightShift ? -m2Data[5:0] : m2Data;
2353
        m3Rt:   b <= disRightShift ? -m3Data[5:0] : m3Data;
2354
        m4Rt:   b <= disRightShift ? -m4Data[5:0] : m4Data;
2355
        wRt:    b <= disRightShift ? -wData[5:0] : wData;
2356
        tRt:    b <= disRightShift ? -tData[5:0] : tData;
2357
        default:        b <= disRightShift ? -rfob[5:0] : rfob;
2358
        endcase
2359
        if (dOpcode==`SHFTI)
2360
                case(dFunc)
2361
                `RORI:          b <= {58'd0,~dIR[24:19]+6'd1};
2362
                default:        b <= {58'd0,dIR[24:19]};
2363
                endcase
2364
        casex(dRc)
2365
        9'bxxxx00000:   c <= 64'd0;
2366
        xRt:    c <= xData;
2367
        m1Rt:   c <= m1Data;
2368
        m2Rt:   c <= m2Data;
2369
        m3Rt:   c <= m3Data;
2370
        m4Rt:   c <= m4Data;
2371
        wRt:    c <= wData;
2372
        tRt:    c <= tData;
2373
        default:        c <= rfoc;
2374
        endcase
2375
 
2376
        // Set the target register
2377
        casex(dOpcode)
2378
        `SETLO:         xRt <= {dAXC,dIR[36:32]};
2379
        `SETHI:         xRt <= {dAXC,dIR[36:32]};
2380
        `RR:            xRt <= {dAXC,dIR[24:20]};
2381
        `BTRI:          xRt <= 9'd0;
2382
        `BTRR:          xRt <= 9'd0;
2383
        `TRAPcc:        xRt <= 9'd0;
2384
        `TRAPcci:       xRt <= 9'd0;
2385
        `JMP:           xRt <= 9'd00;
2386
        `CALL:          xRt <= {dAXC,5'd31};
2387
        `RET:           xRt <= {dAXC,dIR[24:20]};
2388
        `MEMNDX:
2389
                case(dFunc)
2390
                `SW,`SH,`SC,`SB,`OUTW,`OUTH,`OUTC,`OUTB:
2391
                                xRt <= 9'd0;
2392
                default:        xRt <= {dAXC,dIR[24:20]};
2393
                endcase
2394
        `SW,`SH,`SC,`SB,`OUTW,`OUTH,`OUTC,`OUTB:
2395
                                xRt <= 9'd0;
2396
        `NOPI:          xRt <= 9'd0;
2397
        `BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
2398
                                xRt <= 9'd0;
2399
        default:        xRt <= {dAXC,dIR[29:25]};
2400
        endcase
2401
        if (dOpcode[6:4]==`IMM)
2402
                xRt <= 9'd0;
2403
 
2404
        // Set immediate value
2405
        if (xOpcode[6:4]==`IMM) begin
2406
                imm <= {xIR[38:0],dIR[24:0]};
2407
        end
2408
        else
2409
                casex(dOpcode)
2410
                `SETLO: imm <= {{32{dIR[31]}},dIR[31:0]};
2411
                `SETHI: imm <= {dIR[31:0],32'h00000000};
2412
                `BTRI:  imm <= {{44{dIR[19]}},dIR[19:0]};
2413
                `BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
2414
                        imm <= {{46{dIR[17]}},dIR[17:0]};
2415
                `ANDI:  imm <= {39'h7FFFFFFFFF,dIR[24:0]};
2416
                `ORI:   imm <= {39'h0000000000,dIR[24:0]};
2417
                `XORI:  imm <= {39'h0000000000,dIR[24:0]};
2418
                `RET:   imm <= {44'h00000000000,dIR[19:0]};
2419
                `MEMNDX:        imm <= {{51{dIR[19]}},dIR[19:7]};
2420
                default:        imm <= {{39{dIR[24]}},dIR[24:0]};
2421
                endcase
2422
        case(dOpcode)
2423
 
2424
        `MISC:
2425
                case(dFunc)
2426
                `SEI:   im <= 1'b1;
2427
                `CLI:   im <= 1'b0;
2428
                endcase
2429
        endcase
2430
 
2431
end
2432
 
2433
//---------------------------------------------------------
2434
// IFETCH:
2435
// - check for external hardware interrupt
2436
// - fetch instruction
2437
// - increment PC
2438
// - set special register defaults for some instructions
2439
//---------------------------------------------------------
2440
if (advanceI) begin
2441
        dextype <= `EX_NON;
2442
        if (iOpcode[6:4]!=`IMM) begin
2443
                epcnt <= epcnt + 5'd1;
2444
                case(epcnt)
2445
                5'd0:   AXC <= EP[0][ 3: 0];
2446
                5'd1:   AXC <= EP[0][ 7: 4];
2447
                5'd2:   AXC <= EP[0][11: 8];
2448
                5'd3:   AXC <= EP[0][15:12];
2449
                5'd4:   AXC <= EP[0][19:16];
2450
                5'd5:   AXC <= EP[0][23:20];
2451
                5'd6:   AXC <= EP[0][27:24];
2452
                5'd7:   AXC <= EP[0][31:28];
2453
                5'd8:   AXC <= EP[1][ 3: 0];
2454
                5'd9:   AXC <= EP[1][ 7: 4];
2455
                5'd10:  AXC <= EP[1][11: 8];
2456
                5'd11:  AXC <= EP[1][15:12];
2457
                5'd12:  AXC <= EP[1][19:16];
2458
                5'd13:  AXC <= EP[1][23:20];
2459
                5'd14:  AXC <= EP[1][27:24];
2460
                5'd15:  AXC <= EP[1][31:28];
2461
                5'd16:  AXC <= EP[2][ 3: 0];
2462
                5'd17:  AXC <= EP[2][ 7: 4];
2463
                5'd18:  AXC <= EP[2][11: 8];
2464
                5'd19:  AXC <= EP[2][15:12];
2465
                5'd20:  AXC <= EP[2][19:16];
2466
                5'd21:  AXC <= EP[2][23:20];
2467
                5'd22:  AXC <= EP[2][27:24];
2468
                5'd23:  AXC <= EP[2][31:28];
2469
                5'd24:  AXC <= EP[3][ 3: 0];
2470
                5'd25:  AXC <= EP[3][ 7: 4];
2471
                5'd26:  AXC <= EP[3][11: 8];
2472
                5'd27:  AXC <= EP[3][15:12];
2473
                5'd28:  AXC <= EP[3][19:16];
2474
                5'd29:  AXC <= EP[3][23:20];
2475
                5'd30:  AXC <= EP[3][27:24];
2476
                5'd31:  AXC <= EP[3][31:28];
2477
                endcase
2478
        end
2479
//      AXC <= EP[epcnt[4:3]][{epcnt[2:0],2'b11}:{epcnt[2:0],2'b00}];
2480
 
2481
//  Interrupt won't be recognized if the context is already processing another
2482
//  exception
2483
        if (nmi_edge & !StatusHWI[AXC]) begin
2484
                StatusHWI[AXC] <= 1'b1;
2485
                IPC[AXC] <= pc_axc;
2486
                nmi_edge <= 1'b0;
2487
                dirqf[AXC] <= 1'b1;
2488
                dIR <= `NOP_INSN;
2489
                dextype <= `EX_NMI;
2490
        end
2491
        else if (irq_i & !im & !StatusHWI[AXC]) begin
2492
                StatusHWI[AXC] <= 1'b1;
2493
                IPC[AXC] <= pc_axc;
2494
                dirqf[AXC] <= 1'b1;
2495
                dIR <= `NOP_INSN;
2496
                dextype <= `EX_IRQ;
2497
        end
2498
        // Are we filling the pipeline with NOP's as a result of a previous
2499
        // hardware interrupt ? Only NOP out the pipeline for the context
2500
        // servicing the interrupt.
2501
        else if (dirqf[AXC]|dFip[AXC]) begin
2502
                dIR <= `NOP_INSN;
2503
        end
2504
        else if (ITLBMiss)
2505
                dIR <= `NOP_INSN;
2506
        else begin
2507
                dIR <= insn;
2508
`include "insn_dump.v"
2509
        end
2510
        nopI <= 1'b0;
2511
        if (dOpcode[6:4]!=`IMM) begin
2512
                dpc <= pc_axc;
2513
        end
2514
        dAXC <= AXC;
2515
        casex(iOpcode)
2516
        `SETLO:         dRa <= {AXC,insn[36:32]};
2517
        `SETHI:         dRa <= {AXC,insn[36:32]};
2518
        default:        dRa <= {AXC,insn[34:30]};
2519
        endcase
2520
        dRb <= {AXC,insn[29:25]};
2521
        dRc <= {AXC,insn[24:20]};
2522
        if (ITLBMiss) begin
2523
                CauseCode[AXC] <= `EX_TLBI;
2524
                StatusEXL[AXC] <= 1'b1;
2525
                BadVAddr[AXC] <= pc_axc[63:13];
2526
                pc[AXC] <= `ITLB_MissHandler;
2527
                EPC[AXC] <= pc_axc;
2528
        end
2529
        else begin
2530
                dbranch_taken <= 1'b0;
2531
                pc[AXC] <= fnIncPC(pc_axc);
2532
                case(iOpcode)
2533
                `MISC:
2534
                        case(iFunc)
2535
                        `FIP:   dFip[AXC] <= 1'b1;
2536
                        default:        ;
2537
                        endcase
2538
                `JMP,`CALL:
2539
                        begin
2540
                                dbranch_taken <= 1'b1;
2541
                                pc[AXC] <= jmp_tgt;
2542
                        end
2543
                `BTRR:
2544
                        case(insn[4:0])
2545
                        `BEQ,`BNE,`BLT,`BLE,`BGT,`BGE,`BLTU,`BLEU,`BGTU,`BGEU,`BAND,`BOR,`BNR:
2546
                                if (predict_taken) begin
2547
                                        $display("Taking predicted branch: %h",{pc_axc[63:4] + {{42{insn[24]}},insn[24:7]},insn[6:5],2'b00});
2548
                                        dbranch_taken <= 1'b1;
2549
                                        pc[AXC] <= {pc_axc[63:4] + {{42{insn[24]}},insn[24:7]},insn[6:5],2'b00};
2550
                                end
2551
                        default:        ;
2552
                        endcase
2553
                `BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
2554
                        begin
2555
                                if (predict_taken) begin
2556
                                        dbranch_taken <= 1'b1;
2557
                                        pc[AXC] <= {pc_axc[63:4] + {{50{insn[29]}},insn[29:20]},insn[19:18],2'b00};
2558
                                end
2559
                        end
2560
                `TRAPcc:        if (predict_taken) begin pc[AXC] <= {TBA[63:13],`GEN_TRAP_OFFSET}; dbranch_taken <= 1'b1; end
2561
                `TRAPcci:       if (predict_taken) begin pc[AXC] <= {TBA[63:13],`GEN_TRAP_OFFSET}; dbranch_taken <= 1'b1; end
2562
                default:        ;
2563
                endcase
2564
        end
2565
end
2566
 
2567
//`include "RPSTAGE.v"
2568
//---------------------------------------------------------
2569
// EXECUTE - part two:
2570
// - override the default program counter increment for
2571
//   control flow instructions
2572
// - NOP out the instructions following a branch in the
2573
//   pipeline
2574
//---------------------------------------------------------
2575
if (advanceX) begin
2576
        case(xOpcode)
2577
        `MISC:
2578
                case(xFunc)
2579
                `IRET:
2580
                        if (StatusHWI[xAXC]) begin
2581
                                pc[xAXC] <= IPC[xAXC];
2582
                                if (xAXC==AXC) begin
2583
                                        dpc <= EPC[xAXC];
2584
                                        dIR <= `NOP_INSN;
2585
                                end
2586
                                if (xAXC==dAXC) begin
2587
                                        xpc <= EPC[xAXC];
2588
                                        xIR <= `NOP_INSN;
2589
                                        xRt <= 9'd0;
2590
                                end
2591
                                StatusHWI[xAXC] <= 1'b0;
2592
                        end
2593
                `ERET:  begin
2594
                                        if (StatusEXL[xAXC]) begin
2595
                                                pc[xAXC] <= EPC[xAXC];
2596
                                                if (xAXC==AXC) begin
2597
                                                        dpc <= EPC[xAXC];
2598
                                                        dIR <= `NOP_INSN;
2599
                                                end
2600
                                                if (xAXC==dAXC) begin
2601
                                                        xpc <= EPC[xAXC];
2602
                                                        xIR <= `NOP_INSN;
2603
                                                        xRt <= 9'd0;
2604
                                                end
2605
                                        end
2606
                                        StatusEXL[xAXC] <= 1'b0;
2607
                                end
2608
                default:        ;
2609
                endcase
2610
        `BTRR:
2611
                case(xIR[4:0])
2612
        // BEQ r1,r2,label
2613
                `BEQ,`BNE,`BLT,`BLE,`BGT,`BGE,`BLTU,`BLEU,`BGTU,`BGEU,`BAND,`BOR,`BNR:
2614
                        if (takb & !xbranch_taken) begin
2615
                                $display("Taking branch %h",xpc[63:4] + {{42{xIR[24]}},xIR[24:7]});
2616
                                pc[xAXC][63:4] <= xpc[63:4] + {{42{xIR[24]}},xIR[24:7]};
2617
                                pc[xAXC][3:2] <= xIR[6:5];
2618
                                if (xAXC==AXC) begin
2619
                                        dpc[63:4] <= xpc[63:4] + {{42{xIR[24]}},xIR[24:7]};
2620
                                        dpc[3:2] <= xIR[6:5];
2621
                                        dIR <= `NOP_INSN;
2622
                                end
2623
                                if (xAXC==dAXC) begin
2624
                                        xpc[63:4] <= xpc[63:4] + {{42{xIR[24]}},xIR[24:7]};
2625
                                        xpc[3:2] <= xIR[6:5];
2626
                                        xIR <= `NOP_INSN;
2627
                                        xRt <= 9'd0;
2628
                                end
2629
                        end
2630
                        else if (!takb & xbranch_taken) begin
2631
                                $display("Fixing branch misprediction %h",fnIncPC(xpc));
2632
                                pc[xAXC] <= fnIncPC(xpc);
2633
                                if (xAXC==AXC) begin
2634
                                        dpc <= fnIncPC(xpc);
2635
                                        dIR <= `NOP_INSN;
2636
                                end
2637
                                if (xAXC==dAXC) begin
2638
                                        xpc <= fnIncPC(xpc);
2639
                                        xIR <= `NOP_INSN;
2640
                                        xRt <= 9'd0;
2641
                                end
2642
                        end
2643
        // BEQ r1,r2,r10
2644
                `BEQR,`BNER,`BLTR,`BLER,`BGTR,`BGER,`BLTUR,`BLEUR,`BGTUR,`BGEUR://,`BANDR,`BORR,`BNRR:
2645
                        if (takb) begin
2646
                                pc[xAXC][63:2] <= c[63:2];
2647
                                pc[xAXC][1:0] <= 2'b00;
2648
                                if (xAXC==AXC) begin
2649
                                        dpc[63:2] <= c[63:2];
2650
                                        dpc[1:0] <= 2'b00;
2651
                                        dIR <= `NOP_INSN;
2652
                                end
2653
                                if (dAXC==xAXC) begin
2654
                                        xpc[63:2] <= c[63:2];
2655
                                        xpc[1:0] <= 2'b00;
2656
                                        xIR <= `NOP_INSN;
2657
                                        xRt <= 9'd0;
2658
                                end
2659
                        end
2660
                default:        ;
2661
                endcase
2662
        // JMP and CALL change the program counter immediately in the IF stage.
2663
        // There's no work to do here. The pipeline does not need to be cleared.
2664
        `JMP:   ;
2665
        `CALL:  ;
2666
        `JAL:   begin
2667
                                pc[xAXC][63:2] <= a[63:2] + imm[63:2];
2668
                                if (AXC==xAXC) begin
2669
                                        dIR <= `NOP_INSN;
2670
                                        dpc[63:2] <= a[63:2] + imm[63:2];
2671
                                end
2672
                                if (dAXC==xAXC) begin
2673
                                        xpc[63:2] <= a[63:2] + imm[63:2];
2674
                                        xIR <= `NOP_INSN;
2675
                                        xRt <= 9'd0;
2676
                                end
2677
                        end
2678
        `RET:   begin
2679
                                pc[xAXC][63:2] <= b[63:2];
2680
                                $display("returning to: %h", {b,2'b00});
2681
                                if (AXC==xAXC) begin
2682
                                        dpc[63:2] <= b[63:2];
2683
                                        dIR <= `NOP_INSN;
2684
                                end
2685
                                if (xAXC==dAXC) begin
2686
                                        xpc[63:2] <= b[63:2];
2687
                                        xIR <= `NOP_INSN;
2688
                                        xRt <= 9'd0;
2689
                                end
2690
                        end
2691
        // BEQ r1,#3,r10
2692
        `BTRI:
2693
                if (takb) begin
2694
                        pc[xAXC][63:2] <= b[63:2];
2695
                        pc[xAXC][1:0] <= 2'b00;
2696
                        if (xAXC==AXC) begin
2697
                                dpc[63:2] <= b[63:2];
2698
                                dpc[1:0] <= 2'b00;
2699
                                dIR <= `NOP_INSN;
2700
                        end
2701
                        if (dAXC==xAXC) begin
2702
                                xpc[63:2] <= b[63:2];
2703
                                xpc[1:0] <= 2'b00;
2704
                                xIR <= `NOP_INSN;
2705
                                xRt <= 9'd0;
2706
                        end
2707
                end
2708
        // BEQI r1,#3,label
2709
        `BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
2710
                if (takb) begin
2711
                        if (!xbranch_taken) begin
2712
                                pc[xAXC][63:4] <= xpc[63:4] + {{50{xIR[29]}},xIR[29:20]};
2713
                                pc[xAXC][3:2] <= xIR[19:18];
2714
                                if (AXC==xAXC) begin
2715
                                        dpc[63:4] <= xpc[63:4] + {{50{xIR[29]}},xIR[29:20]};
2716
                                        dpc[3:2] <= xIR[19:18];
2717
                                        dIR <= `NOP_INSN;
2718
                                end
2719
                                if (dAXC==xAXC) begin
2720
                                        xpc[63:4] <= xpc[63:4] + {{50{xIR[29]}},xIR[29:20]};
2721
                                        xpc[3:2] <= xIR[19:18];
2722
                                        xIR <= `NOP_INSN;
2723
                                        xRt <= 9'd0;
2724
                                end
2725
                        end
2726
                end
2727
                else begin
2728
                        if (xbranch_taken) begin
2729
                                pc[xAXC] <= fnIncPC(xpc);
2730
                                if (AXC==xAXC) begin
2731
                                        dpc <= fnIncPC(xpc);
2732
                                        dIR <= `NOP_INSN;
2733
                                end
2734
                                if (dAXC==xAXC) begin
2735
                                        xpc <= fnIncPC(xpc);
2736
                                        xIR <= `NOP_INSN;
2737
                                        xRt <= 9'd0;
2738
                                end
2739
                        end
2740
                end
2741
        `TRAPcc,`TRAPcci:
2742
                if (takb) begin
2743
                        StatusEXL[xAXC] <= 1'b1;
2744
                        CauseCode[xAXC] <= `EX_TRAP;
2745
                        EPC[xAXC] <= xpc;
2746
                        if (!xbranch_taken) begin
2747
                                pc[xAXC] <= {TBA[63:13],`GEN_TRAP_OFFSET};
2748
                                if (xAXC==AXC) begin
2749
                                        dpc <= {TBA[63:13],`GEN_TRAP_OFFSET};
2750
                                        dIR <= `NOP_INSN;
2751
                                end
2752
                                if (xAXC==dAXC) begin
2753
                                        xpc <= {TBA[63:13],`GEN_TRAP_OFFSET};
2754
                                        xIR <= `NOP_INSN;
2755
                                        xRt <= 9'd0;
2756
                                end
2757
                        end
2758
                end
2759
                else begin
2760
                        if (xbranch_taken) begin
2761
                                pc[xAXC] <= fnIncPC(xpc);
2762
                                if (xAXC==AXC) begin
2763
                                        dpc <= fnIncPC(xpc);
2764
                                        dIR <= `NOP_INSN;
2765
                                end
2766
                                if (xAXC==dAXC) begin
2767
                                        xpc <= fnIncPC(xpc);
2768
                                        xIR <= `NOP_INSN;
2769
                                        xRt <= 9'd0;
2770
                                end
2771
                        end
2772
                end
2773
        default:        ;
2774
        endcase
2775
        if (dbz_error) begin
2776
                $display("Divide by zero error");
2777
                CauseCode[xAXC] <= `EX_DBZ;
2778
                StatusEXL[xAXC] <= 1'b1;
2779
                EPC[xAXC] <= xpc;
2780
                pc[xAXC] <= {TBA[63:13],`DBZ_TRAP_OFFSET};
2781
                if (xAXC==AXC) begin
2782
                        dpc <= {TBA[63:13],`DBZ_TRAP_OFFSET};
2783
                        dIR <= `NOP_INSN;
2784
                end
2785
                if (xAXC==dAXC) begin
2786
                        xpc <= {TBA[63:13],`DBZ_TRAP_OFFSET};
2787
                        xIR <= `NOP_INSN;
2788
                        xRt <= 9'd0;
2789
                end
2790
        end
2791
        if (ovr_error) begin
2792
                $display("Overflow error");
2793
                CauseCode[xAXC] <= `EX_OFL;
2794
                StatusEXL[xAXC] <= 1'b1;
2795
                EPC[xAXC] <= xpc;
2796
                pc[xAXC] <= {TBA[63:13],`OFL_TRAP_OFFSET};
2797
                if (xAXC==AXC) begin
2798
                        dpc <= {TBA[63:13],`OFL_TRAP_OFFSET};
2799
                        dIR <= `NOP_INSN;
2800
                end
2801
                if (xAXC==dAXC) begin
2802
                        xpc <= {TBA[63:13],`OFL_TRAP_OFFSET};
2803
                        xIR <= `NOP_INSN;
2804
                        xRt <= 9'd0;
2805
                end
2806
        end
2807
end
2808
 
2809
//---------------------------------------------------------
2810
// MEMORY1 (M1') - part two:
2811
// Check for a TLB miss.
2812
//---------------------------------------------------------
2813
if (advanceM1) begin
2814
        if (m1IsLoad|m1IsStore) begin
2815
                if (DTLBMiss) begin
2816
                        $display("DTLB miss on address: %h",ea);
2817
                        m1extype <= `EX_TLBD;
2818
                        CauseCode[m1AXC] <= `EX_TLBD;
2819
                        StatusEXL[m1AXC] <= 1'b1;
2820
                        BadVAddr[m1AXC] <= ea[63:13];
2821
                        EPC[m1AXC] <= m1pc;
2822
                        pc[m1AXC] <= `DTLB_MissHandler;
2823
                        if (m1AXC==xAXC) begin
2824
                                m1pc <= `DTLB_MissHandler;
2825
                                m1Opcode <= `NOPI;
2826
                                m1Rt <= 9'd0;
2827
                        end
2828
                        if (m1AXC==dAXC) begin
2829
                                xpc <= `DTLB_MissHandler;
2830
                                xIR <= `NOP_INSN;
2831
                                xRt <= 9'd0;
2832
                        end
2833
                        if (m1AXC==AXC) begin
2834
                                dpc <= `DTLB_MissHandler;
2835
                                dIR <= `NOP_INSN;
2836
                        end
2837
                end
2838
        end
2839
end
2840
 
2841
//---------------------------------------------------------
2842
// MEMORY2 (M2')
2843
//---------------------------------------------------------
2844
if (advanceM2) begin
2845
end
2846
 
2847
//---------------------------------------------------------
2848
// MEMORY4 (M3')
2849
//---------------------------------------------------------
2850
if (advanceM3) begin
2851
end
2852
 
2853
//---------------------------------------------------------
2854
// MEMORY4 (M4')
2855
// - no exceptions
2856
//---------------------------------------------------------
2857
if (advanceM4) begin
2858
end
2859
 
2860
//---------------------------------------------------------
2861
// WRITEBACK (WB') - part two:
2862
// - vector to exception handler address
2863
// In the case of a hardware interrupt (NMI/IRQ) we know
2864
// the pipeline following the interrupt is filled with
2865
// NOP instructions. This means there is no need to 
2866
// invalidate the pipeline.
2867
//---------------------------------------------------------
2868
if (advanceW) begin
2869
        case(wextype)
2870
        `EX_RST:        pc[wAXC] <= `RESET_VECTOR;
2871
        `EX_NMI:        pc[wAXC] <= `NMI_VECTOR;
2872
        `EX_IRQ:        pc[wAXC] <= `IRQ_VECTOR;
2873
        default:        ;//pc[63:2] <= exception_address[63:2];
2874
        endcase
2875
end
2876
 
2877
 
2878
//---------------------------------------------------------
2879
// Cache loader
2880
//---------------------------------------------------------
2881
if (rst_i) begin
2882
        cstate <= IDLE;
2883
//      wr_icache <= 1'b0;
2884
        wr_dcache <= 1'b0;
2885
end
2886
else begin
2887
//wr_icache <= 1'b0;
2888
wr_dcache <= 1'b0;
2889
case(cstate)
2890
IDLE:
2891
        // we can't do anything until the command buffer is available
2892
        // in theory the command fifo should always be available
2893
        if (!cmd_full) begin
2894
                if (triggerDCacheLoad) begin
2895
                        dcaccess <= 1'b1;
2896
                        cmd_en <= 1'b1;
2897
                        cmd_instr <= 3'b001;    // READ
2898
                        cmd_byte_addr <= {pea[29:5],5'b00000};
2899
                        dadr_o <= {pea[63:5],5'b00000};
2900
                        cmd_bl <= 6'd8; // Eight words per cache line
2901
                        cstate <= DCACT;
2902
                end
2903
                else if (triggerICacheLoad) begin
2904
                        if (!ppc[63]) begin
2905
                                icaccess <= 1'b1;
2906
                                cmd_en <= 1'b1; // the command fifo should always be available
2907
                                cmd_instr <= 3'b001;    // READ
2908
                                cmd_byte_addr <= {ppc[29:6],6'h00};
2909
                                iadr_o <= {ppc[63:6],6'h00};
2910
                                cmd_bl <= 6'd16;        // Sixteen words per cache line
2911
                                cstate <= ICACT;
2912
                        end
2913
                        else begin
2914
                                iciaccess <= 1'b1;
2915
                                bte_o <= 2'b00;                 // linear burst
2916
                                cti_o <= 3'b010;                // burst access
2917
                                cyc_o <= 1'b1;
2918
                                stb_o <= 1'b1;
2919
                                adr_o <= {ppc[63:6],6'h00};
2920
                                iadr_o <= {ppc[63:6],6'h00};
2921
                                cstate <= ICACT1;
2922
                        end
2923
                end
2924
        end
2925
        // Sometime after the read command is issued, the read fifo will begin to fill
2926
ICACT:
2927
        begin
2928
                rd_en <= 1'b1;
2929
                cstate <= ICACT0;
2930
        end
2931
//ICACT0:       // Read word 0
2932
        // At this point it should not be necessary to check rd_empty
2933
//      if (!rd_empty) begin
2934
//              wr_icache <= 1'b1;
2935
//              idat <= rd_data;
2936
//              cstate <= ICACT1;
2937
//      end
2938
 
2939
ICACT0: // Read word 1-15
2940
        // Might have to wait for subsequent data to be available
2941
        if (!rd_empty) begin
2942
//              wr_icache <= 1'b1;
2943
//              idat <= rd_data;
2944
                iadr_o[5:2] <= iadr_o[5:2] + 4'h1;
2945
                if (iadr_o[5:2]==4'hF) begin
2946
                        rd_en <= 1'b0;
2947
                        tmem[iadr_o[12:6]] <= {1'b1,iadr_o[63:13]};     // This will cause ihit to go high
2948
                        tvalid[iadr_o[12:6]] <= 1'b1;
2949
                        cstate <= ICDLY;
2950
                end
2951
        end
2952
ICDLY:
2953
        // The fifo should have emptied out, if not we force it to empty
2954
        if (!rd_empty) begin
2955
                rd_en <= 1'b1;
2956
        end
2957
        else begin
2958
                icaccess <= 1'b0;
2959
                rd_en <= 1'b0;
2960
                cstate <= IDLE;
2961
        end
2962
 
2963
// WISHBONE burst accesses
2964
//
2965
ICACT1:
2966
        if (ack_i) begin
2967
                adr_o[5:2] <= adr_o[5:2] + 4'd1;
2968
                iadr_o[5:2] <= iadr_o[5:2] + 4'd1;
2969
                if (adr_o[5:2]==4'hE)
2970
                        cti_o <= 3'b111;        // Last cycle ahead
2971
                if (adr_o[5:2]==4'hF) begin
2972
                        cti_o <= 3'b000;        // back to non-burst mode
2973
                        cyc_o <= 1'b0;
2974
                        stb_o <= 1'b0;
2975
                        tmem[iadr_o[12:6]] <= {1'b1,iadr_o[63:13]};     // This will cause ihit to go high
2976
                        tvalid[iadr_o[12:6]] <= 1'b1;
2977
                        iciaccess <= 1'b0;
2978
                        cstate <= IDLE;
2979
                end
2980
        end
2981
 
2982
DCACT:
2983
        begin
2984
                rd_en <= 1'b1;          // Data should be available on the next clock cycle
2985
                cstate <= DCACT0;
2986
        end
2987
DCACT0: // Read word 0
2988
        // At this point it should not be necessary to check rd_empty
2989
        if (!rd_empty) begin
2990
                wr_dcache <= 1'b1;
2991
                ddat <= rd_data;
2992
                dadr_o[4:2] <= 3'b000;
2993
                cstate <= DCACT1;
2994
        end
2995
DCACT1: // Read word 1
2996
        // Might have to wait for subsequent data to be available
2997
        if (!rd_empty) begin
2998
                wr_dcache <= 1'b1;
2999
                ddat <= rd_data;
3000
                dadr_o[4:2] <= dadr_o[4:2]+3'd1;
3001
                if (dadr_o[4:2]==3'b111) begin
3002
                        rd_en <= 1'b0;
3003
                        cstate <= DCDLY;
3004
                end
3005
        end
3006
DCDLY:
3007
        // The fifo should have emptied out, if not, empty it out.
3008
        if (!rd_empty) begin
3009
                rd_en <= 1'b1;
3010
        end
3011
        else begin
3012
                dcaccess <= 1'b0;
3013
                rd_en <= 1'b0;
3014
                cstate <= IDLE;
3015
        end
3016
endcase
3017
end
3018
 
3019
end
3020
 
3021
endmodule

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