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robfinch |
/* ===============================================================
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(C) 2006 Robert Finch
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All rights reserved.
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rob@birdcomputer.ca
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fpLOOUnit.v
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- 'latency of one' floating point unit
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- instructions can execute using a single cycle
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- issue rate is one per clock cycle
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- latency is one clock cycle
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- parameterized width
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- IEEE 754 representation
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This source code is free for use and modification for
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non-commercial or evaluation purposes, provided this
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copyright statement and disclaimer remains present in
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the file.
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If the code is modified, please state the origin and
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note that the code has been modified.
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NO WARRANTY.
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THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF
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ANY KIND, WHETHER EXPRESS OR IMPLIED. The user must assume
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the entire risk of using the Work.
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IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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ANY INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES
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WHATSOEVER RELATING TO THE USE OF THIS WORK, OR YOUR
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RELATIONSHIP WITH THE AUTHOR.
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IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU
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TO USE THE WORK IN APPLICATIONS OR SYSTEMS WHERE THE
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WORK'S FAILURE TO PERFORM CAN REASONABLY BE EXPECTED
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TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN LOSS
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OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK,
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AND YOU AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS
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FROM ANY CLAIMS OR LOSSES RELATING TO SUCH UNAUTHORIZED
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USE.
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i2f - convert integer to floating point
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f2i - convert floating point to integer
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Ref: Webpack 8.1i Spartan3-4 xc3s1000 4ft256
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61 LUTS / 34 slices / 16 ns
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=============================================================== */
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module fpLOOUnit
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#(parameter WID=32)
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(
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input clk,
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input ce,
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input [1:0] rm,
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input [5:0] op,
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input [WID:1] a,
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output reg [WID:1] o,
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output done
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);
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localparam MSB = WID-1;
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localparam EMSB = WID==80 ? 14 :
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WID==64 ? 10 :
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WID==52 ? 10 :
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WID==48 ? 10 :
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WID==44 ? 10 :
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WID==42 ? 10 :
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WID==40 ? 9 :
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WID==32 ? 7 :
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WID==24 ? 6 : 4;
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localparam FMSB = WID==80 ? 63 :
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WID==64 ? 51 :
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WID==52 ? 39 :
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WID==48 ? 35 :
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WID==44 ? 31 :
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WID==42 ? 29 :
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WID==40 ? 28 :
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WID==32 ? 22 :
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WID==24 ? 15 : 9;
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wire [WID:1] i2f_o;
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wire [WID:1] f2i_o;
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delay1 u1 (.clk(clk), .ce(ce), .i(op==6'd13||op==6'd14), .o(done) );
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i2f i2f0 (.clk(clk), .ce(ce), .rm(rm), .i(a), .o(i2f_o) );
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f2i f2i0 (.clk(clk), .ce(ce), .i(a), .o(f2i_o) );
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always @(op,a,i2f_o,f2i_o)
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case (op)
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6'd13: o <= i2f_o;
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6'd14: o <= f2i_o;
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default: o <= 0;
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endcase
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endmodule
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