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robfinch |
/* ===============================================================
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(C) 2007 Robert T Finch
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All rights reserved.
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rob@birdcomputer.ca
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fpZLUnit.v
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- zero latency floating point unit
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- instructions can execute in a single cycle without
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a clock
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- parameterized width
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- IEEE 754 representation
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This source code is free for use and modification for
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non-commercial or evaluation purposes, provided this
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copyright statement and disclaimer remains present in
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the file.
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If the code is modified, please state the origin and
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note that the code has been modified.
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NO WARRANTY.
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THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF
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ANY KIND, WHETHER EXPRESS OR IMPLIED. The user must assume
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the entire risk of using the Work.
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IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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ANY INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES
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WHATSOEVER RELATING TO THE USE OF THIS WORK, OR YOUR
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RELATIONSHIP WITH THE AUTHOR.
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IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU
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TO USE THE WORK IN APPLICATIONS OR SYSTEMS WHERE THE
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WORK'S FAILURE TO PERFORM CAN REASONABLY BE EXPECTED
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TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN LOSS
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OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK,
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AND YOU AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS
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FROM ANY CLAIMS OR LOSSES RELATING TO SUCH UNAUTHORIZED
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USE.
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fabs - get absolute value of number
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fnabs - get negative absolute value of number
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fneg - negate number
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fmov - copy input to output
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fsign - get sign of number (set number to +1,0, or -1)
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fman - get mantissa (set exponent to zero)
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fclt - less than
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fcle - less than or equal
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fcgt - greater than
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fcge - greater than or equal
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fceq - equal
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fcne - not equal
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fcor - ordered
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fcun - unordered
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Ref: Webpack 8.1i Spartan3-4 xc3s1000 4ft256
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160 LUTS / 80 slices / 21 ns
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=============================================================== */
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`define FABS 6'd0
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`define FNABS 6'd1
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`define FNEG 6'd2
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`define FMOV 6'd3
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`define FSIGN 6'd4
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`define FMAN 6'd5
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module fpZLUnit
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#(parameter WID=32)
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(
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input [5:0] op,
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input [WID:1] a,
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input [WID:1] b, // for fcmp
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output reg [WID:1] o,
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output nanx
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);
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localparam MSB = WID-1;
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localparam EMSB = WID==80 ? 14 :
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WID==64 ? 10 :
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WID==52 ? 10 :
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WID==48 ? 10 :
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WID==44 ? 10 :
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WID==42 ? 10 :
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WID==40 ? 9 :
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WID==32 ? 7 :
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WID==24 ? 6 : 4;
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localparam FMSB = WID==80 ? 63 :
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WID==64 ? 51 :
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WID==52 ? 39 :
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WID==48 ? 35 :
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WID==44 ? 31 :
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WID==42 ? 29 :
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WID==40 ? 28 :
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WID==32 ? 22 :
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WID==24 ? 15 : 9;
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wire az = a[WID-1:1]==0;
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wire cmp_o;
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fp_cmp_unit #(WID) u1 (.op(op[2:0]), .a(a), .b(b), .o(cmp_o), .nanx(nanx) );
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always @(op,a,cmp_o,az)
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case (op)
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`FABS: o <= {1'b0,a[WID-1:1]}; // fabs
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`FNABS: o <= {1'b1,a[WID-1:1]}; // fnabs
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`FNEG: o <= {~a[WID],a[WID-1:1]}; // fneg
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`FMOV: o <= a; // fmov
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`FSIGN: o <= az ? 0 : {a[WID],1'b0,{EMSB{1'b1}},{FMSB+1{1'b0}}}; // fsign
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`FMAN: o <= {a[WID],1'b0,{EMSB{1'b1}},a[FMSB:1]}; // fman
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default: o <= cmp_o;
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endcase
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endmodule
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