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[/] [raptor64/] [trunk/] [rtl/] [verilog/] [fp/] [fp_cmp_unit.v] - Blame information for rev 3

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1 3 robfinch 
/* ============================================================================
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        (C) 2007  Robert T Finch
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        All rights reserved.
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        rob@birdcomputer.ca
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        fp_cmp_unit.v
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                - floating point comparison unit
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                - parameterized width
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                - IEEE 754 representation
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        Verilog 2001
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        Notice of Confidentiality
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        http://en.wikipedia.org/wiki/IEEE_754
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        Ref: Webpack 8.1i Spartan3-4 xc3s1000-4ft256
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        111 LUTS / 58 slices / 16 ns
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        Ref: Webpack 8.1i Spartan3-4 xc3s1000-4ft256
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        109 LUTS / 58 slices / 16.4 ns
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============================================================================ */
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`define FCLT            3'd0
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`define FCGE            3'd1
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`define FCLE            3'd2
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`define FCGT            3'd3
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`define FCEQ            3'd4
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`define FCNE            3'd5
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`define FCUN            3'd6
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`define FCOR            3'd7
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module fp_cmp_unit(op, a, b, o, nanx);
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parameter WID = 32;
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localparam MSB = WID-1;
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localparam EMSB = WID==80 ? 14 :
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                  WID==64 ? 10 :
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                                  WID==52 ? 10 :
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                                  WID==48 ? 10 :
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                                  WID==44 ? 10 :
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                                  WID==42 ? 10 :
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                                  WID==40 ?  9 :
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                                  WID==32 ?  7 :
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                                  WID==24 ?  6 : 4;
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localparam FMSB = WID==80 ? 63 :
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                  WID==64 ? 51 :
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                                  WID==52 ? 39 :
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                                  WID==48 ? 35 :
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                                  WID==44 ? 31 :
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                                  WID==42 ? 29 :
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                                  WID==40 ? 28 :
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                                  WID==32 ? 22 :
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                                  WID==24 ? 15 : 9;
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input [2:0] op;
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input [WID-1:0] a, b;
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output o;
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reg o;
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output nanx;
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// Decompose the operands
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wire sa;
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wire sb;
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wire [EMSB:0] xa;
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wire [EMSB:0] xb;
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wire [FMSB:0] ma;
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wire [FMSB:0] mb;
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wire az, bz;
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wire nan_a, nan_b;
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fp_decomp #(WID) u1(.i(a), .sgn(sa), .exp(xa), .man(ma), .vz(az), .qnan(), .snan(), .nan(nan_a) );
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fp_decomp #(WID) u2(.i(b), .sgn(sb), .exp(xb), .man(mb), .vz(bz), .qnan(), .snan(), .nan(nan_b) );
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wire unordered = nan_a | nan_b;
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wire eq = (az & bz) || (a==b);  // special test for zero, ugh!
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wire gt1 = {xa,ma} > {xb,mb};
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wire lt1 = {xa,ma} < {xb,mb};
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wire lt = sa ^ sb ? sa & !(az & bz): sa ? gt1 : lt1;
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always @(op or unordered or eq or lt)
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        case (op)       // synopsys full_case parallel_case
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        `FCOR:  o = !unordered;
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        `FCUN:  o =  unordered;
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        `FCEQ:  o =  eq;
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        `FCNE:  o = !eq;
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        `FCLT:  o =  lt;
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        `FCGE:  o = !lt;
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        `FCLE:  o =  lt | eq;
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        `FCGT:  o = !(lt | eq);
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        endcase
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// an unorder comparison will signal a nan exception
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assign nanx = op!=`FCOR && op!=`FCUN && unordered;
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endmodule

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