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[/] [raptor64/] [trunk/] [rtl/] [verilog/] [lib/] [math/] [BCDMath.v] - Blame information for rev 41

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1 41 robfinch
`timescale 1ns / 1ps
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//=============================================================================
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//        __
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//   \\__/ o\    (C) 2012  Robert Finch
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@opencores.org
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//       ||
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//  
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//      BCDMath.v
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//
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//  
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//                                                                          
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//
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//=============================================================================
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//
28 3 robfinch
module BCDAdd(ci,a,b,o,c);
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input ci;               // carry input
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input [7:0] a;
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input [7:0] b;
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output [7:0] o;
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output c;
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wire c0,c1;
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wire [4:0] hsN0 = a[3:0] + b[3:0] + ci;
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wire [4:0] hsN1 = a[7:4] + b[7:4] + c0;
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BCDAddAdjust u1 (hsN0,o[3:0],c0);
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BCDAddAdjust u2 (hsN1,o[7:4],c);
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endmodule
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module BCDSub(ci,a,b,o,c);
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input ci;               // carry input
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input [7:0] a;
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input [7:0] b;
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output [7:0] o;
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output c;
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wire c0,c1;
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wire [4:0] hdN0 = a[3:0] - b[3:0] - ci;
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wire [4:0] hdN1 = a[7:4] - b[7:4] - c0;
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BCDSubAdjust u1 (hdN0,o[3:0],c0);
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BCDSubAdjust u2 (hdN1,o[7:4],c);
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endmodule
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module BCDAddAdjust(i,o,c);
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input [4:0] i;
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output [3:0] o;
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reg [3:0] o;
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output c;
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reg c;
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always @(i)
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case(i)
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5'h0: begin o = 4'h0; c = 1'b0; end
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5'h1: begin o = 4'h1; c = 1'b0; end
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5'h2: begin o = 4'h2; c = 1'b0; end
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5'h3: begin o = 4'h3; c = 1'b0; end
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5'h4: begin o = 4'h4; c = 1'b0; end
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5'h5: begin o = 4'h5; c = 1'b0; end
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5'h6: begin o = 4'h6; c = 1'b0; end
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5'h7: begin o = 4'h7; c = 1'b0; end
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5'h8: begin o = 4'h8; c = 1'b0; end
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5'h9: begin o = 4'h9; c = 1'b0; end
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5'hA: begin o = 4'h0; c = 1'b1; end
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5'hB: begin o = 4'h1; c = 1'b1; end
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5'hC: begin o = 4'h2; c = 1'b1; end
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5'hD: begin o = 4'h3; c = 1'b1; end
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5'hE: begin o = 4'h4; c = 1'b1; end
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5'hF: begin o = 4'h5; c = 1'b1; end
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5'h10:  begin o = 4'h6; c = 1'b1; end
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5'h11:  begin o = 4'h7; c = 1'b1; end
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5'h12:  begin o = 4'h8; c = 1'b1; end
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5'h13:  begin o = 4'h9; c = 1'b1; end
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default:        begin o = 4'h9; c = 1'b1; end
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endcase
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endmodule
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module BCDSubAdjust(i,o,c);
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input [4:0] i;
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output [3:0] o;
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reg [3:0] o;
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output c;
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reg c;
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always @(i)
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case(i)
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5'h0: begin o = 4'h0; c = 1'b0; end
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5'h1: begin o = 4'h1; c = 1'b0; end
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5'h2: begin o = 4'h2; c = 1'b0; end
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5'h3: begin o = 4'h3; c = 1'b0; end
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5'h4: begin o = 4'h4; c = 1'b0; end
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5'h5: begin o = 4'h5; c = 1'b0; end
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5'h6: begin o = 4'h6; c = 1'b0; end
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5'h7: begin o = 4'h7; c = 1'b0; end
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5'h8: begin o = 4'h8; c = 1'b0; end
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5'h9: begin o = 4'h9; c = 1'b0; end
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5'h16: begin 0 = 4'h0; c = 1'b1; end
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5'h17: begin o = 4'h1; c = 1'b1; end
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5'h18: begin o = 4'h2; c = 1'b1; end
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5'h19: begin o = 4'h3; c = 1'b1; end
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5'h1A: begin o = 4'h4; c = 1'b1; end
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5'h1B: begin o = 4'h5; c = 1'b1; end
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5'h1C: begin o = 4'h6; c = 1'b1; end
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5'h1D: begin o = 4'h7; c = 1'b1; end
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5'h1E: begin o = 4'h8; c = 1'b1; end
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5'h1F: begin o = 4'h9; c = 1'b1; end
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default: begin o = 4'h9; c = 1'b1; end
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endcase
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endmodule

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