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[/] [raptor64/] [trunk/] [rtl/] [verilog/] [lib/] [rol.v] - Blame information for rev 26

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1 3 robfinch
//=============================================================================
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//      (C) 2006-2011  Robert Finch
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//      All rights reserved.
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//      robfinch@opencores.org
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//
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//      rol.v
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//              Rotate or shift left by up to 64 bits.
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//
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//                                                                          
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//      Funnel rotater / shifter
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//      Rotate, arithmetic shift left, or logical shift /
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//      arithmetic shift right by 0 to 63 bits.
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//      Parameterized with a default width of 32 bits.
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//
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//=============================================================================
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//
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// op
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//      0        shift left
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//      1       rotate left
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module rol
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#(parameter WID = 32)
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(
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input op,
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input [WID:1] a,
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input [5:0] b,
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output [WID:1] o
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);
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wire [WID:1] t1, t2, t3;
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assign o = t3;
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rolx1  #(WID) u1 (op,  a, b[1:0], t1);
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rolx4  #(WID) u2 (op, t1, b[3:2], t2);
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rolx16 #(WID) u3 (op, t2, b[5:4], t3);
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endmodule
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