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[/] [raptor64/] [trunk/] [rtl/] [verilog/] [lib/] [rolx1.v] - Blame information for rev 3

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1 3 robfinch
//=============================================================================
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//      (C) 2006-2011  Robert Finch
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//      All rights reserved.
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//      robfinch@opencores.org
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//
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//      rolx1.v
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//              Rotate or shift to the left by zero, one, two or
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//      three bits.
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//
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//
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//                                                                          
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//      Funnel rotater / shifter
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//      Rotate, arithmetic shift left, or logical shift /
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//      arithmetic shift right by 0 to 63 bits.
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//      Parameterized with a default width of 32 bits.
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//
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//
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//      Rotate or shift left by 0 to 3 bits.
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//      Parameterized with a default width of 32 bits.
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//
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//      Resource Usage Samples:
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//      Ref. SpartanII
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//      64 LUTs
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//      
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//      Webpack 7.1i xc3s1000-4ft256
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//      64 LUTs / 32 slices / 11 ns             (32 bits)
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//=============================================================================
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//
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module rolx1
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#(parameter WID = 32)
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(
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input op,                                       // 0=shift, 1= rotate
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input [WID:1] a,
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input [1:0] b,
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output reg [WID:1] o
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);
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wire [2:0] opx = {3{op}};
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always @(a, b, opx)
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begin
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        case(b)
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        2'd0:   o <= a;
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        2'd1:   o <= {a[WID-1:1],a[WID]&opx[0]};
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        2'd2:   o <= {a[WID-2:1],a[WID:WID-1]&opx[1:0]};
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        2'd3:   o <= {a[WID-3:1],a[WID:WID-2]&opx[2:0]};
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        endcase
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end
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endmodule

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